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Import of gcc 4.5.4. The (possibly incomplete) list of fixed bugs is

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50617 [4.5/4.6/4.7 Regression] ICE: RTL flag check: INSN_ANNULLED_BRANCH_P used with unexpected rtx code 'simplify_immed_subreg' in output_bb, at config/pa/pa.c:6631
  45383 [4.5 Regression] Implicit conversion to pointer does no longer automatically generate operator== and operator!=.
  45606 [4.5 Regression] match a method prototyped a typedef alias with the original type (using stdlib)
  47398 [4.5 Regression] tree check: accessed elt 10 of tree_vec with 9 elts in tsubst, at cp/pt.c:10500
  49951 [4.5/4.6/4.7 Regression] Debug stepping behavior regarding g++ Class destructor has changed for the worse starting at gcc 4.5.0
  43190 [4.4 Regression] Used pointer typedefs eliminated from debug info
  43866 [4.4 Regression] wrong code with -fbounds-check -funswitch-loops
  43897 [4.4 Regression] IA-64 asm clobbers are ignored
  44777 [4.4 Regression] ICE: SIGSEGV with -fprofile-use in gcc.c-torture/execute/comp-goto-2.c
  46985 [4.5 Regression] ICE: SIGSEGV in is_gimple_min_invariant (gimple.c:2742) with -fno-tree-ccp -fno-tree-dominator-opts -fno-tree-fre
  47780 [4.5 Regression] -fcompare-debug failure with -O -fgcse -fgcse-las -fstack-protector-all
  47858 [4.5/4.6/4.7 Regression] IPA-SRA decreases quality of debug info
  47903 [4.5 Regression] var-tracking.c: valgrind error
  48685 [4.5 Regression] ICE in gimplify_expr, at gimplify.c:7034
  52139 [4.5 Regression] ICE: in remove_insn, at emit-rtl.c:3960 with -O -fPIC -fno-tree-dominator-opts -fno-tree-fre
  48046 [4.5 Regression] Expected diagnostic "reference to 'type' is ambiguous" not given for function-local static declaration
  51406 [4.5/4.6/4.7 Regression][c++0x] Incorrect result of static_cast to rvalue reference to base class.
  43949 [4.4 Regression] bogus warning: array subscript is above array bounds
  45982 [4.4 Regression] PTA does not track integers
  48172 [4.5 Regression] incorrect vectorization of loop in GCC 4.5.* with -O3
  49115 [4.5 Regression] invalid return value optimization (?) when exception is thrown and caught
  49279 [4.5 Regression] Optimization incorrectly presuming constant variable inside loop in g++ 4.5 and 4.6 with -O2 and -O3 for x86_64 targets
  50189 [4.5 Regression] Wrong code error in -O2 [-fstrict-enums] compile, target independent
  48660 [4.5/4.6 Regression] ARM ICE in expand_expr_real_1
  23656 Cross-compilation with newlib fails in libiberty
  37985 [4.5/4.6/4.7/4.8 Regression] unsigned char shift lacks "statement with no effect" warning
  38292 [4.5/4.6/4.7/4.8 Regression] corrupted profile info with -O[23] -fprofile-use
  40778 [4.5 Regression] Mudflap instrumentation missing in cloned function.
  40992 [4.4 Regression] cunroll ignoring asm size
  48306 [4.4 Regression] presence of gcc subdir with . in PATH causes breakdown
  49651 [4.4 Regression] nested lambdas and -O3 produced incorrect integer variable increments
  52223 [4.5/4.6 Regression] libffi's man page install breaks with multilibs and overridden mandir
  53418 [4.5 Regression] ICE at gimplify.c:7773
  53138 [4.7 Regression] spaceship operator miscompiled
  50091 [4.5/4.6/4.7 Regression] -fstack-check generates wrong assembly
  50979 architecture mismatch: "mul32" not enabled for "smul" or "umul"
  51187 miscompilation of genrecog.c at -O2 for --target=avr
  52717 thunk referenced in discarded section when building samba with -flto
  48742 [4.5 Regression] Internal error in gimplify_expr
  49120 [4.5 Regression] bogus "value computed is not used" warning (variable-length array in compound statement)
  49161 [4.5 Regression] Fix VRP on switch stmts
  49619 [4.5 Regression] ICE in simplify_subreg, at simplify-rtx.c:5362
  49621 [4.5 regression] ICE in trunc_int_for_mode, at explow.c:57
  49644 [4.5 Regression] post-increment of promoted operand is incorrect.
  51767 [4.5 Regression] ICE with degenerated asm goto
  51768 [4.5 Regression] ICE with invalid asm goto
  52736 [4.5/4.6/4.7/4.8 Regression] miscompilation: store to aliased __m128d is 8 Bytes off
  49440 [4.6 regression] Invalid dynamic_cast for unnamed namespace
  50565 [4.5/4.6/4.7 Regression] initializer element is not computable at load time
  52294 [4.7 Regression] [ARM Thumb] generated asm code produces "branch out of range" error in gas with -Os -mcpu=cortex-a9
  41159 [LTO] ICE in insert_value_copy_on_edge, at tree-outof-ssa.c:225
  48822 [4.5 Regression] G++ gets stucks and never finishes compilation when enabling -O2/3 optimization options.
  50162 [4.5 Regression] Wrong vectorization
  49381 Unresolved symbols in libgcjgc.a when linking gctest
  45786 [4.5 Regression] Relational operators .eq. and == are not recognized as equivalent
  48708 Invalid V2DI vector set insn generated
  50464 Using -Ofast -march=bdver1 results in internal compiler error: in extract_insn, at recog.c:2109
  51821 [4.5/4.6/4.7 Regression] 64bit > 32bit conversion produces incorrect results with optimizations
  52698 -maddress-mode=long doesn't work
  53228 [4.6/4.7/4.8 Regression] target attributes in libcpp/lex.c cause illegal instructions to be used elsewhere
  42082 [C++0x] ICE on probably invalid with "canonical types differ for identical types"
  42652 vectorizer created unaligned vector insns
  42856 [4.4 Regression] FAIL: gcc.dg/torture/pr41555.c -O0 (test for excess errors)
  47733 psignal (int, const? char*) in libiberty/strsignal.h
  48743 -march=native mis-detects AMD K6-2+ / K6-3 as Athlon - compiled C fails with "illegal instruction"
  49038 [4.5/4.6/4.7 Regression] -ftree-vectorise introduces reads past end of array
  49448 arm-tab-linux-gnu-eabi enableds big endian when it should not
  49461 boehm-gc and gcj incompatible with pie
  50875 O3 and -mavx lead to internal compiler error: in find_reloads
  51161 [C++0x] Illegal static_cast to rvalue reference to ambiguous base class
  51393 Wrong parameter type for _mm256_insert_epi64 in avxintrin.h
  51444 [4.4 Regression]: Spurious "is used uninitialized" warning for structure with bitfields
  51835 ARM EABI violation when passing arguments to helper floating functions like __aeabi_d2iz
  52894 [4.5,4.6,4.7 Regression] Stage1 bootstrap fails with gcc-4.6.3: Infinite loop in pointer_set_insert
  53310 [4.5/4.6/4.7/4.8 Regression] EOSHIFT leaks memory
  53744 gcov version oscillates between 407* and 407p on branches
  52335 [4.4/4.5/4.6/4.7 Regression] I/O: -std=f95 rejects valid DELIM= in OPEN
  46192 [4.5/4.6/4.7 regression] wrong code for renaming of volatile packed array with address clause
  44581 [4.5/4.6/4.7 Regression] internal compiler error: in simplify_subreg
  49307 [4.5/4.6/4.7 Regression] ICE in spill_failure, at reload1.c:2113
  50163 [4.4/4.5/4.6/4.7 Regression] ICE: initialization expression
  50273 [4.5/4.6/4.7 Regression] -Walign-commons no longer effective
  52022 [4.5/4.6/4.7 Regression] Wrong-code with procedures passed as actual argument
  52452 [4.5/4.6/4.7/4.8 Regression] INTRINSIC cannot be applied to gfortran's ETIME
  25973 [4.5/4.6/4.7/4.8 Regression] Wrong warning: control reaches end of non-void function
  53521 [4.5/4.6/4.7/4.8 Regression] Memory leak with zero-sized array constructor
This commit is contained in:
skrll 2012-09-18 06:09:45 +00:00
parent 4710b77fb6
commit a9d89c3b8a
293 changed files with 7118 additions and 2186 deletions
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30
external/gpl3/gcc/dist/ChangeLog vendored
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@ -1,3 +1,33 @@
2012-07-02 Release Manager
* GCC 4.5.4 released.
2011-12-18 Eric Botcazou <ebotcazou@adacore.com>
* configure: Regenerate.
2011-06-27 Hans-Peter Nilsson <hp@axis.com>
PR regression/47836
PR bootstrap/23656
PR other/47733
PR bootstrap/49247
PR c/48825
* configure.ac (target_libraries): Remove target-libiberty.
Remove all target-specific settings adding target-libiberty to
skipdirs and noconfigdirs. Remove checking target_configdirs
and removing target-libiberty but keeping target-libgcc if
otherwise empty.
* Makefile.def (target_modules): Don't add libiberty.
(dependencies): Remove all traces of target-libiberty.
* configure, Makefile.in: Regenerate.
2011-06-19 Jack Howarth <howarth@bromo.med.uc.edu>
PR target/49461
* configure.ac: Use mh-x86-darwin.
* configure: Regenerate.
2011-04-28 Release Manager
* GCC 4.5.3 released.

2
external/gpl3/gcc/dist/INSTALL/configure.html vendored
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@ -561,7 +561,7 @@ systems that support conditional traps).
<!-- If you make -with-llsc the default for additional targets, -->
<!-- update the -with-llsc description in the MIPS section below. -->
<br><dt><code>--with-llsc</code><dd>On MIPS targets, make <samp><span class="option">-mllsc</span></samp> the default when no
<samp><span class="option">-mno-lsc</span></samp> option is passed. This is the default for
<samp><span class="option">-mno-llsc</span></samp> option is passed. This is the default for
Linux-based targets, as the kernel will emulate them if the ISA does
not provide them.

2
external/gpl3/gcc/dist/LAST_UPDATED vendored
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@ -1 +1 @@
Obtained from SVN: tags/gcc_4_5_3_release revision 173114
Obtained from SVN: tags/gcc_4_5_4_release revision 189153

651
external/gpl3/gcc/dist/MD5SUMS vendored
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File diff suppressed because it is too large Load Diff

7
external/gpl3/gcc/dist/Makefile.def vendored
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@ -164,7 +164,6 @@ target_modules = { module= libtermcap; no_check=true;
missing=maintainer-clean; };
target_modules = { module= winsup; };
target_modules = { module= libgloss; no_check=true; };
target_modules = { module= libiberty; };
target_modules = { module= gperf; };
target_modules = { module= examples; no_check=true; no_install=true; };
target_modules = { module= libffi; };
@ -532,7 +531,6 @@ dependencies = { module=configure-target-boehm-gc; on=configure-target-qthreads;
dependencies = { module=configure-target-boehm-gc; on=all-target-libstdc++-v3; };
dependencies = { module=configure-target-fastjar; on=configure-target-zlib; };
dependencies = { module=all-target-fastjar; on=all-target-zlib; };
dependencies = { module=all-target-fastjar; on=all-target-libiberty; };
dependencies = { module=configure-target-libjava; on=configure-target-zlib; };
dependencies = { module=configure-target-libjava; on=configure-target-boehm-gc; };
dependencies = { module=configure-target-libjava; on=configure-target-qthreads; };
@ -543,9 +541,7 @@ dependencies = { module=all-target-libjava; on=all-target-boehm-gc; };
dependencies = { module=all-target-libjava; on=all-target-qthreads; };
dependencies = { module=all-target-libjava; on=all-target-libffi; };
dependencies = { module=configure-target-libobjc; on=configure-target-boehm-gc; };
dependencies = { module=all-target-libobjc; on=all-target-libiberty; };
dependencies = { module=all-target-libobjc; on=all-target-boehm-gc; };
dependencies = { module=all-target-libstdc++-v3; on=all-target-libiberty; };
dependencies = { module=configure-target-libstdc++-v3; on=configure-target-libgomp; };
// parallel_list.o and parallel_settings.o depend on omp.h, which is
// generated by the libgomp configure. Unfortunately, due to the use of
@ -560,10 +556,7 @@ lang_env_dependencies = { module=winsup; };
lang_env_dependencies = { module=qthreads; };
dependencies = { module=all-target-libgloss; on=all-target-newlib; };
dependencies = { module=all-target-winsup; on=all-target-libiberty; };
dependencies = { module=all-target-winsup; on=all-target-libtermcap; };
dependencies = { module=configure-target-libiberty; on=all-binutils; };
dependencies = { module=configure-target-libiberty; on=all-ld; };
dependencies = { module=configure-target-newlib; on=all-binutils; };
dependencies = { module=configure-target-newlib; on=all-ld; };

469
external/gpl3/gcc/dist/Makefile.in vendored
View File

@ -930,7 +930,6 @@ configure-target: \
maybe-configure-target-libtermcap \
maybe-configure-target-winsup \
maybe-configure-target-libgloss \
maybe-configure-target-libiberty \
maybe-configure-target-gperf \
maybe-configure-target-examples \
maybe-configure-target-libffi \
@ -1112,7 +1111,6 @@ all-target: maybe-all-target-libobjc
all-target: maybe-all-target-libtermcap
all-target: maybe-all-target-winsup
all-target: maybe-all-target-libgloss
all-target: maybe-all-target-libiberty
all-target: maybe-all-target-gperf
all-target: maybe-all-target-examples
all-target: maybe-all-target-libffi
@ -1233,7 +1231,6 @@ info-target: maybe-info-target-libobjc
info-target: maybe-info-target-libtermcap
info-target: maybe-info-target-winsup
info-target: maybe-info-target-libgloss
info-target: maybe-info-target-libiberty
info-target: maybe-info-target-gperf
info-target: maybe-info-target-examples
info-target: maybe-info-target-libffi
@ -1347,7 +1344,6 @@ dvi-target: maybe-dvi-target-libobjc
dvi-target: maybe-dvi-target-libtermcap
dvi-target: maybe-dvi-target-winsup
dvi-target: maybe-dvi-target-libgloss
dvi-target: maybe-dvi-target-libiberty
dvi-target: maybe-dvi-target-gperf
dvi-target: maybe-dvi-target-examples
dvi-target: maybe-dvi-target-libffi
@ -1461,7 +1457,6 @@ pdf-target: maybe-pdf-target-libobjc
pdf-target: maybe-pdf-target-libtermcap
pdf-target: maybe-pdf-target-winsup
pdf-target: maybe-pdf-target-libgloss
pdf-target: maybe-pdf-target-libiberty
pdf-target: maybe-pdf-target-gperf
pdf-target: maybe-pdf-target-examples
pdf-target: maybe-pdf-target-libffi
@ -1575,7 +1570,6 @@ html-target: maybe-html-target-libobjc
html-target: maybe-html-target-libtermcap
html-target: maybe-html-target-winsup
html-target: maybe-html-target-libgloss
html-target: maybe-html-target-libiberty
html-target: maybe-html-target-gperf
html-target: maybe-html-target-examples
html-target: maybe-html-target-libffi
@ -1689,7 +1683,6 @@ TAGS-target: maybe-TAGS-target-libobjc
TAGS-target: maybe-TAGS-target-libtermcap
TAGS-target: maybe-TAGS-target-winsup
TAGS-target: maybe-TAGS-target-libgloss
TAGS-target: maybe-TAGS-target-libiberty
TAGS-target: maybe-TAGS-target-gperf
TAGS-target: maybe-TAGS-target-examples
TAGS-target: maybe-TAGS-target-libffi
@ -1803,7 +1796,6 @@ install-info-target: maybe-install-info-target-libobjc
install-info-target: maybe-install-info-target-libtermcap
install-info-target: maybe-install-info-target-winsup
install-info-target: maybe-install-info-target-libgloss
install-info-target: maybe-install-info-target-libiberty
install-info-target: maybe-install-info-target-gperf
install-info-target: maybe-install-info-target-examples
install-info-target: maybe-install-info-target-libffi
@ -1917,7 +1909,6 @@ install-pdf-target: maybe-install-pdf-target-libobjc
install-pdf-target: maybe-install-pdf-target-libtermcap
install-pdf-target: maybe-install-pdf-target-winsup
install-pdf-target: maybe-install-pdf-target-libgloss
install-pdf-target: maybe-install-pdf-target-libiberty
install-pdf-target: maybe-install-pdf-target-gperf
install-pdf-target: maybe-install-pdf-target-examples
install-pdf-target: maybe-install-pdf-target-libffi
@ -2031,7 +2022,6 @@ install-html-target: maybe-install-html-target-libobjc
install-html-target: maybe-install-html-target-libtermcap
install-html-target: maybe-install-html-target-winsup
install-html-target: maybe-install-html-target-libgloss
install-html-target: maybe-install-html-target-libiberty
install-html-target: maybe-install-html-target-gperf
install-html-target: maybe-install-html-target-examples
install-html-target: maybe-install-html-target-libffi
@ -2145,7 +2135,6 @@ installcheck-target: maybe-installcheck-target-libobjc
installcheck-target: maybe-installcheck-target-libtermcap
installcheck-target: maybe-installcheck-target-winsup
installcheck-target: maybe-installcheck-target-libgloss
installcheck-target: maybe-installcheck-target-libiberty
installcheck-target: maybe-installcheck-target-gperf
installcheck-target: maybe-installcheck-target-examples
installcheck-target: maybe-installcheck-target-libffi
@ -2259,7 +2248,6 @@ mostlyclean-target: maybe-mostlyclean-target-libobjc
mostlyclean-target: maybe-mostlyclean-target-libtermcap
mostlyclean-target: maybe-mostlyclean-target-winsup
mostlyclean-target: maybe-mostlyclean-target-libgloss
mostlyclean-target: maybe-mostlyclean-target-libiberty
mostlyclean-target: maybe-mostlyclean-target-gperf
mostlyclean-target: maybe-mostlyclean-target-examples
mostlyclean-target: maybe-mostlyclean-target-libffi
@ -2373,7 +2361,6 @@ clean-target: maybe-clean-target-libobjc
clean-target: maybe-clean-target-libtermcap
clean-target: maybe-clean-target-winsup
clean-target: maybe-clean-target-libgloss
clean-target: maybe-clean-target-libiberty
clean-target: maybe-clean-target-gperf
clean-target: maybe-clean-target-examples
clean-target: maybe-clean-target-libffi
@ -2487,7 +2474,6 @@ distclean-target: maybe-distclean-target-libobjc
distclean-target: maybe-distclean-target-libtermcap
distclean-target: maybe-distclean-target-winsup
distclean-target: maybe-distclean-target-libgloss
distclean-target: maybe-distclean-target-libiberty
distclean-target: maybe-distclean-target-gperf
distclean-target: maybe-distclean-target-examples
distclean-target: maybe-distclean-target-libffi
@ -2601,7 +2587,6 @@ maintainer-clean-target: maybe-maintainer-clean-target-libobjc
maintainer-clean-target: maybe-maintainer-clean-target-libtermcap
maintainer-clean-target: maybe-maintainer-clean-target-winsup
maintainer-clean-target: maybe-maintainer-clean-target-libgloss
maintainer-clean-target: maybe-maintainer-clean-target-libiberty
maintainer-clean-target: maybe-maintainer-clean-target-gperf
maintainer-clean-target: maybe-maintainer-clean-target-examples
maintainer-clean-target: maybe-maintainer-clean-target-libffi
@ -2770,7 +2755,6 @@ check-target: \
maybe-check-target-libtermcap \
maybe-check-target-winsup \
maybe-check-target-libgloss \
maybe-check-target-libiberty \
maybe-check-target-gperf \
maybe-check-target-examples \
maybe-check-target-libffi \
@ -2991,7 +2975,6 @@ install-target: \
maybe-install-target-libtermcap \
maybe-install-target-winsup \
maybe-install-target-libgloss \
maybe-install-target-libiberty \
maybe-install-target-gperf \
maybe-install-target-examples \
maybe-install-target-libffi \
@ -50216,448 +50199,6 @@ maintainer-clean-target-libgloss:
.PHONY: configure-target-libiberty maybe-configure-target-libiberty
maybe-configure-target-libiberty:
@if gcc-bootstrap
configure-target-libiberty: stage_current
@endif gcc-bootstrap
@if target-libiberty
maybe-configure-target-libiberty: configure-target-libiberty
configure-target-libiberty:
@: $(MAKE); $(unstage)
@r=`${PWD_COMMAND}`; export r; \
s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
echo "Checking multilib configuration for libiberty..."; \
$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libiberty ; \
$(CC_FOR_TARGET) --print-multi-lib > $(TARGET_SUBDIR)/libiberty/multilib.tmp 2> /dev/null ; \
if test -r $(TARGET_SUBDIR)/libiberty/multilib.out; then \
if cmp -s $(TARGET_SUBDIR)/libiberty/multilib.tmp $(TARGET_SUBDIR)/libiberty/multilib.out; then \
rm -f $(TARGET_SUBDIR)/libiberty/multilib.tmp; \
else \
rm -f $(TARGET_SUBDIR)/libiberty/Makefile; \
mv $(TARGET_SUBDIR)/libiberty/multilib.tmp $(TARGET_SUBDIR)/libiberty/multilib.out; \
fi; \
else \
mv $(TARGET_SUBDIR)/libiberty/multilib.tmp $(TARGET_SUBDIR)/libiberty/multilib.out; \
fi; \
test ! -f $(TARGET_SUBDIR)/libiberty/Makefile || exit 0; \
$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libiberty ; \
$(NORMAL_TARGET_EXPORTS) \
echo Configuring in $(TARGET_SUBDIR)/libiberty; \
cd "$(TARGET_SUBDIR)/libiberty" || exit 1; \
case $(srcdir) in \
/* | [A-Za-z]:[\\/]*) topdir=$(srcdir) ;; \
*) topdir=`echo $(TARGET_SUBDIR)/libiberty/ | \
sed -e 's,\./,,g' -e 's,[^/]*/,../,g' `$(srcdir) ;; \
esac; \
srcdiroption="--srcdir=$${topdir}/libiberty"; \
libsrcdir="$$s/libiberty"; \
rm -f no-such-file || : ; \
CONFIG_SITE=no-such-file $(SHELL) $${libsrcdir}/configure \
$(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
--target=${target_alias} $${srcdiroption} \
|| exit 1
@endif target-libiberty
.PHONY: all-target-libiberty maybe-all-target-libiberty
maybe-all-target-libiberty:
@if gcc-bootstrap
all-target-libiberty: stage_current
@endif gcc-bootstrap
@if target-libiberty
TARGET-target-libiberty=all
maybe-all-target-libiberty: all-target-libiberty
all-target-libiberty: configure-target-libiberty
@: $(MAKE); $(unstage)
@r=`${PWD_COMMAND}`; export r; \
s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
$(NORMAL_TARGET_EXPORTS) \
(cd $(TARGET_SUBDIR)/libiberty && \
$(MAKE) $(BASE_FLAGS_TO_PASS) $(EXTRA_TARGET_FLAGS) \
$(TARGET-target-libiberty))
@endif target-libiberty
.PHONY: check-target-libiberty maybe-check-target-libiberty
maybe-check-target-libiberty:
@if target-libiberty
maybe-check-target-libiberty: check-target-libiberty
check-target-libiberty:
@: $(MAKE); $(unstage)
@r=`${PWD_COMMAND}`; export r; \
s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
$(NORMAL_TARGET_EXPORTS) \
(cd $(TARGET_SUBDIR)/libiberty && \
$(MAKE) $(TARGET_FLAGS_TO_PASS) check)
@endif target-libiberty
.PHONY: install-target-libiberty maybe-install-target-libiberty
maybe-install-target-libiberty:
@if target-libiberty
maybe-install-target-libiberty: install-target-libiberty
install-target-libiberty: installdirs
@: $(MAKE); $(unstage)
@r=`${PWD_COMMAND}`; export r; \
s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
$(NORMAL_TARGET_EXPORTS) \
(cd $(TARGET_SUBDIR)/libiberty && \
$(MAKE) $(TARGET_FLAGS_TO_PASS) install)
@endif target-libiberty
# Other targets (info, dvi, pdf, etc.)
.PHONY: maybe-info-target-libiberty info-target-libiberty
maybe-info-target-libiberty:
@if target-libiberty
maybe-info-target-libiberty: info-target-libiberty
info-target-libiberty: \
configure-target-libiberty
@: $(MAKE); $(unstage)
@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0 ; \
r=`${PWD_COMMAND}`; export r; \
s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
$(NORMAL_TARGET_EXPORTS) \
echo "Doing info in $(TARGET_SUBDIR)/libiberty" ; \
for flag in $(EXTRA_TARGET_FLAGS); do \
eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
done; \
(cd $(TARGET_SUBDIR)/libiberty && \
$(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
"CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
"RANLIB=$${RANLIB}" \
"DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
info) \
|| exit 1
@endif target-libiberty
.PHONY: maybe-dvi-target-libiberty dvi-target-libiberty
maybe-dvi-target-libiberty:
@if target-libiberty
maybe-dvi-target-libiberty: dvi-target-libiberty
dvi-target-libiberty: \
configure-target-libiberty
@: $(MAKE); $(unstage)
@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0 ; \
r=`${PWD_COMMAND}`; export r; \
s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
$(NORMAL_TARGET_EXPORTS) \
echo "Doing dvi in $(TARGET_SUBDIR)/libiberty" ; \
for flag in $(EXTRA_TARGET_FLAGS); do \
eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
done; \
(cd $(TARGET_SUBDIR)/libiberty && \
$(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
"CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
"RANLIB=$${RANLIB}" \
"DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
dvi) \
|| exit 1
@endif target-libiberty
.PHONY: maybe-pdf-target-libiberty pdf-target-libiberty
maybe-pdf-target-libiberty:
@if target-libiberty
maybe-pdf-target-libiberty: pdf-target-libiberty
pdf-target-libiberty: \
configure-target-libiberty
@: $(MAKE); $(unstage)
@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0 ; \
r=`${PWD_COMMAND}`; export r; \
s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
$(NORMAL_TARGET_EXPORTS) \
echo "Doing pdf in $(TARGET_SUBDIR)/libiberty" ; \
for flag in $(EXTRA_TARGET_FLAGS); do \
eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
done; \
(cd $(TARGET_SUBDIR)/libiberty && \
$(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
"CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
"RANLIB=$${RANLIB}" \
"DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
pdf) \
|| exit 1
@endif target-libiberty
.PHONY: maybe-html-target-libiberty html-target-libiberty
maybe-html-target-libiberty:
@if target-libiberty
maybe-html-target-libiberty: html-target-libiberty
html-target-libiberty: \
configure-target-libiberty
@: $(MAKE); $(unstage)
@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0 ; \
r=`${PWD_COMMAND}`; export r; \
s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
$(NORMAL_TARGET_EXPORTS) \
echo "Doing html in $(TARGET_SUBDIR)/libiberty" ; \
for flag in $(EXTRA_TARGET_FLAGS); do \
eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
done; \
(cd $(TARGET_SUBDIR)/libiberty && \
$(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
"CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
"RANLIB=$${RANLIB}" \
"DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
html) \
|| exit 1
@endif target-libiberty
.PHONY: maybe-TAGS-target-libiberty TAGS-target-libiberty
maybe-TAGS-target-libiberty:
@if target-libiberty
maybe-TAGS-target-libiberty: TAGS-target-libiberty
TAGS-target-libiberty: \
configure-target-libiberty
@: $(MAKE); $(unstage)
@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0 ; \
r=`${PWD_COMMAND}`; export r; \
s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
$(NORMAL_TARGET_EXPORTS) \
echo "Doing TAGS in $(TARGET_SUBDIR)/libiberty" ; \
for flag in $(EXTRA_TARGET_FLAGS); do \
eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
done; \
(cd $(TARGET_SUBDIR)/libiberty && \
$(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
"CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
"RANLIB=$${RANLIB}" \
"DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
TAGS) \
|| exit 1
@endif target-libiberty
.PHONY: maybe-install-info-target-libiberty install-info-target-libiberty
maybe-install-info-target-libiberty:
@if target-libiberty
maybe-install-info-target-libiberty: install-info-target-libiberty
install-info-target-libiberty: \
configure-target-libiberty \
info-target-libiberty
@: $(MAKE); $(unstage)
@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0 ; \
r=`${PWD_COMMAND}`; export r; \
s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
$(NORMAL_TARGET_EXPORTS) \
echo "Doing install-info in $(TARGET_SUBDIR)/libiberty" ; \
for flag in $(EXTRA_TARGET_FLAGS); do \
eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
done; \
(cd $(TARGET_SUBDIR)/libiberty && \
$(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
"CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
"RANLIB=$${RANLIB}" \
"DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
install-info) \
|| exit 1
@endif target-libiberty
.PHONY: maybe-install-pdf-target-libiberty install-pdf-target-libiberty
maybe-install-pdf-target-libiberty:
@if target-libiberty
maybe-install-pdf-target-libiberty: install-pdf-target-libiberty
install-pdf-target-libiberty: \
configure-target-libiberty \
pdf-target-libiberty
@: $(MAKE); $(unstage)
@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0 ; \
r=`${PWD_COMMAND}`; export r; \
s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
$(NORMAL_TARGET_EXPORTS) \
echo "Doing install-pdf in $(TARGET_SUBDIR)/libiberty" ; \
for flag in $(EXTRA_TARGET_FLAGS); do \
eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
done; \
(cd $(TARGET_SUBDIR)/libiberty && \
$(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
"CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
"RANLIB=$${RANLIB}" \
"DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
install-pdf) \
|| exit 1
@endif target-libiberty
.PHONY: maybe-install-html-target-libiberty install-html-target-libiberty
maybe-install-html-target-libiberty:
@if target-libiberty
maybe-install-html-target-libiberty: install-html-target-libiberty
install-html-target-libiberty: \
configure-target-libiberty \
html-target-libiberty
@: $(MAKE); $(unstage)
@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0 ; \
r=`${PWD_COMMAND}`; export r; \
s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
$(NORMAL_TARGET_EXPORTS) \
echo "Doing install-html in $(TARGET_SUBDIR)/libiberty" ; \
for flag in $(EXTRA_TARGET_FLAGS); do \
eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
done; \
(cd $(TARGET_SUBDIR)/libiberty && \
$(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
"CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
"RANLIB=$${RANLIB}" \
"DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
install-html) \
|| exit 1
@endif target-libiberty
.PHONY: maybe-installcheck-target-libiberty installcheck-target-libiberty
maybe-installcheck-target-libiberty:
@if target-libiberty
maybe-installcheck-target-libiberty: installcheck-target-libiberty
installcheck-target-libiberty: \
configure-target-libiberty
@: $(MAKE); $(unstage)
@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0 ; \
r=`${PWD_COMMAND}`; export r; \
s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
$(NORMAL_TARGET_EXPORTS) \
echo "Doing installcheck in $(TARGET_SUBDIR)/libiberty" ; \
for flag in $(EXTRA_TARGET_FLAGS); do \
eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
done; \
(cd $(TARGET_SUBDIR)/libiberty && \
$(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
"CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
"RANLIB=$${RANLIB}" \
"DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
installcheck) \
|| exit 1
@endif target-libiberty
.PHONY: maybe-mostlyclean-target-libiberty mostlyclean-target-libiberty
maybe-mostlyclean-target-libiberty:
@if target-libiberty
maybe-mostlyclean-target-libiberty: mostlyclean-target-libiberty
mostlyclean-target-libiberty:
@: $(MAKE); $(unstage)
@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0 ; \
r=`${PWD_COMMAND}`; export r; \
s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
$(NORMAL_TARGET_EXPORTS) \
echo "Doing mostlyclean in $(TARGET_SUBDIR)/libiberty" ; \
for flag in $(EXTRA_TARGET_FLAGS); do \
eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
done; \
(cd $(TARGET_SUBDIR)/libiberty && \
$(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
"CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
"RANLIB=$${RANLIB}" \
"DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
mostlyclean) \
|| exit 1
@endif target-libiberty
.PHONY: maybe-clean-target-libiberty clean-target-libiberty
maybe-clean-target-libiberty:
@if target-libiberty
maybe-clean-target-libiberty: clean-target-libiberty
clean-target-libiberty:
@: $(MAKE); $(unstage)
@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0 ; \
r=`${PWD_COMMAND}`; export r; \
s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
$(NORMAL_TARGET_EXPORTS) \
echo "Doing clean in $(TARGET_SUBDIR)/libiberty" ; \
for flag in $(EXTRA_TARGET_FLAGS); do \
eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
done; \
(cd $(TARGET_SUBDIR)/libiberty && \
$(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
"CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
"RANLIB=$${RANLIB}" \
"DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
clean) \
|| exit 1
@endif target-libiberty
.PHONY: maybe-distclean-target-libiberty distclean-target-libiberty
maybe-distclean-target-libiberty:
@if target-libiberty
maybe-distclean-target-libiberty: distclean-target-libiberty
distclean-target-libiberty:
@: $(MAKE); $(unstage)
@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0 ; \
r=`${PWD_COMMAND}`; export r; \
s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
$(NORMAL_TARGET_EXPORTS) \
echo "Doing distclean in $(TARGET_SUBDIR)/libiberty" ; \
for flag in $(EXTRA_TARGET_FLAGS); do \
eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
done; \
(cd $(TARGET_SUBDIR)/libiberty && \
$(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
"CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
"RANLIB=$${RANLIB}" \
"DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
distclean) \
|| exit 1
@endif target-libiberty
.PHONY: maybe-maintainer-clean-target-libiberty maintainer-clean-target-libiberty
maybe-maintainer-clean-target-libiberty:
@if target-libiberty
maybe-maintainer-clean-target-libiberty: maintainer-clean-target-libiberty
maintainer-clean-target-libiberty:
@: $(MAKE); $(unstage)
@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0 ; \
r=`${PWD_COMMAND}`; export r; \
s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
$(NORMAL_TARGET_EXPORTS) \
echo "Doing maintainer-clean in $(TARGET_SUBDIR)/libiberty" ; \
for flag in $(EXTRA_TARGET_FLAGS); do \
eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
done; \
(cd $(TARGET_SUBDIR)/libiberty && \
$(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
"CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
"RANLIB=$${RANLIB}" \
"DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
maintainer-clean) \
|| exit 1
@endif target-libiberty
.PHONY: configure-target-gperf maybe-configure-target-gperf
maybe-configure-target-gperf:
@if gcc-bootstrap
@ -57654,7 +57195,6 @@ configure-target-libobjc: stage_last
configure-target-libtermcap: stage_last
configure-target-winsup: stage_last
configure-target-libgloss: stage_last
configure-target-libiberty: stage_last
configure-target-gperf: stage_last
configure-target-examples: stage_last
configure-target-libffi: stage_last
@ -57683,7 +57223,6 @@ configure-target-libobjc: maybe-all-gcc
configure-target-libtermcap: maybe-all-gcc
configure-target-winsup: maybe-all-gcc
configure-target-libgloss: maybe-all-gcc
configure-target-libiberty: maybe-all-gcc
configure-target-gperf: maybe-all-gcc
configure-target-examples: maybe-all-gcc
configure-target-libffi: maybe-all-gcc
@ -58395,7 +57934,6 @@ configure-target-boehm-gc: maybe-configure-target-qthreads
configure-target-boehm-gc: maybe-all-target-libstdc++-v3
configure-target-fastjar: maybe-configure-target-zlib
all-target-fastjar: maybe-all-target-zlib
all-target-fastjar: maybe-all-target-libiberty
configure-target-libjava: maybe-configure-target-zlib
configure-target-libjava: maybe-configure-target-boehm-gc
configure-target-libjava: maybe-configure-target-qthreads
@ -58406,9 +57944,7 @@ all-target-libjava: maybe-all-target-boehm-gc
all-target-libjava: maybe-all-target-qthreads
all-target-libjava: maybe-all-target-libffi
configure-target-libobjc: maybe-configure-target-boehm-gc
all-target-libobjc: maybe-all-target-libiberty
all-target-libobjc: maybe-all-target-boehm-gc
all-target-libstdc++-v3: maybe-all-target-libiberty
configure-target-libstdc++-v3: maybe-configure-target-libgomp
configure-stage1-target-libstdc++-v3: maybe-configure-stage1-target-libgomp
@ -58426,10 +57962,7 @@ all-stage4-target-libstdc++-v3: maybe-configure-stage4-target-libgomp
all-stageprofile-target-libstdc++-v3: maybe-configure-stageprofile-target-libgomp
all-stagefeedback-target-libstdc++-v3: maybe-configure-stagefeedback-target-libgomp
all-target-libgloss: maybe-all-target-newlib
all-target-winsup: maybe-all-target-libiberty
all-target-winsup: maybe-all-target-libtermcap
configure-target-libiberty: maybe-all-binutils
configure-target-libiberty: maybe-all-ld
configure-target-newlib: maybe-all-binutils
configure-target-newlib: maybe-all-ld
@ -58464,7 +57997,6 @@ configure-target-libobjc: maybe-all-target-libgcc
configure-target-libtermcap: maybe-all-target-libgcc
configure-target-winsup: maybe-all-target-libgcc
configure-target-libgloss: maybe-all-target-libgcc
configure-target-libiberty: maybe-all-target-libgcc
configure-target-gperf: maybe-all-target-libgcc
configure-target-examples: maybe-all-target-libgcc
configure-target-libffi: maybe-all-target-libgcc
@ -58495,7 +58027,6 @@ configure-target-libtermcap: maybe-all-target-newlib maybe-all-target-libgloss
configure-target-winsup: maybe-all-target-newlib maybe-all-target-libgloss
configure-target-gperf: maybe-all-target-newlib maybe-all-target-libgloss
configure-target-gperf: maybe-all-target-libstdc++-v3

392
external/gpl3/gcc/dist/NEWS vendored
View File

@ -9,27 +9,30 @@ http://gcc.gnu.org/gcc-4.5/index.html
GCC 4.5 Release Series
Apr 28, 2011
Jul 2, 2012
The [1]GNU project and the GCC developers are pleased to announce the
release of GCC 4.5.3.
release of GCC 4.5.4.
This release is a bug-fix release, containing fixes for regressions in
GCC 4.5.2 relative to previous releases of GCC.
GCC 4.5.3 relative to previous releases of GCC.
Release History
GCC 4.5.4
Jul 2, 2012 ([2]changes)
GCC 4.5.3
Apr 28, 2011 ([2]changes)
Apr 28, 2011 ([3]changes)
GCC 4.5.2
Dec 16, 2010 ([3]changes)
Dec 16, 2010 ([4]changes)
GCC 4.5.1
Jul 31, 2010 ([4]changes)
Jul 31, 2010 ([5]changes)
GCC 4.5.0
April 14, 2010 ([5]changes)
April 14, 2010 ([6]changes)
References and Acknowledgements
@ -37,33 +40,33 @@ References and Acknowledgements
supports several other languages aside from C, it now stands for the
GNU Compiler Collection.
A list of [6]successful builds is updated as new information becomes
A list of [7]successful builds is updated as new information becomes
available.
The GCC developers would like to thank the numerous people that have
contributed new features, improvements, bug fixes, and other changes as
well as test results to GCC. This [7]amazing group of volunteers is
well as test results to GCC. This [8]amazing group of volunteers is
what makes GCC successful.
For additional information about GCC please refer to the [8]GCC project
web site or contact the [9]GCC development mailing list.
For additional information about GCC please refer to the [9]GCC project
web site or contact the [10]GCC development mailing list.
To obtain GCC please use [10]our mirror sites or [11]our SVN server.
To obtain GCC please use [11]our mirror sites or [12]our SVN server.
For questions related to the use of GCC, please consult these web
pages and the [12]GCC manuals. If that fails, the
[13]gcc-help@gcc.gnu.org mailing list might help. Comments on these
pages and the [13]GCC manuals. If that fails, the
[14]gcc-help@gcc.gnu.org mailing list might help. Comments on these
web pages and the development of GCC are welcome on our developer
list at [14]gcc@gcc.gnu.org. All of [15]our lists have public
list at [15]gcc@gcc.gnu.org. All of [16]our lists have public
archives.
Copyright (C) [16]Free Software Foundation, Inc. Verbatim copying and
Copyright (C) [17]Free Software Foundation, Inc. Verbatim copying and
distribution of this entire article is permitted in any medium,
provided this notice is preserved.
These pages are [17]maintained by the GCC team. Last modified
2011-04-28[18].
These pages are [18]maintained by the GCC team. Last modified
2012-07-02[19].
References
@ -72,19 +75,20 @@ References
3. http://gcc.gnu.org/gcc-4.5/changes.html
4. http://gcc.gnu.org/gcc-4.5/changes.html
5. http://gcc.gnu.org/gcc-4.5/changes.html
6. http://gcc.gnu.org/gcc-4.5/buildstat.html
7. http://gcc.gnu.org/onlinedocs/gcc/Contributors.html
8. http://gcc.gnu.org/index.html
9. mailto:gcc@gcc.gnu.org
10. http://gcc.gnu.org/mirrors.html
11. http://gcc.gnu.org/svn.html
12. http://gcc.gnu.org/onlinedocs/
13. mailto:gcc-help@gcc.gnu.org
14. mailto:gcc@gcc.gnu.org
15. http://gcc.gnu.org/lists.html
16. http://www.fsf.org/
17. http://gcc.gnu.org/about.html
18. http://validator.w3.org/check/referer
6. http://gcc.gnu.org/gcc-4.5/changes.html
7. http://gcc.gnu.org/gcc-4.5/buildstat.html
8. http://gcc.gnu.org/onlinedocs/gcc/Contributors.html
9. http://gcc.gnu.org/index.html
10. mailto:gcc@gcc.gnu.org
11. http://gcc.gnu.org/mirrors.html
12. http://gcc.gnu.org/svn.html
13. http://gcc.gnu.org/onlinedocs/
14. mailto:gcc-help@gcc.gnu.org
15. mailto:gcc@gcc.gnu.org
16. http://gcc.gnu.org/lists.html
17. http://www.fsf.org/
18. http://gcc.gnu.org/about.html
19. http://validator.w3.org/check/referer
======================================================================
http://gcc.gnu.org/gcc-4.5/changes.html
@ -171,10 +175,10 @@ General Optimizer Improvements
(e.g. csinf and csinl) are also handled.
* A new link-time optimizer has been added ([8]-flto). When this
option is used, GCC generates a bytecode representation of each
input file and writes it to special ELF sections in each object
input file and writes it to specially-named sections in each object
file. When the object files are linked together, all the function
bodies are read from these ELF sections and instantiated as if they
had been part of the same translation unit. This enables
bodies are read from these named sections and instantiated as if
they had been part of the same translation unit. This enables
interprocedural optimizations to work across different files (and
even different languages), potentially improving the performance of
the generated code. To use the link-timer optimizer, -flto needs to
@ -490,8 +494,6 @@ vector-size: improvement = 3: call stack = 0x804842c ...
ATAN(Y,X) is now an alias for ATAN2(Y,X).
+ The BLOCK construct has been implemented.
Java (GCJ)
New Targets and Target Specific Improvements
AIX
@ -595,8 +597,6 @@ New Targets and Target Specific Improvements
use_debug_exception_return. See the documentation for more details
about these attributes.
picochip
RS/6000 (POWER/PowerPC)
* GCC now supports the Power ISA 2.06, which includes the VSX
@ -616,6 +616,11 @@ New Targets and Target Specific Improvements
* GCC can now be configured with options --with-cpu-32,
--with-cpu-64, --with-tune-32 and --with-tune-64 to control the
default optimization separately for 32-bit and 64-bit modes.
* Starting with GCC 4.5.4, vectors of type vector long long or vector
long are passed and returned in the same method as other vectors
with the VSX instruction set. Previously the GCC compiler did not
adhere to the ABI for 128-bit vectors with 64-bit integer base
types (PR 48857). This is also fixed in the GCC 4.6.1 release.
RX
@ -638,7 +643,7 @@ Operating Systems
* Numerous other minor bugfixes and improvements, and substantial
enhancements to the Fortran language support library.
Documentation improvements
>
Other significant improvements
@ -699,11 +704,11 @@ GCC 4.5.2
GCC 4.5.3
This is the [27]list of problem reports (PRs) from GCC's bug tracking
system that are known to be fixed in the 4.5.2 release. This list might
system that are known to be fixed in the 4.5.3 release. This list might
not be complete (that is, it is possible that some PRs that have been
fixed are not listed here).
On the PowerPC compiler, the altivec builtin functions vec_ld and
On the PowerPC compiler, the Altivec builtin functions vec_ld and
vec_st have been modified to generate the Altivec memory instructions
LVX and STVX, even if the -mvsx option is used. In the initial GCC 4.5
release, these builtin functions were changed to generate VSX memory
@ -713,20 +718,27 @@ GCC 4.5.3
vec_vsx_ld and vec_vsx_st which always generates the VSX memory
instructions.
GCC 4.5.4
This is the [28]list of problem reports (PRs) from GCC's bug tracking
system that are known to be fixed in the 4.5.4 release. This list might
not be complete (that is, it is possible that some PRs that have been
fixed are not listed here).
For questions related to the use of GCC, please consult these web
pages and the [28]GCC manuals. If that fails, the
[29]gcc-help@gcc.gnu.org mailing list might help. Comments on these
pages and the [29]GCC manuals. If that fails, the
[30]gcc-help@gcc.gnu.org mailing list might help. Comments on these
web pages and the development of GCC are welcome on our developer
list at [30]gcc@gcc.gnu.org. All of [31]our lists have public
list at [31]gcc@gcc.gnu.org. All of [32]our lists have public
archives.
Copyright (C) [32]Free Software Foundation, Inc. Verbatim copying and
Copyright (C) [33]Free Software Foundation, Inc. Verbatim copying and
distribution of this entire article is permitted in any medium,
provided this notice is preserved.
These pages are [33]maintained by the GCC team. Last modified
2011-04-25[34].
These pages are [34]maintained by the GCC team. Last modified
2012-07-02[35].
References
@ -756,49 +768,53 @@ References
24. http://gcc.gnu.org/bugzilla/buglist.cgi?bug_status=RESOLVED&resolution=FIXED&target_milestone=4.5.1
25. http://gcc.gnu.org/onlinedocs/gcc/Optimize-Options.html#index-flto-801
26. http://gcc.gnu.org/bugzilla/buglist.cgi?bug_status=RESOLVED&resolution=FIXED&target_milestone=4.5.2
27. http://gcc.gnu.org/bugzilla/buglist.cgi?bug_status=RESOLVED&resolution=FIXED&target_milestone=4.5.2
28. http://gcc.gnu.org/onlinedocs/
29. mailto:gcc-help@gcc.gnu.org
30. mailto:gcc@gcc.gnu.org
31. http://gcc.gnu.org/lists.html
32. http://www.fsf.org/
33. http://gcc.gnu.org/about.html
34. http://validator.w3.org/check/referer
27. http://gcc.gnu.org/bugzilla/buglist.cgi?bug_status=RESOLVED&resolution=FIXED&target_milestone=4.5.3
28. http://gcc.gnu.org/bugzilla/buglist.cgi?bug_status=RESOLVED&resolution=FIXED&target_milestone=4.5.4
29. http://gcc.gnu.org/onlinedocs/
30. mailto:gcc-help@gcc.gnu.org
31. mailto:gcc@gcc.gnu.org
32. http://gcc.gnu.org/lists.html
33. http://www.fsf.org/
34. http://gcc.gnu.org/about.html
35. http://validator.w3.org/check/referer
======================================================================
http://gcc.gnu.org/gcc-4.4/index.html
GCC 4.4 Release Series
April 16, 2011
March 13, 2012
The [1]GNU project and the GCC developers are pleased to announce the
release of GCC 4.4.6.
release of GCC 4.4.7.
This release is a bug-fix release, containing fixes for regressions in
GCC 4.4.5 relative to previous releases of GCC.
GCC 4.4.6 relative to previous releases of GCC.
Release History
GCC 4.4.7
March 13, 2012 ([2]changes)
GCC 4.4.6
April 16, 2011 ([2]changes)
April 16, 2011 ([3]changes)
GCC 4.4.5
October 1, 2010 ([3]changes)
October 1, 2010 ([4]changes)
GCC 4.4.4
April 29, 2010 ([4]changes)
April 29, 2010 ([5]changes)
GCC 4.4.3
January 21, 2010 ([5]changes)
January 21, 2010 ([6]changes)
GCC 4.4.2
October 15, 2009 ([6]changes)
October 15, 2009 ([7]changes)
GCC 4.4.1
July 22, 2009 ([7]changes)
July 22, 2009 ([8]changes)
GCC 4.4.0
April 21, 2009 ([8]changes)
April 21, 2009 ([9]changes)
References and Acknowledgements
@ -806,33 +822,33 @@ References and Acknowledgements
supports several other languages aside from C, it now stands for the
GNU Compiler Collection.
A list of [9]successful builds is updated as new information becomes
A list of [10]successful builds is updated as new information becomes
available.
The GCC developers would like to thank the numerous people that have
contributed new features, improvements, bug fixes, and other changes as
well as test results to GCC. This [10]amazing group of volunteers is
well as test results to GCC. This [11]amazing group of volunteers is
what makes GCC successful.
For additional information about GCC please refer to the [11]GCC
project web site or contact the [12]GCC development mailing list.
For additional information about GCC please refer to the [12]GCC
project web site or contact the [13]GCC development mailing list.
To obtain GCC please use [13]our mirror sites or [14]our SVN server.
To obtain GCC please use [14]our mirror sites or [15]our SVN server.
For questions related to the use of GCC, please consult these web
pages and the [15]GCC manuals. If that fails, the
[16]gcc-help@gcc.gnu.org mailing list might help. Comments on these
pages and the [16]GCC manuals. If that fails, the
[17]gcc-help@gcc.gnu.org mailing list might help. Comments on these
web pages and the development of GCC are welcome on our developer
list at [17]gcc@gcc.gnu.org. All of [18]our lists have public
list at [18]gcc@gcc.gnu.org. All of [19]our lists have public
archives.
Copyright (C) [19]Free Software Foundation, Inc. Verbatim copying and
Copyright (C) [20]Free Software Foundation, Inc. Verbatim copying and
distribution of this entire article is permitted in any medium,
provided this notice is preserved.
These pages are [20]maintained by the GCC team. Last modified
2011-04-25[21].
These pages are [21]maintained by the GCC team. Last modified
2012-03-13[22].
References
@ -844,26 +860,27 @@ References
6. http://gcc.gnu.org/gcc-4.4/changes.html
7. http://gcc.gnu.org/gcc-4.4/changes.html
8. http://gcc.gnu.org/gcc-4.4/changes.html
9. http://gcc.gnu.org/gcc-4.4/buildstat.html
10. http://gcc.gnu.org/onlinedocs/gcc/Contributors.html
11. http://gcc.gnu.org/index.html
12. mailto:gcc@gcc.gnu.org
13. http://gcc.gnu.org/mirrors.html
14. http://gcc.gnu.org/svn.html
15. http://gcc.gnu.org/onlinedocs/
16. mailto:gcc-help@gcc.gnu.org
17. mailto:gcc@gcc.gnu.org
18. http://gcc.gnu.org/lists.html
19. http://www.fsf.org/
20. http://gcc.gnu.org/about.html
21. http://validator.w3.org/check/referer
9. http://gcc.gnu.org/gcc-4.4/changes.html
10. http://gcc.gnu.org/gcc-4.4/buildstat.html
11. http://gcc.gnu.org/onlinedocs/gcc/Contributors.html
12. http://gcc.gnu.org/index.html
13. mailto:gcc@gcc.gnu.org
14. http://gcc.gnu.org/mirrors.html
15. http://gcc.gnu.org/svn.html
16. http://gcc.gnu.org/onlinedocs/
17. mailto:gcc-help@gcc.gnu.org
18. mailto:gcc@gcc.gnu.org
19. http://gcc.gnu.org/lists.html
20. http://www.fsf.org/
21. http://gcc.gnu.org/about.html
22. http://validator.w3.org/check/referer
======================================================================
http://gcc.gnu.org/gcc-4.4/changes.html
GCC 4.4 Release Series
Changes, New Features, and Fixes
The latest release in the 4.4 release series is [1]GCC 4.4.6.
The latest release in the 4.4 release series is [1]GCC 4.4.7.
Caveats
@ -1442,24 +1459,31 @@ GCC 4.4.6
not be complete (that is, it is possible that some PRs that have been
fixed are not listed here).
GCC 4.4.7
This is the [19]list of problem reports (PRs) from GCC's bug tracking
system that are known to be fixed in the 4.4.7 release. This list might
not be complete (that is, it is possible that some PRs that have been
fixed are not listed here).
For questions related to the use of GCC, please consult these web
pages and the [19]GCC manuals. If that fails, the
[20]gcc-help@gcc.gnu.org mailing list might help. Comments on these
pages and the [20]GCC manuals. If that fails, the
[21]gcc-help@gcc.gnu.org mailing list might help. Comments on these
web pages and the development of GCC are welcome on our developer
list at [21]gcc@gcc.gnu.org. All of [22]our lists have public
list at [22]gcc@gcc.gnu.org. All of [23]our lists have public
archives.
Copyright (C) [23]Free Software Foundation, Inc. Verbatim copying and
Copyright (C) [24]Free Software Foundation, Inc. Verbatim copying and
distribution of this entire article is permitted in any medium,
provided this notice is preserved.
These pages are [24]maintained by the GCC team. Last modified
2011-04-25[25].
These pages are [25]maintained by the GCC team. Last modified
2012-03-13[26].
References
1. http://gcc.gnu.org/gcc-4.4/changes.html#4.4.6
1. http://gcc.gnu.org/gcc-4.4/changes.html#4.4.7
2. http://gcc.gnu.org/gcc-4.3/changes.html#obsoleted
3. http://gcc.gnu.org/gcc-4.4/porting_to.html
4. http://gcc.gnu.org/wiki/Graphite
@ -1477,45 +1501,49 @@ References
16. http://gcc.gnu.org/bugzilla/buglist.cgi?bug_status=RESOLVED&resolution=FIXED&target_milestone=4.4.4
17. http://gcc.gnu.org/bugzilla/buglist.cgi?bug_status=RESOLVED&resolution=FIXED&target_milestone=4.4.5
18. http://gcc.gnu.org/bugzilla/buglist.cgi?bug_status=RESOLVED&resolution=FIXED&target_milestone=4.4.6
19. http://gcc.gnu.org/onlinedocs/
20. mailto:gcc-help@gcc.gnu.org
21. mailto:gcc@gcc.gnu.org
22. http://gcc.gnu.org/lists.html
23. http://www.fsf.org/
24. http://gcc.gnu.org/about.html
25. http://validator.w3.org/check/referer
19. http://gcc.gnu.org/bugzilla/buglist.cgi?bug_status=RESOLVED&resolution=FIXED&target_milestone=4.4.7
20. http://gcc.gnu.org/onlinedocs/
21. mailto:gcc-help@gcc.gnu.org
22. mailto:gcc@gcc.gnu.org
23. http://gcc.gnu.org/lists.html
24. http://www.fsf.org/
25. http://gcc.gnu.org/about.html
26. http://validator.w3.org/check/referer
======================================================================
http://gcc.gnu.org/gcc-4.3/index.html
GCC 4.3 Release Series
May 22, 2010
Jun 27, 2011
The [1]GNU project and the GCC developers are pleased to announce the
release of GCC 4.3.5.
release of GCC 4.3.6.
This release is a bug-fix release, containing fixes for regressions in
GCC 4.3.4 relative to previous releases of GCC.
GCC 4.3.5 relative to previous releases of GCC.
Release History
GCC 4.3.6
Jun 27, 2011 ([2]changes)
GCC 4.3.5
May 22, 2010 ([2]changes)
May 22, 2010 ([3]changes)
GCC 4.3.4
August 4, 2009 ([3]changes)
August 4, 2009 ([4]changes)
GCC 4.3.3
January 24, 2009 ([4]changes)
January 24, 2009 ([5]changes)
GCC 4.3.2
August 27, 2008 ([5]changes)
August 27, 2008 ([6]changes)
GCC 4.3.1
June 6, 2008 ([6]changes)
June 6, 2008 ([7]changes)
GCC 4.3.0
March 5, 2008 ([7]changes)
March 5, 2008 ([8]changes)
References and Acknowledgements
@ -1523,33 +1551,33 @@ References and Acknowledgements
supports several other languages aside from C, it now stands for the
GNU Compiler Collection.
A list of [8]successful builds is updated as new information becomes
A list of [9]successful builds is updated as new information becomes
available.
The GCC developers would like to thank the numerous people that have
contributed new features, improvements, bug fixes, and other changes as
well as test results to GCC. This [9]amazing group of volunteers is
well as test results to GCC. This [10]amazing group of volunteers is
what makes GCC successful.
For additional information about GCC please refer to the [10]GCC
project web site or contact the [11]GCC development mailing list.
For additional information about GCC please refer to the [11]GCC
project web site or contact the [12]GCC development mailing list.
To obtain GCC please use [12]our mirror sites or [13]our SVN server.
To obtain GCC please use [13]our mirror sites or [14]our SVN server.
For questions related to the use of GCC, please consult these web
pages and the [14]GCC manuals. If that fails, the
[15]gcc-help@gcc.gnu.org mailing list might help. Comments on these
pages and the [15]GCC manuals. If that fails, the
[16]gcc-help@gcc.gnu.org mailing list might help. Comments on these
web pages and the development of GCC are welcome on our developer
list at [16]gcc@gcc.gnu.org. All of [17]our lists have public
list at [17]gcc@gcc.gnu.org. All of [18]our lists have public
archives.
Copyright (C) [18]Free Software Foundation, Inc. Verbatim copying and
Copyright (C) [19]Free Software Foundation, Inc. Verbatim copying and
distribution of this entire article is permitted in any medium,
provided this notice is preserved.
These pages are [19]maintained by the GCC team. Last modified
2011-04-25[20].
These pages are [20]maintained by the GCC team. Last modified
2011-06-27[21].
References
@ -1560,19 +1588,20 @@ References
5. http://gcc.gnu.org/gcc-4.3/changes.html
6. http://gcc.gnu.org/gcc-4.3/changes.html
7. http://gcc.gnu.org/gcc-4.3/changes.html
8. http://gcc.gnu.org/gcc-4.3/buildstat.html
9. http://gcc.gnu.org/onlinedocs/gcc/Contributors.html
10. http://gcc.gnu.org/index.html
11. mailto:gcc@gcc.gnu.org
12. http://gcc.gnu.org/mirrors.html
13. http://gcc.gnu.org/svn.html
14. http://gcc.gnu.org/onlinedocs/
15. mailto:gcc-help@gcc.gnu.org
16. mailto:gcc@gcc.gnu.org
17. http://gcc.gnu.org/lists.html
18. http://www.fsf.org/
19. http://gcc.gnu.org/about.html
20. http://validator.w3.org/check/referer
8. http://gcc.gnu.org/gcc-4.3/changes.html
9. http://gcc.gnu.org/gcc-4.3/buildstat.html
10. http://gcc.gnu.org/onlinedocs/gcc/Contributors.html
11. http://gcc.gnu.org/index.html
12. mailto:gcc@gcc.gnu.org
13. http://gcc.gnu.org/mirrors.html
14. http://gcc.gnu.org/svn.html
15. http://gcc.gnu.org/onlinedocs/
16. mailto:gcc-help@gcc.gnu.org
17. mailto:gcc@gcc.gnu.org
18. http://gcc.gnu.org/lists.html
19. http://www.fsf.org/
20. http://gcc.gnu.org/about.html
21. http://validator.w3.org/check/referer
======================================================================
http://gcc.gnu.org/gcc-4.3/changes.html
@ -2229,6 +2258,11 @@ New Targets and Target Specific Improvements
sign-bit and infinity checks of binary and decimal floating
point numbers.
SPARC
* Support for the Sun UltraSPARC T2 (Niagara 2) processor has been
added.
Xtensa
* Stack unwinding for exception handling now uses by default a
@ -2329,20 +2363,27 @@ GCC 4.3.5
not be complete (that is, it is possible that some PRs that have been
fixed are not listed here).
GCC 4.3.6
This is the [30]list of problem reports (PRs) from GCC's bug tracking
system that are known to be fixed in the 4.3.6 release. This list might
not be complete (that is, it is possible that some PRs that have been
fixed are not listed here).
For questions related to the use of GCC, please consult these web
pages and the [30]GCC manuals. If that fails, the
[31]gcc-help@gcc.gnu.org mailing list might help. Comments on these
pages and the [31]GCC manuals. If that fails, the
[32]gcc-help@gcc.gnu.org mailing list might help. Comments on these
web pages and the development of GCC are welcome on our developer
list at [32]gcc@gcc.gnu.org. All of [33]our lists have public
list at [33]gcc@gcc.gnu.org. All of [34]our lists have public
archives.
Copyright (C) [34]Free Software Foundation, Inc. Verbatim copying and
Copyright (C) [35]Free Software Foundation, Inc. Verbatim copying and
distribution of this entire article is permitted in any medium,
provided this notice is preserved.
These pages are [35]maintained by the GCC team. Last modified
2011-04-25[36].
These pages are [36]maintained by the GCC team. Last modified
2011-09-12[37].
References
@ -2375,13 +2416,14 @@ References
27. http://gcc.gnu.org/bugzilla/buglist.cgi?bug_status=RESOLVED&resolution=FIXED&target_milestone=4.3.3
28. http://gcc.gnu.org/bugzilla/buglist.cgi?bug_status=RESOLVED&resolution=FIXED&target_milestone=4.3.4
29. http://gcc.gnu.org/bugzilla/buglist.cgi?bug_status=RESOLVED&resolution=FIXED&target_milestone=4.3.5
30. http://gcc.gnu.org/onlinedocs/
31. mailto:gcc-help@gcc.gnu.org
32. mailto:gcc@gcc.gnu.org
33. http://gcc.gnu.org/lists.html
34. http://www.fsf.org/
35. http://gcc.gnu.org/about.html
36. http://validator.w3.org/check/referer
30. http://gcc.gnu.org/bugzilla/buglist.cgi?bug_status=RESOLVED&resolution=FIXED&target_milestone=4.3.6
31. http://gcc.gnu.org/onlinedocs/
32. mailto:gcc-help@gcc.gnu.org
33. mailto:gcc@gcc.gnu.org
34. http://gcc.gnu.org/lists.html
35. http://www.fsf.org/
36. http://gcc.gnu.org/about.html
37. http://validator.w3.org/check/referer
======================================================================
http://gcc.gnu.org/gcc-4.2/index.html
@ -4017,7 +4059,7 @@ GCC 4.0.4
provided this notice is preserved.
These pages are [21]maintained by the GCC team. Last modified
2011-04-25[22].
2012-02-20[22].
References
@ -4028,7 +4070,7 @@ References
5. http://gcc.gnu.org/news/sms.html
6. http://www.akkadia.org/drepper/dsohowto.pdf
7. http://gcc.gnu.org/gcc-4.0/changes.html#visibility
8. http://www.codesourcery.com/public/cxx-abi/
8. http://sourcery.mentor.com/public/cxx-abi/
9. http://gcc.gnu.org/fortran/
10. http://gcc.gnu.org/install/
11. http://gcc.gnu.org/wiki/Visibility
@ -4826,8 +4868,8 @@ New Targets and Target Specific Improvements
M32R
* Support for the M32R/2 processor has been added by Renesas.
* Support for an M32R Linux target and PIC code generation has been
added by Renesas.
* Support for an M32R GNU/Linux target and PIC code generation has
been added by Renesas.
M68000
@ -5905,7 +5947,7 @@ GCC 3.4.6
provided this notice is preserved.
These pages are [417]maintained by the GCC team. Last modified
2011-04-25[418].
2012-04-24[418].
References
@ -5916,8 +5958,8 @@ References
5. http://gcc.gnu.org/gcc-3.4/mips-abi.html
6. http://gcc.gnu.org/gcc-3.4/sparc-abi.html
7. http://www.boost.org/
8. http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11953
9. http://gcc.gnu.org/bugzilla/show_bug.cgi?id=8361
8. http://gcc.gnu.org/PR11953
9. http://gcc.gnu.org/PR8361
10. http://gcc.gnu.org/onlinedocs/gcc-3.4.3/gcc/Other-Builtins.html#Other%20Builtins
11. http://www.open-std.org/jtc1/sc22/wg21/docs/cwg_closed.html#209
12. http://gcc.gnu.org/bugs/#cxx_rvalbind
@ -6574,7 +6616,7 @@ New Targets and Target Specific Improvements
+ The 32-bit port now supports weak symbols under HP-UX 11.
+ The handling of initializers and finalizers has been improved
under HP-UX 11. The 64-bit port no longer uses collect2.
+ Dwarf2 EH support has been added to the 32-bit linux port.
+ Dwarf2 EH support has been added to the 32-bit GNU/Linux port.
+ ABI fixes to correct the passing of small structures by value.
* The SPARC, HP-PA, SH4, and x86/pentium ports have been converted to
use the DFA processor pipeline description.
@ -7170,7 +7212,7 @@ GCC 3.3.1
with negative argument
* [268]11098 g++ doesn't emit complete debugging information for
local variables in destructors
* [269]11137 Linux shared library constructors not called unless
* [269]11137 GNU/Linux shared library constructors not called unless
there's one global object
* [270]11154 spurious ambiguity report for template class
specialization
@ -7777,7 +7819,7 @@ GCC 3.3.6
provided this notice is preserved.
These pages are [558]maintained by the GCC team. Last modified
2011-04-25[559].
2011-10-24[559].
References
@ -8929,8 +8971,8 @@ GCC 3.2.1
* [208]6984: wrong code generated with -O2, -O3, -Os for do-while
loop on PowerPC
* [209]7114: PowerPC: ICE building strcoll.op from glibc-2.2.5
* [210]7130: miscompiled code for GCC-3.1 in powerpc linux with
-funroll-all-loops
* [210]7130: miscompiled code for GCC-3.1 on
powerpc-unknown-linux-gnu with -funroll-all-loops
* [211]7133: PowerPC ICE: unrecognizable insn
* [212]7380: ICE in extract_insn, at recog.c:2148
* [213]8252: ICE on Altivec code with optimization turned on
@ -9032,7 +9074,7 @@ GCC 3.2
provided this notice is preserved.
These pages are [251]maintained by the GCC team. Last modified
2011-04-25[252].
2011-10-24[252].
References
@ -10646,7 +10688,7 @@ http://gcc.gnu.org/egcs-1.1/index.html
+ Fix problems with ctors/dtors in SCO shared libraries.
+ Abort instead of generating incorrect code for PPro/PII
floating point conditional moves.
+ Avoid multiply defined symbols on Linux/GNU systems using
+ Avoid multiply defined symbols on GNU/Linux systems using
libc-5.4.xx.
+ Fix abort in alpha compiler.
* Fortran-specific fixes
@ -10689,7 +10731,7 @@ http://gcc.gnu.org/egcs-1.1/index.html
provided this notice is preserved.
These pages are [16]maintained by the GCC team. Last modified
2011-04-25[17].
2011-10-24[17].
References
@ -10926,7 +10968,7 @@ http://gcc.gnu.org/egcs-1.0/index.html
contain C++ code (upgrade to 1.0.1 and use that).
* Various bugfixes in the x86, hppa, mips, and rs6000/ppc backends.
The x86 changes fix code generation errors exposed when building
glibc2 and the Linux dynamic linker (ld.so).
glibc2 and the usual GNU/Linux dynamic linker (ld.so).
The hppa change fixes a compiler abort when configured for use with
RTEMS.
The MIPS changes fix problems with the definition of LONG_MAX on
@ -10953,7 +10995,7 @@ http://gcc.gnu.org/egcs-1.0/index.html
* g++/libstdc++ improvements and fixes
+ libstdc++ in the EGCS release has been updated and should be
link compatible with libstdc++-2.8.
+ Various fixes in libio/libstdc++ to work better on Linux
+ Various fixes in libio/libstdc++ to work better on GNU/Linux
systems.
+ Fix problems with duplicate symbols on systems that do not
support weak symbols.
@ -10976,9 +11018,9 @@ http://gcc.gnu.org/egcs-1.0/index.html
+ x86 ports define i386 again to keep imake happy.
+ Fix exception handling support on NetBSD ports.
+ Several changes to collect2 to fix many problems with AIX.
+ Define __ELF__ for rs6000/linux.
+ Fix -mcall-linux problem on rs6000/linux.
+ Fix stdarg/vararg problem for rs6000/linux.
+ Define __ELF__ for GNU/Linux on rs6000.
+ Fix -mcall-linux problem on GNU/Linux on rs6000.
+ Fix stdarg/vararg problem for GNU/Linux on rs6000.
+ Allow autoconf to select a proper install problem on AIX 3.1.
+ m68k port support includes -mcpu32 option as well as cpu32
multilibs.
@ -11042,7 +11084,7 @@ http://gcc.gnu.org/egcs-1.0/index.html
provided this notice is preserved.
These pages are [11]maintained by the GCC team. Last modified
2011-04-25[12].
2011-10-24[12].
References
@ -11069,7 +11111,7 @@ http://gcc.gnu.org/egcs-1.0/features.html
* Vast improvements in the C++ compiler; so many they have [2]page of
their own!
* Integrated C++ runtime libraries, including support for most major
linux systems!
GNU/Linux systems!
* New instruction scheduler from IBM Haifa which includes support for
function wide instruction scheduling as well as superscalar
scheduling.
@ -11087,7 +11129,7 @@ http://gcc.gnu.org/egcs-1.0/features.html
Openserver 5 family (5.0.{0,2,4} and Internet FastStart 1.0 and
1.1), Support for RTEMS on several embedded targets, Support for
arm-linux, Mitsubishi M32R, Hitachi H8/S, Matsushita MN102 and
MN103, NEC V850, Sparclet, Solaris & Linux on PowerPCs, etc.
MN103, NEC V850, Sparclet, Solaris & GNU/Linux on PowerPCs, etc.
* Integrated testsuites for gcc, g++, g77, libstdc++ and libio.
* RS6000/PowerPC ports generate code which can run on all
RS6000/PowerPC variants by default.
@ -11095,7 +11137,7 @@ http://gcc.gnu.org/egcs-1.0/features.html
control over how the x86 port generates code.
* Includes the template repository patch (aka repo patch); note the
new template code makes repo obsolete for ELF systems using gnu-ld
such as Linux.
such as GNU/Linux.
* Plus the usual assortment of bugfixes and improvements.
@ -11110,7 +11152,7 @@ http://gcc.gnu.org/egcs-1.0/features.html
provided this notice is preserved.
These pages are [8]maintained by the GCC team. Last modified
2011-04-25[9].
2011-10-24[9].
References

14
external/gpl3/gcc/dist/config/ChangeLog vendored
View File

@ -1,3 +1,17 @@
2012-07-02 Release Manager
* GCC 4.5.4 released.
2011-12-18 Eric Botcazou <ebotcazou@adacore.com>
* acx.m4 (Test for GNAT): Update comment and add quotes in final test.
2011-06-19 Jack Howarth <howarth@bromo.med.uc.edu>
PR target/49461
* mh-x86-darwin: Add file and pass -no_pie on BOOT_LDFLAGS for
darwin11.
2011-04-28 Release Manager
* GCC 4.5.3 released.

8
external/gpl3/gcc/dist/config/acx.m4 vendored
View File

@ -356,9 +356,9 @@ m4_define([AC_CHECK_HEADER],m4_defn([_AC_CHECK_HEADER_OLD]))
ac_c_preproc_warn_flag=yes])# AC_PROG_CPP_WERROR
# Test for GNAT.
# We require the gnatbind program, and a compiler driver that
# understands Ada. We use the user's CC setting, already found,
# and possibly add $1 to the command-line parameters.
# We require the gnatbind & gnatmake programs, as well as a compiler driver
# that understands Ada. We use the user's CC setting, already found, and
# possibly add $1 to the command-line parameters.
#
# Sets the shell variable have_gnat to yes or no as appropriate, and
# substitutes GNATBIND and GNATMAKE.
@ -387,7 +387,7 @@ if test x"$errors" = x && test -f conftest.$ac_objext; then
fi
rm -f conftest.*])
if test x$GNATBIND != xno && test x$GNATMAKE != xno && test x$acx_cv_cc_gcc_supports_ada != xno; then
if test "x$GNATBIND" != xno && test "x$GNATMAKE" != xno && test x$acx_cv_cc_gcc_supports_ada != xno; then
have_gnat=yes
else
have_gnat=no

2
external/gpl3/gcc/dist/config/mh-x86-darwin vendored Normal file
View File

@ -0,0 +1,2 @@
# Ensure we don't try and use -pie, as it is incompatible with pch.
BOOT_LDFLAGS += `case ${host} in *-*-darwin[1][1-9]*) echo -Wl,-no_pie ;; esac;`

4
external/gpl3/gcc/dist/contrib/ChangeLog vendored
View File

@ -1,3 +1,7 @@
2012-07-02 Release Manager
* GCC 4.5.4 released.
2011-04-28 Release Manager
* GCC 4.5.3 released.

4
external/gpl3/gcc/dist/contrib/reghunt/ChangeLog vendored
View File

@ -1,3 +1,7 @@
2012-07-02 Release Manager
* GCC 4.5.4 released.
2011-04-28 Release Manager
* GCC 4.5.3 released.

4
external/gpl3/gcc/dist/contrib/regression/ChangeLog vendored
View File

@ -1,3 +1,7 @@
2012-07-02 Release Manager
* GCC 4.5.4 released.
2011-04-28 Release Manager
* GCC 4.5.3 released.

4
external/gpl3/gcc/dist/fixincludes/ChangeLog vendored
View File

@ -1,3 +1,7 @@
2012-07-02 Release Manager
* GCC 4.5.4 released.
2011-04-28 Release Manager
* GCC 4.5.3 released.

2
external/gpl3/gcc/dist/gcc/BASE-VER vendored
View File

@ -1 +1 @@
4.5.3
4.5.4

2
external/gpl3/gcc/dist/gcc/DATESTAMP vendored
View File

@ -1 +1 @@
20110428
20120702

15
external/gpl3/gcc/dist/gcc/c-common.c vendored
View File

@ -4031,14 +4031,15 @@ c_common_truthvalue_conversion (location_t location, tree expr)
/* Distribute the conversion into the arms of a COND_EXPR. */
if (c_dialect_cxx ())
{
tree op1 = TREE_OPERAND (expr, 1);
tree op2 = TREE_OPERAND (expr, 2);
/* In C++ one of the arms might have void type if it is throw. */
if (!VOID_TYPE_P (TREE_TYPE (op1)))
op1 = c_common_truthvalue_conversion (location, op1);
if (!VOID_TYPE_P (TREE_TYPE (op2)))
op2 = c_common_truthvalue_conversion (location, op2);
expr = fold_build3_loc (location, COND_EXPR, truthvalue_type_node,
TREE_OPERAND (expr, 0),
c_common_truthvalue_conversion (location,
TREE_OPERAND (expr,
1)),
c_common_truthvalue_conversion (location,
TREE_OPERAND (expr,
2)));
TREE_OPERAND (expr, 0), op1, op2);
goto ret;
}
else

5
external/gpl3/gcc/dist/gcc/c-decl.c vendored
View File

@ -3909,7 +3909,7 @@ start_decl (struct c_declarator *declarator, struct c_declspecs *declspecs,
return 0;
if (expr)
add_stmt (expr);
add_stmt (fold_convert (void_type_node, expr));
if (TREE_CODE (decl) != FUNCTION_DECL && MAIN_NAME_P (DECL_NAME (decl)))
warning (OPT_Wmain, "%q+D is usually a function", decl);
@ -7385,7 +7385,8 @@ start_function (struct c_declspecs *declspecs, struct c_declarator *declarator,
/* If the declarator is not suitable for a function definition,
cause a syntax error. */
if (decl1 == 0)
if (decl1 == 0
|| TREE_CODE (decl1) != FUNCTION_DECL)
return 0;
loc = DECL_SOURCE_LOCATION (decl1);

9
external/gpl3/gcc/dist/gcc/c-typeck.c vendored
View File

@ -4219,6 +4219,11 @@ build_conditional_expr (location_t colon_loc, tree ifexp, bool ifexp_bcp,
ret = fold_build3_loc (colon_loc, COND_EXPR, result_type, ifexp, op1, op2);
else
{
if (int_operands)
{
op1 = remove_c_maybe_const_expr (op1);
op2 = remove_c_maybe_const_expr (op2);
}
ret = build3 (COND_EXPR, result_type, ifexp, op1, op2);
if (int_operands)
ret = note_integer_operands (ret);
@ -9655,6 +9660,7 @@ build_binary_op (location_t location, enum tree_code code,
{
case MULT_EXPR:
case TRUNC_DIV_EXPR:
op1 = c_save_expr (op1);
imag = build2 (resultcode, real_type, imag, op1);
/* Fall through. */
case PLUS_EXPR:
@ -9675,6 +9681,7 @@ build_binary_op (location_t location, enum tree_code code,
switch (code)
{
case MULT_EXPR:
op0 = c_save_expr (op0);
imag = build2 (resultcode, real_type, op0, imag);
/* Fall through. */
case PLUS_EXPR:
@ -9800,7 +9807,7 @@ build_binary_op (location_t location, enum tree_code code,
warn_for_sign_compare (location, orig_op0_folded,
orig_op1_folded, op0, op1,
result_type, resultcode);
if (!in_late_binary_op)
if (!in_late_binary_op && !int_operands)
{
if (!op0_maybe_const || TREE_CODE (op0) != INTEGER_CST)
op0 = c_wrap_maybe_const (op0, !op0_maybe_const);

162
external/gpl3/gcc/dist/gcc/caller-save.c vendored
View File

@ -439,101 +439,93 @@ saved_hard_reg_compare_func (const void *v1p, const void *v2p)
void
setup_save_areas (void)
{
int i, j, k;
unsigned int r;
int i, j, k, freq;
HARD_REG_SET hard_regs_used;
struct saved_hard_reg *saved_reg;
rtx insn;
struct insn_chain *chain, *next;
unsigned int regno;
HARD_REG_SET hard_regs_to_save, used_regs, this_insn_sets;
reg_set_iterator rsi;
/* Allocate space in the save area for the largest multi-register
pseudos first, then work backwards to single register
pseudos. */
/* Find and record all call-used hard-registers in this function. */
CLEAR_HARD_REG_SET (hard_regs_used);
for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
if (reg_renumber[i] >= 0 && REG_N_CALLS_CROSSED (i) > 0)
{
unsigned int regno = reg_renumber[i];
unsigned int endregno
= end_hard_regno (GET_MODE (regno_reg_rtx[i]), regno);
for (r = regno; r < endregno; r++)
if (call_used_regs[r])
SET_HARD_REG_BIT (hard_regs_used, r);
}
/* Find every CALL_INSN and record which hard regs are live across the
call into HARD_REG_MAP and HARD_REGS_USED. */
initiate_saved_hard_regs ();
/* Create hard reg saved regs. */
for (chain = reload_insn_chain; chain != 0; chain = next)
{
insn = chain->insn;
next = chain->next;
if (!CALL_P (insn)
|| find_reg_note (insn, REG_NORETURN, NULL))
continue;
freq = REG_FREQ_FROM_BB (BLOCK_FOR_INSN (insn));
REG_SET_TO_HARD_REG_SET (hard_regs_to_save,
&chain->live_throughout);
COPY_HARD_REG_SET (used_regs, call_used_reg_set);
/* Record all registers set in this call insn. These don't
need to be saved. N.B. the call insn might set a subreg
of a multi-hard-reg pseudo; then the pseudo is considered
live during the call, but the subreg that is set
isn't. */
CLEAR_HARD_REG_SET (this_insn_sets);
note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets);
/* Sibcalls are considered to set the return value. */
if (SIBLING_CALL_P (insn) && crtl->return_rtx)
mark_set_regs (crtl->return_rtx, NULL_RTX, &this_insn_sets);
AND_COMPL_HARD_REG_SET (used_regs, call_fixed_reg_set);
AND_COMPL_HARD_REG_SET (used_regs, this_insn_sets);
AND_HARD_REG_SET (hard_regs_to_save, used_regs);
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
if (TEST_HARD_REG_BIT (hard_regs_to_save, regno))
{
if (hard_reg_map[regno] != NULL)
hard_reg_map[regno]->call_freq += freq;
else
saved_reg = new_saved_hard_reg (regno, freq);
SET_HARD_REG_BIT (hard_regs_used, regno);
}
/* Look through all live pseudos, mark their hard registers. */
EXECUTE_IF_SET_IN_REG_SET
(&chain->live_throughout, FIRST_PSEUDO_REGISTER, regno, rsi)
{
int r = reg_renumber[regno];
int bound;
if (r < 0)
continue;
bound = r + hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
for (; r < bound; r++)
if (TEST_HARD_REG_BIT (used_regs, r))
{
if (hard_reg_map[r] != NULL)
hard_reg_map[r]->call_freq += freq;
else
saved_reg = new_saved_hard_reg (r, freq);
SET_HARD_REG_BIT (hard_regs_to_save, r);
SET_HARD_REG_BIT (hard_regs_used, r);
}
}
}
/* If requested, figure out which hard regs can share save slots. */
if (optimize && flag_ira_share_save_slots)
{
rtx insn, slot;
struct insn_chain *chain, *next;
rtx slot;
char *saved_reg_conflicts;
unsigned int regno;
int next_k, freq;
struct saved_hard_reg *saved_reg, *saved_reg2, *saved_reg3;
int next_k;
struct saved_hard_reg *saved_reg2, *saved_reg3;
int call_saved_regs_num;
struct saved_hard_reg *call_saved_regs[FIRST_PSEUDO_REGISTER];
HARD_REG_SET hard_regs_to_save, used_regs, this_insn_sets;
reg_set_iterator rsi;
int best_slot_num;
int prev_save_slots_num;
rtx prev_save_slots[FIRST_PSEUDO_REGISTER];
initiate_saved_hard_regs ();
/* Create hard reg saved regs. */
for (chain = reload_insn_chain; chain != 0; chain = next)
{
insn = chain->insn;
next = chain->next;
if (!CALL_P (insn)
|| find_reg_note (insn, REG_NORETURN, NULL))
continue;
freq = REG_FREQ_FROM_BB (BLOCK_FOR_INSN (insn));
REG_SET_TO_HARD_REG_SET (hard_regs_to_save,
&chain->live_throughout);
COPY_HARD_REG_SET (used_regs, call_used_reg_set);
/* Record all registers set in this call insn. These don't
need to be saved. N.B. the call insn might set a subreg
of a multi-hard-reg pseudo; then the pseudo is considered
live during the call, but the subreg that is set
isn't. */
CLEAR_HARD_REG_SET (this_insn_sets);
note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets);
/* Sibcalls are considered to set the return value. */
if (SIBLING_CALL_P (insn) && crtl->return_rtx)
mark_set_regs (crtl->return_rtx, NULL_RTX, &this_insn_sets);
AND_COMPL_HARD_REG_SET (used_regs, call_fixed_reg_set);
AND_COMPL_HARD_REG_SET (used_regs, this_insn_sets);
AND_HARD_REG_SET (hard_regs_to_save, used_regs);
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
if (TEST_HARD_REG_BIT (hard_regs_to_save, regno))
{
if (hard_reg_map[regno] != NULL)
hard_reg_map[regno]->call_freq += freq;
else
saved_reg = new_saved_hard_reg (regno, freq);
}
/* Look through all live pseudos, mark their hard registers. */
EXECUTE_IF_SET_IN_REG_SET
(&chain->live_throughout, FIRST_PSEUDO_REGISTER, regno, rsi)
{
int r = reg_renumber[regno];
int bound;
if (r < 0)
continue;
bound = r + hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
for (; r < bound; r++)
if (TEST_HARD_REG_BIT (used_regs, r))
{
if (hard_reg_map[r] != NULL)
hard_reg_map[r]->call_freq += freq;
else
saved_reg = new_saved_hard_reg (r, freq);
SET_HARD_REG_BIT (hard_regs_to_save, r);
}
}
}
/* Find saved hard register conflicts. */
saved_reg_conflicts = (char *) xmalloc (saved_regs_num * saved_regs_num);
memset (saved_reg_conflicts, 0, saved_regs_num * saved_regs_num);
@ -691,8 +683,10 @@ setup_save_areas (void)
}
else
{
/* Now run through all the call-used hard-registers and allocate
space for them in the caller-save area. Try to allocate space
/* We are not sharing slots.
Run through all the call-used hard-registers and allocate
space for each in the caller-save area. Try to allocate space
in a manner which allows multi-register saves/restores to be done. */
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)

55
external/gpl3/gcc/dist/gcc/cfgrtl.c vendored
View File

@ -1116,6 +1116,7 @@ force_nonfallthru_and_redirect (edge e, basic_block target)
rtx note;
edge new_edge;
int abnormal_edge_flags = 0;
bool asm_goto_edge = false;
int loc;
/* In the case the last instruction is conditional jump to the next
@ -1195,8 +1196,28 @@ force_nonfallthru_and_redirect (edge e, basic_block target)
}
}
if (EDGE_COUNT (e->src->succs) >= 2 || abnormal_edge_flags)
/* If e->src ends with asm goto, see if any of the ASM_OPERANDS_LABELs
don't point to target label. */
if (JUMP_P (BB_END (e->src))
&& target != EXIT_BLOCK_PTR
&& e->dest == target
&& (e->flags & EDGE_FALLTHRU)
&& (note = extract_asm_operands (PATTERN (BB_END (e->src)))))
{
int i, n = ASM_OPERANDS_LABEL_LENGTH (note);
for (i = 0; i < n; ++i)
if (XEXP (ASM_OPERANDS_LABEL (note, i), 0) == BB_HEAD (target))
{
asm_goto_edge = true;
break;
}
}
if (EDGE_COUNT (e->src->succs) >= 2 || abnormal_edge_flags || asm_goto_edge)
{
gcov_type count = e->count;
int probability = e->probability;
/* Create the new structures. */
/* If the old block ended with a tablejump, skip its table
@ -1207,7 +1228,7 @@ force_nonfallthru_and_redirect (edge e, basic_block target)
note = NEXT_INSN (note);
jump_block = create_basic_block (note, NULL, e->src);
jump_block->count = e->count;
jump_block->count = count;
jump_block->frequency = EDGE_FREQUENCY (e);
jump_block->loop_depth = target->loop_depth;
@ -1223,13 +1244,27 @@ force_nonfallthru_and_redirect (edge e, basic_block target)
/* Wire edge in. */
new_edge = make_edge (e->src, jump_block, EDGE_FALLTHRU);
new_edge->probability = e->probability;
new_edge->count = e->count;
new_edge->probability = probability;
new_edge->count = count;
/* Redirect old edge. */
redirect_edge_pred (e, jump_block);
e->probability = REG_BR_PROB_BASE;
/* If asm goto has any label refs to target's label,
add also edge from asm goto bb to target. */
if (asm_goto_edge)
{
new_edge->probability /= 2;
new_edge->count /= 2;
jump_block->count /= 2;
jump_block->frequency /= 2;
new_edge = make_edge (new_edge->src, target,
e->flags & ~EDGE_FALLTHRU);
new_edge->probability = probability - probability / 2;
new_edge->count = count - count / 2;
}
new_bb = jump_block;
}
else
@ -1640,9 +1675,10 @@ rtl_dump_bb (basic_block bb, FILE *outf, int indent, int flags ATTRIBUTE_UNUSED)
putc ('\n', outf);
}
for (insn = BB_HEAD (bb), last = NEXT_INSN (BB_END (bb)); insn != last;
insn = NEXT_INSN (insn))
print_rtl_single (outf, insn);
if (bb->index != ENTRY_BLOCK && bb->index != EXIT_BLOCK)
for (insn = BB_HEAD (bb), last = NEXT_INSN (BB_END (bb)); insn != last;
insn = NEXT_INSN (insn))
print_rtl_single (outf, insn);
if (df)
{
@ -2754,6 +2790,11 @@ cfg_layout_merge_blocks (basic_block a, basic_block b)
rtx first = BB_END (a), last;
last = emit_insn_after_noloc (b->il.rtl->header, BB_END (a), a);
/* The above might add a BARRIER as BB_END, but as barriers
aren't valid parts of a bb, remove_insn doesn't update
BB_END if it is a barrier. So adjust BB_END here. */
while (BB_END (a) != first && BARRIER_P (BB_END (a)))
BB_END (a) = PREV_INSN (BB_END (a));
delete_insn_chain (NEXT_INSN (first), last, false);
b->il.rtl->header = NULL;
}

2
external/gpl3/gcc/dist/gcc/combine.c vendored
View File

@ -5298,7 +5298,7 @@ combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
{
/* Try to simplify the expression further. */
rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
temp = combine_simplify_rtx (tor, mode, in_dest);
temp = combine_simplify_rtx (tor, VOIDmode, in_dest);
/* If we could, great. If not, do not go ahead with the IOR
replacement, since PLUS appears in many special purpose

38
external/gpl3/gcc/dist/gcc/config/alpha/alpha.c vendored
View File

@ -2464,7 +2464,7 @@ alpha_emit_conditional_branch (rtx operands[], enum machine_mode cmp_mode)
{
case EQ: case LE: case LT: case LEU: case LTU:
case UNORDERED:
/* We have these compares: */
/* We have these compares. */
cmp_code = code, branch_code = NE;
break;
@ -2701,13 +2701,15 @@ alpha_emit_conditional_move (rtx cmp, enum machine_mode mode)
switch (code)
{
case EQ: case LE: case LT: case LEU: case LTU:
case UNORDERED:
/* We have these compares. */
cmp_code = code, code = NE;
break;
case NE:
/* This must be reversed. */
cmp_code = EQ, code = EQ;
case ORDERED:
/* These must be reversed. */
cmp_code = reverse_condition (code), code = EQ;
break;
case GE: case GT: case GEU: case GTU:
@ -2727,6 +2729,14 @@ alpha_emit_conditional_move (rtx cmp, enum machine_mode mode)
gcc_unreachable ();
}
if (cmp_mode == DImode)
{
if (!reg_or_0_operand (op0, DImode))
op0 = force_reg (DImode, op0);
if (!reg_or_8bit_operand (op1, DImode))
op1 = force_reg (DImode, op1);
}
tem = gen_reg_rtx (cmp_mode);
emit_insn (gen_rtx_SET (VOIDmode, tem,
gen_rtx_fmt_ee (cmp_code, cmp_mode,
@ -2738,6 +2748,14 @@ alpha_emit_conditional_move (rtx cmp, enum machine_mode mode)
local_fast_math = 1;
}
if (cmp_mode == DImode)
{
if (!reg_or_0_operand (op0, DImode))
op0 = force_reg (DImode, op0);
if (!reg_or_8bit_operand (op1, DImode))
op1 = force_reg (DImode, op1);
}
/* We may be able to use a conditional move directly.
This avoids emitting spurious compares. */
if (signed_comparison_operator (cmp, VOIDmode)
@ -2756,11 +2774,13 @@ alpha_emit_conditional_move (rtx cmp, enum machine_mode mode)
switch (code)
{
case EQ: case LE: case LT: case LEU: case LTU:
case UNORDERED:
/* We have these compares: */
break;
case NE:
/* This must be reversed. */
case ORDERED:
/* These must be reversed. */
code = reverse_condition (code);
cmov_code = EQ;
break;
@ -4915,6 +4935,13 @@ alpha_gp_save_rtx (void)
return m;
}
static void
alpha_instantiate_decls (void)
{
if (cfun->machine->gp_save_rtx != NULL_RTX)
instantiate_decl_rtl (cfun->machine->gp_save_rtx);
}
static int
alpha_ra_ever_killed (void)
{
@ -11125,6 +11152,9 @@ alpha_init_libfuncs (void)
#undef TARGET_TRAMPOLINE_INIT
#define TARGET_TRAMPOLINE_INIT alpha_trampoline_init
#undef TARGET_INSTANTIATE_DECLS
#define TARGET_INSTANTIATE_DECLS alpha_instantiate_decls
#undef TARGET_SECONDARY_RELOAD
#define TARGET_SECONDARY_RELOAD alpha_secondary_reload

35
external/gpl3/gcc/dist/gcc/config/alpha/linux-unwind.h vendored
View File

@ -1,5 +1,5 @@
/* DWARF2 EH unwinding support for Alpha Linux.
Copyright (C) 2004, 2005, 2009 Free Software Foundation, Inc.
Copyright (C) 2004, 2005, 2009, 2011, 2012 Free Software Foundation, Inc.
This file is part of GCC.
@ -36,25 +36,27 @@ alpha_fallback_frame_state (struct _Unwind_Context *context,
{
unsigned int *pc = context->ra;
struct sigcontext *sc;
long new_cfa, i;
long new_cfa;
int i;
if (pc[0] != 0x47fe0410 /* mov $30,$16 */
|| pc[2] != 0x00000083 /* callsys */)
|| pc[2] != 0x00000083) /* callsys */
return _URC_END_OF_STACK;
if (context->cfa == 0)
return _URC_END_OF_STACK;
if (pc[1] == 0x201f0067) /* lda $0,NR_sigreturn */
sc = context->cfa;
else if (pc[1] == 0x201f015f) /* lda $0,NR_rt_sigreturn */
else if (pc[1] == 0x201f015f) /* lda $0,NR_rt_sigreturn */
{
struct rt_sigframe {
struct siginfo info;
siginfo_t info;
struct ucontext uc;
} *rt_ = context->cfa;
sc = &rt_->uc.uc_mcontext;
}
else
return _URC_END_OF_STACK;
new_cfa = sc->sc_regs[30];
fs->regs.cfa_how = CFA_REG_OFFSET;
fs->regs.cfa_reg = 30;
@ -63,16 +65,35 @@ alpha_fallback_frame_state (struct _Unwind_Context *context,
{
fs->regs.reg[i].how = REG_SAVED_OFFSET;
fs->regs.reg[i].loc.offset
= (long)&sc->sc_regs[i] - new_cfa;
= (long) &sc->sc_regs[i] - new_cfa;
}
for (i = 0; i < 31; ++i)
{
fs->regs.reg[i+32].how = REG_SAVED_OFFSET;
fs->regs.reg[i+32].loc.offset
= (long)&sc->sc_fpregs[i] - new_cfa;
= (long) &sc->sc_fpregs[i] - new_cfa;
}
fs->regs.reg[64].how = REG_SAVED_OFFSET;
fs->regs.reg[64].loc.offset = (long)&sc->sc_pc - new_cfa;
fs->retaddr_column = 64;
fs->signal_frame = 1;
return _URC_NO_REASON;
}
#define MD_FROB_UPDATE_CONTEXT alpha_frob_update_context
/* Fix up for signal handlers that don't have S flag set. */
static void
alpha_frob_update_context (struct _Unwind_Context *context,
_Unwind_FrameState *fs ATTRIBUTE_UNUSED)
{
unsigned int *pc = context->ra;
if (pc[0] == 0x47fe0410 /* mov $30,$16 */
&& pc[2] == 0x00000083 /* callsys */
&& (pc[1] == 0x201f0067 /* lda $0,NR_sigreturn */
|| pc[1] == 0x201f015f)) /* lda $0,NR_rt_sigreturn */
_Unwind_SetSignalFrame (context, 1);
}

28
external/gpl3/gcc/dist/gcc/config/arm/arm.c vendored
View File

@ -3338,6 +3338,10 @@ arm_libcall_uses_aapcs_base (const_rtx libcall)
convert_optab_libfunc (sext_optab, SFmode, HFmode));
add_libcall (libcall_htab,
convert_optab_libfunc (trunc_optab, HFmode, SFmode));
add_libcall (libcall_htab,
convert_optab_libfunc (sfix_optab, SImode, DFmode));
add_libcall (libcall_htab,
convert_optab_libfunc (ufix_optab, SImode, DFmode));
add_libcall (libcall_htab,
convert_optab_libfunc (sfix_optab, DImode, DFmode));
add_libcall (libcall_htab,
@ -3346,6 +3350,28 @@ arm_libcall_uses_aapcs_base (const_rtx libcall)
convert_optab_libfunc (sfix_optab, DImode, SFmode));
add_libcall (libcall_htab,
convert_optab_libfunc (ufix_optab, DImode, SFmode));
/* Values from double-precision helper functions are returned in core
registers if the selected core only supports single-precision
arithmetic, even if we are using the hard-float ABI. The same is
true for single-precision helpers, but we will never be using the
hard-float ABI on a CPU which doesn't support single-precision
operations in hardware. */
add_libcall (libcall_htab, optab_libfunc (add_optab, DFmode));
add_libcall (libcall_htab, optab_libfunc (sdiv_optab, DFmode));
add_libcall (libcall_htab, optab_libfunc (smul_optab, DFmode));
add_libcall (libcall_htab, optab_libfunc (neg_optab, DFmode));
add_libcall (libcall_htab, optab_libfunc (sub_optab, DFmode));
add_libcall (libcall_htab, optab_libfunc (eq_optab, DFmode));
add_libcall (libcall_htab, optab_libfunc (lt_optab, DFmode));
add_libcall (libcall_htab, optab_libfunc (le_optab, DFmode));
add_libcall (libcall_htab, optab_libfunc (ge_optab, DFmode));
add_libcall (libcall_htab, optab_libfunc (gt_optab, DFmode));
add_libcall (libcall_htab, optab_libfunc (unord_optab, DFmode));
add_libcall (libcall_htab, convert_optab_libfunc (sext_optab, DFmode,
SFmode));
add_libcall (libcall_htab, convert_optab_libfunc (trunc_optab, SFmode,
DFmode));
}
return libcall && htab_find (libcall_htab, libcall) != NULL;
@ -18237,7 +18263,7 @@ neon_emit_pair_result_insn (enum machine_mode mode,
rtx tmp1 = gen_reg_rtx (mode);
rtx tmp2 = gen_reg_rtx (mode);
emit_insn (intfn (tmp1, op1, tmp2, op2));
emit_insn (intfn (tmp1, op1, op2, tmp2));
emit_move_insn (mem, tmp1);
mem = adjust_address (mem, mode, GET_MODE_SIZE (mode));

39
external/gpl3/gcc/dist/gcc/config/arm/neon.md vendored
View File

@ -680,7 +680,7 @@
(match_operand:SI 2 "immediate_operand" "i")))]
"TARGET_NEON"
{
int elt = ffs ((int) INTVAL (operands[2]) - 1);
int elt = ffs ((int) INTVAL (operands[2])) - 1;
if (BYTES_BIG_ENDIAN)
elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
operands[2] = GEN_INT (elt);
@ -3895,13 +3895,14 @@
(define_insn "neon_vtrn<mode>_internal"
[(set (match_operand:VDQW 0 "s_register_operand" "=w")
(unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")]
UNSPEC_VTRN1))
(set (match_operand:VDQW 2 "s_register_operand" "=w")
(unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")]
UNSPEC_VTRN2))]
(unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
(match_operand:VDQW 2 "s_register_operand" "w")]
UNSPEC_VTRN1))
(set (match_operand:VDQW 3 "s_register_operand" "=2")
(unspec:VDQW [(match_dup 1) (match_dup 2)]
UNSPEC_VTRN2))]
"TARGET_NEON"
"vtrn.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
"vtrn.<V_sz_elem>\t%<V_reg>0, %<V_reg>3"
[(set (attr "neon_type")
(if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
(const_string "neon_bp_simple")
@ -3921,13 +3922,14 @@
(define_insn "neon_vzip<mode>_internal"
[(set (match_operand:VDQW 0 "s_register_operand" "=w")
(unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")]
UNSPEC_VZIP1))
(set (match_operand:VDQW 2 "s_register_operand" "=w")
(unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")]
UNSPEC_VZIP2))]
(unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
(match_operand:VDQW 2 "s_register_operand" "w")]
UNSPEC_VZIP1))
(set (match_operand:VDQW 3 "s_register_operand" "=2")
(unspec:VDQW [(match_dup 1) (match_dup 2)]
UNSPEC_VZIP2))]
"TARGET_NEON"
"vzip.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
"vzip.<V_sz_elem>\t%<V_reg>0, %<V_reg>3"
[(set (attr "neon_type")
(if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
(const_string "neon_bp_simple")
@ -3947,13 +3949,14 @@
(define_insn "neon_vuzp<mode>_internal"
[(set (match_operand:VDQW 0 "s_register_operand" "=w")
(unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")]
(unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
(match_operand:VDQW 2 "s_register_operand" "w")]
UNSPEC_VUZP1))
(set (match_operand:VDQW 2 "s_register_operand" "=w")
(unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")]
UNSPEC_VUZP2))]
(set (match_operand:VDQW 3 "s_register_operand" "=2")
(unspec:VDQW [(match_dup 1) (match_dup 2)]
UNSPEC_VUZP2))]
"TARGET_NEON"
"vuzp.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
"vuzp.<V_sz_elem>\t%<V_reg>0, %<V_reg>3"
[(set (attr "neon_type")
(if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
(const_string "neon_bp_simple")

9
external/gpl3/gcc/dist/gcc/config/arm/thumb2.md vendored
View File

@ -380,7 +380,7 @@
(not:SI (match_operator:SI 1 "arm_comparison_operator"
[(match_operand 2 "cc_register" "") (const_int 0)])))]
"TARGET_THUMB2"
"ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #1"
"ite\\t%D1\;mvn%D1\\t%0, #0\;mvn%d1\\t%0, #1"
[(set_attr "conds" "use")
(set_attr "length" "10")]
)
@ -1108,6 +1108,7 @@
(match_operand:SI 2 "low_reg_or_int_operand" "")]))]
"TARGET_THUMB2
&& peep2_regno_dead_p(0, CC_REGNUM)
&& (CONST_INT_P (operands[2]) || operands[1] == operands[0])
&& ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
|| REG_P(operands[2]))"
[(parallel
@ -1120,10 +1121,10 @@
)
(define_insn "*thumb2_shiftsi3_short"
[(set (match_operand:SI 0 "low_register_operand" "=l")
[(set (match_operand:SI 0 "low_register_operand" "=l,l")
(match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "low_register_operand" "l")
(match_operand:SI 2 "low_reg_or_int_operand" "lM")]))
[(match_operand:SI 1 "low_register_operand" "0,l")
(match_operand:SI 2 "low_reg_or_int_operand" "l,M")]))
(clobber (reg:CC CC_REGNUM))]
"TARGET_THUMB2 && reload_completed
&& ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)

66
external/gpl3/gcc/dist/gcc/config/avr/avr-stdint.h vendored Normal file
View File

@ -0,0 +1,66 @@
/* Definitions for <stdint.h> types on systems using newlib.
Copyright (C) 2012 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/*
The intention of this file is to supply definitions that work with
avr-gcc's -mint8 that sets int to an 8-bit type.
This file is intended to yield the same results as newlib-stdint.h,
but there are some differences to newlib-stdint.h:
- AVR is an 8-bit architecture that cannot access 16-bit values
atomically, this SIG_ATOMIC_TYPE is "char".
- For the same reason, [u]int_fast8_t is defined as 8-bit type.
*/
#define SIG_ATOMIC_TYPE "char"
#define INT8_TYPE "signed char"
#define INT16_TYPE (INT_TYPE_SIZE == 16 ? "short int" : "long int")
#define INT32_TYPE (INT_TYPE_SIZE == 16 ? "long int" : "long long int")
#define INT64_TYPE (INT_TYPE_SIZE == 16 ? "long long int" : 0)
#define UINT8_TYPE "unsigned char"
#define UINT16_TYPE (INT_TYPE_SIZE == 16 ? "short unsigned int" : "long unsigned int")
#define UINT32_TYPE (INT_TYPE_SIZE == 16 ? "long unsigned int" : "long long unsigned int")
#define UINT64_TYPE (INT_TYPE_SIZE == 16 ? "long long unsigned int" : 0)
#define INT_LEAST8_TYPE INT8_TYPE
#define INT_LEAST16_TYPE INT16_TYPE
#define INT_LEAST32_TYPE INT32_TYPE
#define INT_LEAST64_TYPE INT64_TYPE
#define UINT_LEAST8_TYPE UINT8_TYPE
#define UINT_LEAST16_TYPE UINT16_TYPE
#define UINT_LEAST32_TYPE UINT32_TYPE
#define UINT_LEAST64_TYPE UINT64_TYPE
#define INT_FAST8_TYPE INT8_TYPE
#define INT_FAST16_TYPE (INT_TYPE_SIZE == 16 ? "int" : INT16_TYPE)
#define INT_FAST32_TYPE INT32_TYPE
#define INT_FAST64_TYPE INT64_TYPE
#define UINT_FAST8_TYPE UINT8_TYPE
#define UINT_FAST16_TYPE (INT_TYPE_SIZE == 16 ? "unsigned int" : UINT16_TYPE)
#define UINT_FAST32_TYPE UINT32_TYPE
#define UINT_FAST64_TYPE UINT64_TYPE
#define INTPTR_TYPE PTRDIFF_TYPE
#ifndef UINTPTR_TYPE
#define UINTPTR_TYPE SIZE_TYPE
#endif

67
external/gpl3/gcc/dist/gcc/config/avr/avr.c vendored
View File

@ -1043,8 +1043,7 @@ avr_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
true_regnum (XEXP (x, 0)));
debug_rtx (x);
}
if (!strict && GET_CODE (x) == SUBREG)
x = SUBREG_REG (x);
if (REG_P (x) && (strict ? REG_OK_FOR_BASE_STRICT_P (x)
: REG_OK_FOR_BASE_NOSTRICT_P (x)))
r = POINTER_REGS;
@ -1386,9 +1385,8 @@ notice_update_cc (rtx body ATTRIBUTE_UNUSED, rtx insn)
{
rtx x = XEXP (src, 1);
if (GET_CODE (x) == CONST_INT
&& INTVAL (x) > 0
&& INTVAL (x) != 6)
if (CONST_INT_P (x)
&& IN_RANGE (INTVAL (x), 1, 5))
{
cc_status.value1 = SET_DEST (set);
cc_status.flags |= CC_OVERFLOW_UNUSABLE;
@ -5934,26 +5932,30 @@ jump_over_one_insn_p (rtx insn, rtx dest)
int
avr_hard_regno_mode_ok (int regno, enum machine_mode mode)
{
/* Disallow QImode in stack pointer regs. */
if ((regno == REG_SP || regno == (REG_SP + 1)) && mode == QImode)
return 0;
/* The only thing that can go into registers r28:r29 is a Pmode. */
if (regno == REG_Y && mode == Pmode)
/* NOTE: 8-bit values must not be disallowed for R28 or R29.
Disallowing QI et al. in these regs might lead to code like
(set (subreg:QI (reg:HI 28) n) ...)
which will result in wrong code because reload does not
handle SUBREGs of hard regsisters like this, see PR46779.
This could be fixed in reload. However, it appears
that fixing reload is not wanted by reload people. */
/* Any GENERAL_REGS register can hold 8-bit values. */
if (GET_MODE_SIZE (mode) == 1)
return 1;
/* Otherwise disallow all regno/mode combinations that span r28:r29. */
if (regno <= (REG_Y + 1) && (regno + GET_MODE_SIZE (mode)) >= (REG_Y + 1))
/* FIXME: Ideally, the following test is not needed.
However, it turned out that it can reduce the number
of spill fails. AVR and it's poor endowment with
address registers is extreme stress test for reload. */
if (GET_MODE_SIZE (mode) >= 4
&& regno >= REG_X)
return 0;
if (mode == QImode)
return 1;
/* Modes larger than QImode occupy consecutive registers. */
if (regno + GET_MODE_SIZE (mode) > FIRST_PSEUDO_REGISTER)
return 0;
/* All modes larger than QImode should start in an even register. */
/* All modes larger than 8 bits should start in an even register. */
return !(regno & 1);
}
@ -6080,13 +6082,23 @@ avr_hard_regno_scratch_ok (unsigned int regno)
&& !df_regs_ever_live_p (regno))
return false;
/* Don't allow hard registers that might be part of the frame pointer.
Some places in the compiler just test for [HARD_]FRAME_POINTER_REGNUM
and don't care for a frame pointer that spans more than one register. */
if ((!reload_completed || frame_pointer_needed)
&& (regno == REG_Y || regno == REG_Y + 1))
{
return false;
}
return true;
}
/* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
int
avr_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
avr_hard_regno_rename_ok (unsigned int old_reg,
unsigned int new_reg)
{
/* Interrupt functions can only use registers that have already been
@ -6097,6 +6109,17 @@ avr_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
&& !df_regs_ever_live_p (new_reg))
return 0;
/* Don't allow hard registers that might be part of the frame pointer.
Some places in the compiler just test for [HARD_]FRAME_POINTER_REGNUM
and don't care for a frame pointer that spans more than one register. */
if ((!reload_completed || frame_pointer_needed)
&& (old_reg == REG_Y || old_reg == REG_Y + 1
|| new_reg == REG_Y || new_reg == REG_Y + 1))
{
return 0;
}
return 1;
}

27
external/gpl3/gcc/dist/gcc/config/avr/libgcc.S vendored
View File

@ -28,6 +28,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#define __SP_H__ 0x3e
#define __SP_L__ 0x3d
#define __RAMPZ__ 0x3B
#define __EIND__ 0x3C
/* Most of the functions here are called directly from avr.md
patterns, instead of using the standard libcall mechanisms.
@ -689,7 +690,8 @@ __tablejump__:
lpm
push r0
#if defined (__AVR_HAVE_EIJMP_EICALL__)
push __zero_reg__
in __tmp_reg__, __EIND__
push __tmp_reg__
#endif
ret
#endif
@ -791,22 +793,22 @@ __do_clear_bss:
#if defined(__AVR_HAVE_RAMPZ__)
__do_global_ctors:
ldi r17, hi8(__ctors_start)
ldi r16, hh8(__ctors_start)
ldi r28, lo8(__ctors_end)
ldi r29, hi8(__ctors_end)
ldi r20, hh8(__ctors_end)
ldi r16, hh8(__ctors_end)
rjmp .L__do_global_ctors_start
.L__do_global_ctors_loop:
sbiw r28, 2
sbc r20, __zero_reg__
sbc r16, __zero_reg__
mov_h r31, r29
mov_l r30, r28
out __RAMPZ__, r20
out __RAMPZ__, r16
XCALL __tablejump_elpm__
.L__do_global_ctors_start:
cpi r28, lo8(__ctors_start)
cpc r29, r17
cpc r20, r16
ldi r24, hh8(__ctors_start)
cpc r16, r24
brne .L__do_global_ctors_loop
#else
__do_global_ctors:
@ -832,22 +834,22 @@ __do_global_ctors:
#if defined(__AVR_HAVE_RAMPZ__)
__do_global_dtors:
ldi r17, hi8(__dtors_end)
ldi r16, hh8(__dtors_end)
ldi r28, lo8(__dtors_start)
ldi r29, hi8(__dtors_start)
ldi r20, hh8(__dtors_start)
ldi r16, hh8(__dtors_start)
rjmp .L__do_global_dtors_start
.L__do_global_dtors_loop:
sbiw r28, 2
sbc r20, __zero_reg__
sbc r16, __zero_reg__
mov_h r31, r29
mov_l r30, r28
out __RAMPZ__, r20
out __RAMPZ__, r16
XCALL __tablejump_elpm__
.L__do_global_dtors_start:
cpi r28, lo8(__dtors_end)
cpc r29, r17
cpc r20, r16
ldi r24, hh8(__dtors_end)
cpc r16, r24
brne .L__do_global_dtors_loop
#else
__do_global_dtors:
@ -889,7 +891,8 @@ __tablejump_elpm__:
elpm
push r0
#if defined (__AVR_HAVE_EIJMP_EICALL__)
push __zero_reg__
in __tmp_reg__, __EIND__
push __tmp_reg__
#endif
ret
#endif

6
external/gpl3/gcc/dist/gcc/config/bfin/linux-unwind.h vendored
View File

@ -1,5 +1,5 @@
/* DWARF2 EH unwinding support for Blackfin.
Copyright (C) 2007, 2009 Free Software Foundation, Inc.
Copyright (C) 2007, 2009, 2012 Free Software Foundation, Inc.
This file is part of GCC.
@ -48,10 +48,10 @@ bfin_fallback_frame_state (struct _Unwind_Context *context,
{
struct rt_sigframe {
int sig;
struct siginfo *pinfo;
siginfo_t *pinfo;
void *puc;
char retcode[8];
struct siginfo info;
siginfo_t info;
struct ucontext uc;
} *rt_ = context->cfa;

1
external/gpl3/gcc/dist/gcc/config/darwin-protos.h vendored
View File

@ -93,3 +93,4 @@ extern void darwin_asm_output_anchor (rtx symbol);
extern bool darwin_kextabi_p (void);
extern void darwin_override_options (void);
extern void darwin_patch_builtins (void);
extern void darwin_rename_builtins (void);

28
external/gpl3/gcc/dist/gcc/config/darwin.c vendored
View File

@ -337,6 +337,34 @@ static GTY ((param_is (struct machopic_indirection))) htab_t
/* Return a hash value for a SLOT in the indirections hash table. */
void
darwin_rename_builtins (void)
{
/* The system ___divdc3 routine in libSystem on darwin10 is not
accurate to 1ulp, ours is, so we avoid ever using the system name
for this routine and instead install a non-conflicting name that
is accurate.
When -ffast-math or -funsafe-math-optimizations is given, we can
use the faster version. */
if (!flag_unsafe_math_optimizations)
{
int dcode = (BUILT_IN_COMPLEX_DIV_MIN
+ DCmode - MIN_MODE_COMPLEX_FLOAT);
tree fn = built_in_decls[dcode];
/* Fortran and c call TARGET_INIT_BUILTINS and
TARGET_INIT_LIBFUNCS at different times, so we have to put a
call into each to ensure that at least one of them is called
after build_common_builtin_nodes. A better fix is to add a
new hook to run after build_common_builtin_nodes runs. */
if (fn)
set_user_assembler_name (fn, "___ieee_divdc3");
fn = implicit_built_in_decls[dcode];
if (fn)
set_user_assembler_name (fn, "___ieee_divdc3");
}
}
static hashval_t
machopic_indirection_hash (const void *slot)
{

2
external/gpl3/gcc/dist/gcc/config/i386/athlon.md vendored
View File

@ -798,7 +798,7 @@
"athlon-direct,athlon-fploadk8,athlon-fadd")
(define_insn_reservation "athlon_ssecomi" 4
(and (eq_attr "cpu" "athlon,k8,generic64")
(eq_attr "type" "ssecmp"))
(eq_attr "type" "ssecomi"))
"athlon-vector,athlon-fpsched,athlon-fadd")
(define_insn_reservation "athlon_ssecomi_amdfam10" 3
(and (eq_attr "cpu" "amdfam10")

2
external/gpl3/gcc/dist/gcc/config/i386/avxintrin.h vendored
View File

@ -759,7 +759,7 @@ _mm256_insert_epi8 (__m256i __X, int __D, int const __N)
#ifdef __x86_64__
extern __inline __m256i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm256_insert_epi64 (__m256i __X, int __D, int const __N)
_mm256_insert_epi64 (__m256i __X, long long __D, int const __N)
{
__m128i __Y = _mm256_extractf128_si256 (__X, __N >> 1);
__Y = _mm_insert_epi64 (__Y, __D, __N % 2);

2
external/gpl3/gcc/dist/gcc/config/i386/constraints.md vendored
View File

@ -149,7 +149,7 @@
(define_constraint "G"
"Standard 80387 floating point constant."
(and (match_code "const_double")
(match_test "standard_80387_constant_p (op)")))
(match_test "standard_80387_constant_p (op) > 0")))
;; This can theoretically be any mode's CONST0_RTX.
(define_constraint "C"

14
external/gpl3/gcc/dist/gcc/config/i386/darwin.h vendored
View File

@ -302,3 +302,17 @@ along with GCC; see the file COPYING3. If not see
#define MACHO_SYMBOL_FLAG_VARIABLE ((SYMBOL_FLAG_MACH_DEP) << 3)
#define SUBTARGET32_DEFAULT_CPU "i686"
#define SUBTARGET_INIT_BUILTINS \
do { \
darwin_rename_builtins (); \
} while(0)
/* The system ___divdc3 routine in libSystem on darwin10 is not
accurate to 1ulp, ours is, so we avoid ever using the system name
for this routine and instead install a non-conflicting name that is
accurate. See darwin_rename_builtins. */
#ifdef L_divdc3
#define DECLARE_LIBRARY_RENAMES \
asm(".text; ___divdc3: jmp ___ieee_divdc3 ; .globl ___divdc3");
#endif

2
external/gpl3/gcc/dist/gcc/config/i386/driver-i386.c vendored
View File

@ -494,7 +494,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
processor = PROCESSOR_AMDFAM10;
else if (has_sse2 || has_longmode)
processor = PROCESSOR_K8;
else if (has_3dnowp)
else if (has_3dnowp && family == 6)
processor = PROCESSOR_ATHLON;
else if (has_mmx)
processor = PROCESSOR_K6;

3
external/gpl3/gcc/dist/gcc/config/i386/i386-protos.h vendored
View File

@ -57,7 +57,8 @@ extern bool legitimate_constant_p (rtx);
extern bool constant_address_p (rtx);
extern bool legitimate_pic_operand_p (rtx);
extern int legitimate_pic_address_disp_p (rtx);
extern bool ix86_legitimize_reload_address (rtx, enum machine_mode,
int, int, int);
extern void print_reg (rtx, int, FILE*);
extern void print_operand (FILE*, rtx, int);
extern void print_operand_address (FILE*, rtx);

19
external/gpl3/gcc/dist/gcc/config/i386/i386.h vendored
View File

@ -397,7 +397,7 @@ extern unsigned char ix86_tune_features[X86_TUNE_LAST];
/* Feature tests against the various architecture variations. */
enum ix86_arch_indices {
X86_ARCH_CMOVE, /* || TARGET_SSE */
X86_ARCH_CMOV,
X86_ARCH_CMPXCHG,
X86_ARCH_CMPXCHG8B,
X86_ARCH_XADD,
@ -408,12 +408,16 @@ enum ix86_arch_indices {
extern unsigned char ix86_arch_features[X86_ARCH_LAST];
#define TARGET_CMOVE ix86_arch_features[X86_ARCH_CMOVE]
#define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV]
#define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
#define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
#define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
#define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
/* For sane SSE instruction set generation we need fcomi instruction.
It is safe to enable all CMOVE instructions. */
#define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE)
#define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
extern int x86_prefetch_sse;
@ -1766,6 +1770,17 @@ typedef struct ix86_args {
#define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
/* Try a machine-dependent way of reloading an illegitimate address
operand. If we find one, push the reload and jump to WIN. This
macro is used in only one place: `find_reloads_address' in reload.c. */
#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, INDL, WIN) \
do { \
if (ix86_legitimize_reload_address ((X), (MODE), (OPNUM), \
(int)(TYPE), (INDL))) \
goto WIN; \
} while (0)
/* If defined, a C expression to determine the base term of address X.
This macro is used in only one place: `find_base_term' in alias.c.

203
external/gpl3/gcc/dist/gcc/config/i386/i386.md vendored
View File

@ -2430,7 +2430,7 @@
[(set_attr "type" "*,*,mmx,mmxmov,mmxmov,sselog1,ssemov,ssemov,ssemov,sselog1,ssemov,ssemov,ssemov")
(set (attr "prefix")
(if_then_else (eq_attr "alternative" "5,6,7,8")
(const_string "vex")
(const_string "maybe_vex")
(const_string "orig")))
(set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,TI,DI,V4SF,V2SF,V4SF,V2SF")])
@ -2468,21 +2468,15 @@
return "movdq2q\t{%1, %0|%0, %1}";
case TYPE_SSEMOV:
if (TARGET_AVX)
{
if (get_attr_mode (insn) == MODE_TI)
return "vmovdqa\t{%1, %0|%0, %1}";
else
return "vmovq\t{%1, %0|%0, %1}";
}
if (get_attr_mode (insn) == MODE_TI)
return "movdqa\t{%1, %0|%0, %1}";
/* FALLTHRU */
return "%vmovdqa\t{%1, %0|%0, %1}";
/* Handle broken assemblers that require movd instead of movq. */
if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
return "%vmovd\t{%1, %0|%0, %1}";
return "%vmovq\t{%1, %0|%0, %1}";
case TYPE_MMXMOV:
/* Moves from and into integer register is done using movd
opcode with REX prefix. */
/* Handle broken assemblers that require movd instead of movq. */
if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
return "movd\t{%1, %0|%0, %1}";
return "movq\t{%1, %0|%0, %1}";
@ -2878,7 +2872,7 @@
&& (reload_in_progress || reload_completed
|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
|| (!TARGET_SSE_MATH && optimize_function_for_size_p (cfun)
&& standard_80387_constant_p (operands[1]))
&& standard_80387_constant_p (operands[1]) > 0)
|| GET_CODE (operands[1]) != CONST_DOUBLE
|| memory_operand (operands[0], SFmode))"
{
@ -2915,12 +2909,13 @@
case 9: case 10: case 14: case 15:
return "movd\t{%1, %0|%0, %1}";
case 12: case 13:
return "%vmovd\t{%1, %0|%0, %1}";
case 11:
return "movq\t{%1, %0|%0, %1}";
case 12: case 13:
return "%vmovd\t{%1, %0|%0, %1}";
default:
gcc_unreachable ();
}
@ -3048,11 +3043,10 @@
|| (!(TARGET_SSE2 && TARGET_SSE_MATH)
&& optimize_function_for_size_p (cfun)
&& !memory_operand (operands[0], DFmode)
&& standard_80387_constant_p (operands[1]))
&& standard_80387_constant_p (operands[1]) > 0)
|| GET_CODE (operands[1]) != CONST_DOUBLE
|| ((optimize_function_for_size_p (cfun)
|| !TARGET_MEMORY_MISMATCH_STALL
|| reload_in_progress || reload_completed)
|| !TARGET_MEMORY_MISMATCH_STALL)
&& memory_operand (operands[0], DFmode)))"
{
switch (which_alternative)
@ -3067,6 +3061,7 @@
case 3:
case 4:
return "#";
case 5:
switch (get_attr_mode (insn))
{
@ -3200,7 +3195,7 @@
|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
|| (!(TARGET_SSE2 && TARGET_SSE_MATH)
&& optimize_function_for_size_p (cfun)
&& standard_80387_constant_p (operands[1]))
&& standard_80387_constant_p (operands[1]) > 0)
|| GET_CODE (operands[1]) != CONST_DOUBLE
|| memory_operand (operands[0], DFmode))"
{
@ -3262,7 +3257,8 @@
case 9:
case 10:
return "%vmovd\t{%1, %0|%0, %1}";
/* Handle broken assemblers that require movd instead of movq. */
return "%vmovd\t{%1, %0|%0, %1}";
default:
gcc_unreachable();
@ -3340,7 +3336,7 @@
|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
|| (!(TARGET_SSE2 && TARGET_SSE_MATH)
&& optimize_function_for_size_p (cfun)
&& standard_80387_constant_p (operands[1]))
&& standard_80387_constant_p (operands[1]) > 0)
|| GET_CODE (operands[1]) != CONST_DOUBLE
|| memory_operand (operands[0], DFmode))"
{
@ -3361,11 +3357,11 @@
switch (get_attr_mode (insn))
{
case MODE_V4SF:
return "xorps\t%0, %0";
return "%vxorps\t%0, %d0";
case MODE_V2DF:
return "xorpd\t%0, %0";
return "%vxorpd\t%0, %d0";
case MODE_TI:
return "pxor\t%0, %0";
return "%vpxor\t%0, %d0";
default:
gcc_unreachable ();
}
@ -3375,28 +3371,56 @@
switch (get_attr_mode (insn))
{
case MODE_V4SF:
return "movaps\t{%1, %0|%0, %1}";
return "%vmovaps\t{%1, %0|%0, %1}";
case MODE_V2DF:
return "movapd\t{%1, %0|%0, %1}";
return "%vmovapd\t{%1, %0|%0, %1}";
case MODE_TI:
return "movdqa\t{%1, %0|%0, %1}";
return "%vmovdqa\t{%1, %0|%0, %1}";
case MODE_DI:
return "movq\t{%1, %0|%0, %1}";
return "%vmovq\t{%1, %0|%0, %1}";
case MODE_DF:
return "movsd\t{%1, %0|%0, %1}";
if (TARGET_AVX)
{
if (REG_P (operands[0]) && REG_P (operands[1]))
return "vmovsd\t{%1, %0, %0|%0, %0, %1}";
else
return "vmovsd\t{%1, %0|%0, %1}";
}
else
return "movsd\t{%1, %0|%0, %1}";
case MODE_V1DF:
return "movlpd\t{%1, %0|%0, %1}";
if (TARGET_AVX)
{
if (REG_P (operands[0]))
return "vmovlpd\t{%1, %0, %0|%0, %0, %1}";
else
return "vmovlpd\t{%1, %0|%0, %1}";
}
else
return "movlpd\t{%1, %0|%0, %1}";
case MODE_V2SF:
return "movlps\t{%1, %0|%0, %1}";
if (TARGET_AVX)
{
if (REG_P (operands[0]))
return "vmovlps\t{%1, %0, %0|%0, %0, %1}";
else
return "vmovlps\t{%1, %0|%0, %1}";
}
else
return "movlps\t{%1, %0|%0, %1}";
default:
gcc_unreachable ();
}
default:
gcc_unreachable();
gcc_unreachable ();
}
}
[(set_attr "type" "fmov,fmov,fmov,multi,multi,sselog1,ssemov,ssemov,ssemov")
(set (attr "prefix")
(if_then_else (eq_attr "alternative" "0,1,2,3,4")
(const_string "orig")
(const_string "maybe_vex")))
(set (attr "prefix_data16")
(if_then_else (eq_attr "mode" "V1DF")
(const_string "1")
@ -3543,7 +3567,8 @@
"optimize_function_for_size_p (cfun)
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))
&& (reload_in_progress || reload_completed
|| standard_80387_constant_p (operands[1])
|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
|| standard_80387_constant_p (operands[1]) > 0
|| GET_CODE (operands[1]) != CONST_DOUBLE
|| memory_operand (operands[0], XFmode))"
{
@ -3571,6 +3596,7 @@
"optimize_function_for_speed_p (cfun)
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))
&& (reload_in_progress || reload_completed
|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
|| GET_CODE (operands[1]) != CONST_DOUBLE
|| memory_operand (operands[0], XFmode))"
{
@ -3715,7 +3741,7 @@
}
else if (FP_REG_P (r))
{
if (!standard_80387_constant_p (c))
if (standard_80387_constant_p (c) < 1)
FAIL;
}
else if (MMX_REG_P (r))
@ -3747,7 +3773,7 @@
}
else if (FP_REG_P (r))
{
if (!standard_80387_constant_p (c))
if (standard_80387_constant_p (c) < 1)
FAIL;
}
else if (MMX_REG_P (r))
@ -17658,7 +17684,8 @@
(set (match_operand:DI 1 "register_operand" "=S")
(plus:DI (match_dup 3)
(const_int 8)))]
"TARGET_64BIT"
"TARGET_64BIT
&& !(fixed_regs[SI_REG] || fixed_regs[DI_REG])"
"movsq"
[(set_attr "type" "str")
(set_attr "mode" "DI")
@ -17673,7 +17700,8 @@
(set (match_operand:SI 1 "register_operand" "=S")
(plus:SI (match_dup 3)
(const_int 4)))]
"!TARGET_64BIT"
"!TARGET_64BIT
&& !(fixed_regs[SI_REG] || fixed_regs[DI_REG])"
"movs{l|d}"
[(set_attr "type" "str")
(set_attr "mode" "SI")
@ -17688,7 +17716,8 @@
(set (match_operand:DI 1 "register_operand" "=S")
(plus:DI (match_dup 3)
(const_int 4)))]
"TARGET_64BIT"
"TARGET_64BIT
&& !(fixed_regs[SI_REG] || fixed_regs[DI_REG])"
"movs{l|d}"
[(set_attr "type" "str")
(set_attr "mode" "SI")
@ -17703,7 +17732,8 @@
(set (match_operand:SI 1 "register_operand" "=S")
(plus:SI (match_dup 3)
(const_int 2)))]
"!TARGET_64BIT"
"!TARGET_64BIT
&& !(fixed_regs[SI_REG] || fixed_regs[DI_REG])"
"movsw"
[(set_attr "type" "str")
(set_attr "memory" "both")
@ -17718,7 +17748,8 @@
(set (match_operand:DI 1 "register_operand" "=S")
(plus:DI (match_dup 3)
(const_int 2)))]
"TARGET_64BIT"
"TARGET_64BIT
&& !(fixed_regs[SI_REG] || fixed_regs[DI_REG])"
"movsw"
[(set_attr "type" "str")
(set_attr "memory" "both")
@ -17733,7 +17764,8 @@
(set (match_operand:SI 1 "register_operand" "=S")
(plus:SI (match_dup 3)
(const_int 1)))]
"!TARGET_64BIT"
"!TARGET_64BIT
&& !(fixed_regs[SI_REG] || fixed_regs[DI_REG])"
"movsb"
[(set_attr "type" "str")
(set_attr "memory" "both")
@ -17748,7 +17780,8 @@
(set (match_operand:DI 1 "register_operand" "=S")
(plus:DI (match_dup 3)
(const_int 1)))]
"TARGET_64BIT"
"TARGET_64BIT
&& !(fixed_regs[SI_REG] || fixed_regs[DI_REG])"
"movsb"
[(set_attr "type" "str")
(set_attr "memory" "both")
@ -17779,7 +17812,8 @@
(set (mem:BLK (match_dup 3))
(mem:BLK (match_dup 4)))
(use (match_dup 5))]
"TARGET_64BIT"
"TARGET_64BIT
&& !(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])"
"rep{%;} movsq"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
@ -17798,7 +17832,8 @@
(set (mem:BLK (match_dup 3))
(mem:BLK (match_dup 4)))
(use (match_dup 5))]
"!TARGET_64BIT"
"!TARGET_64BIT
&& !(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])"
"rep{%;} movs{l|d}"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
@ -17817,7 +17852,8 @@
(set (mem:BLK (match_dup 3))
(mem:BLK (match_dup 4)))
(use (match_dup 5))]
"TARGET_64BIT"
"TARGET_64BIT
&& !(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])"
"rep{%;} movs{l|d}"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
@ -17834,7 +17870,8 @@
(set (mem:BLK (match_dup 3))
(mem:BLK (match_dup 4)))
(use (match_dup 5))]
"!TARGET_64BIT"
"!TARGET_64BIT
&& !(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])"
"rep{%;} movsb"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
@ -17851,7 +17888,8 @@
(set (mem:BLK (match_dup 3))
(mem:BLK (match_dup 4)))
(use (match_dup 5))]
"TARGET_64BIT"
"TARGET_64BIT
&& !(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])"
"rep{%;} movsb"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
@ -17911,7 +17949,9 @@
operands[3] = gen_rtx_PLUS (Pmode, operands[0],
GEN_INT (GET_MODE_SIZE (GET_MODE
(operands[2]))));
if (TARGET_SINGLE_STRINGOP || optimize_insn_for_size_p ())
/* Can't use this if the user has appropriated eax or edi. */
if ((TARGET_SINGLE_STRINGOP || optimize_insn_for_size_p ())
&& !(fixed_regs[AX_REG] || fixed_regs[DI_REG]))
{
emit_insn (gen_strset_singleop (operands[0], operands[1], operands[2],
operands[3]));
@ -17933,7 +17973,8 @@
(set (match_operand:DI 0 "register_operand" "=D")
(plus:DI (match_dup 1)
(const_int 8)))]
"TARGET_64BIT"
"TARGET_64BIT
&& !(fixed_regs[AX_REG] || fixed_regs[DI_REG])"
"stosq"
[(set_attr "type" "str")
(set_attr "memory" "store")
@ -17945,7 +17986,8 @@
(set (match_operand:SI 0 "register_operand" "=D")
(plus:SI (match_dup 1)
(const_int 4)))]
"!TARGET_64BIT"
"!TARGET_64BIT
&& !(fixed_regs[AX_REG] || fixed_regs[DI_REG])"
"stos{l|d}"
[(set_attr "type" "str")
(set_attr "memory" "store")
@ -17957,7 +17999,8 @@
(set (match_operand:DI 0 "register_operand" "=D")
(plus:DI (match_dup 1)
(const_int 4)))]
"TARGET_64BIT"
"TARGET_64BIT
&& !(fixed_regs[AX_REG] || fixed_regs[DI_REG])"
"stos{l|d}"
[(set_attr "type" "str")
(set_attr "memory" "store")
@ -17969,7 +18012,8 @@
(set (match_operand:SI 0 "register_operand" "=D")
(plus:SI (match_dup 1)
(const_int 2)))]
"!TARGET_64BIT"
"!TARGET_64BIT
&& !(fixed_regs[AX_REG] || fixed_regs[DI_REG])"
"stosw"
[(set_attr "type" "str")
(set_attr "memory" "store")
@ -17981,7 +18025,8 @@
(set (match_operand:DI 0 "register_operand" "=D")
(plus:DI (match_dup 1)
(const_int 2)))]
"TARGET_64BIT"
"TARGET_64BIT
&& !(fixed_regs[AX_REG] || fixed_regs[DI_REG])"
"stosw"
[(set_attr "type" "str")
(set_attr "memory" "store")
@ -17993,7 +18038,8 @@
(set (match_operand:SI 0 "register_operand" "=D")
(plus:SI (match_dup 1)
(const_int 1)))]
"!TARGET_64BIT"
"!TARGET_64BIT
&& !(fixed_regs[AX_REG] || fixed_regs[DI_REG])"
"stosb"
[(set_attr "type" "str")
(set_attr "memory" "store")
@ -18005,7 +18051,8 @@
(set (match_operand:DI 0 "register_operand" "=D")
(plus:DI (match_dup 1)
(const_int 1)))]
"TARGET_64BIT"
"TARGET_64BIT
&& !(fixed_regs[AX_REG] || fixed_regs[DI_REG])"
"stosb"
[(set_attr "type" "str")
(set_attr "memory" "store")
@ -18032,7 +18079,8 @@
(const_int 0))
(use (match_operand:DI 2 "register_operand" "a"))
(use (match_dup 4))]
"TARGET_64BIT"
"TARGET_64BIT
&& !(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])"
"rep{%;} stosq"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
@ -18049,7 +18097,8 @@
(const_int 0))
(use (match_operand:SI 2 "register_operand" "a"))
(use (match_dup 4))]
"!TARGET_64BIT"
"!TARGET_64BIT
&& !(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])"
"rep{%;} stos{l|d}"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
@ -18066,7 +18115,8 @@
(const_int 0))
(use (match_operand:SI 2 "register_operand" "a"))
(use (match_dup 4))]
"TARGET_64BIT"
"TARGET_64BIT
&& !(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])"
"rep{%;} stos{l|d}"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
@ -18082,7 +18132,8 @@
(const_int 0))
(use (match_operand:QI 2 "register_operand" "a"))
(use (match_dup 4))]
"!TARGET_64BIT"
"!TARGET_64BIT
&& !(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])"
"rep{%;} stosb"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
@ -18098,7 +18149,8 @@
(const_int 0))
(use (match_operand:QI 2 "register_operand" "a"))
(use (match_dup 4))]
"TARGET_64BIT"
"TARGET_64BIT
&& !(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])"
"rep{%;} stosb"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
@ -18119,8 +18171,8 @@
if (optimize_insn_for_size_p () && !TARGET_INLINE_ALL_STRINGOPS)
FAIL;
/* Can't use this if the user has appropriated esi or edi. */
if (fixed_regs[SI_REG] || fixed_regs[DI_REG])
/* Can't use this if the user has appropriated ecx, esi or edi. */
if (fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])
FAIL;
out = operands[0];
@ -18214,7 +18266,8 @@
(clobber (match_operand:SI 0 "register_operand" "=S"))
(clobber (match_operand:SI 1 "register_operand" "=D"))
(clobber (match_operand:SI 2 "register_operand" "=c"))]
"!TARGET_64BIT"
"!TARGET_64BIT
&& !(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])"
"repz{%;} cmpsb"
[(set_attr "type" "str")
(set_attr "mode" "QI")
@ -18229,7 +18282,8 @@
(clobber (match_operand:DI 0 "register_operand" "=S"))
(clobber (match_operand:DI 1 "register_operand" "=D"))
(clobber (match_operand:DI 2 "register_operand" "=c"))]
"TARGET_64BIT"
"TARGET_64BIT
&& !(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])"
"repz{%;} cmpsb"
[(set_attr "type" "str")
(set_attr "mode" "QI")
@ -18265,7 +18319,8 @@
(clobber (match_operand:SI 0 "register_operand" "=S"))
(clobber (match_operand:SI 1 "register_operand" "=D"))
(clobber (match_operand:SI 2 "register_operand" "=c"))]
"!TARGET_64BIT"
"!TARGET_64BIT
&& !(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])"
"repz{%;} cmpsb"
[(set_attr "type" "str")
(set_attr "mode" "QI")
@ -18283,7 +18338,8 @@
(clobber (match_operand:DI 0 "register_operand" "=S"))
(clobber (match_operand:DI 1 "register_operand" "=D"))
(clobber (match_operand:DI 2 "register_operand" "=c"))]
"TARGET_64BIT"
"TARGET_64BIT
&& !(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])"
"repz{%;} cmpsb"
[(set_attr "type" "str")
(set_attr "mode" "QI")
@ -18295,7 +18351,7 @@
(unspec:SI [(match_operand:BLK 1 "general_operand" "")
(match_operand:QI 2 "immediate_operand" "")
(match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
""
"!TARGET_64BIT"
{
if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
DONE;
@ -18308,7 +18364,7 @@
(unspec:DI [(match_operand:BLK 1 "general_operand" "")
(match_operand:QI 2 "immediate_operand" "")
(match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
""
"TARGET_64BIT"
{
if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
DONE;
@ -18331,7 +18387,8 @@
(match_operand:SI 4 "register_operand" "0")] UNSPEC_SCAS))
(clobber (match_operand:SI 1 "register_operand" "=D"))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT"
"!TARGET_64BIT
&& !(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])"
"repnz{%;} scasb"
[(set_attr "type" "str")
(set_attr "mode" "QI")
@ -18345,7 +18402,8 @@
(match_operand:DI 4 "register_operand" "0")] UNSPEC_SCAS))
(clobber (match_operand:DI 1 "register_operand" "=D"))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"TARGET_64BIT
&& !(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])"
"repnz{%;} scasb"
[(set_attr "type" "str")
(set_attr "mode" "QI")
@ -18499,7 +18557,8 @@
(define_insn "*x86_mov<mode>cc_0_m1_neg"
[(set (match_operand:SWI48 0 "register_operand" "=r")
(neg:SWI48 (match_operator 1 "ix86_carry_flag_operator"
[(reg FLAGS_REG) (const_int 0)])))]
[(reg FLAGS_REG) (const_int 0)])))
(clobber (reg:CC FLAGS_REG))]
""
"sbb{<imodesuffix>}\t%0, %0"
[(set_attr "type" "alu")

6
external/gpl3/gcc/dist/gcc/config/i386/linux-unwind.h vendored
View File

@ -1,5 +1,5 @@
/* DWARF2 EH unwinding support for AMD x86-64 and x86.
Copyright (C) 2004, 2005, 2006, 2009 Free Software Foundation, Inc.
Copyright (C) 2004, 2005, 2006, 2009, 2012 Free Software Foundation, Inc.
This file is part of GCC.
@ -133,9 +133,9 @@ x86_fallback_frame_state (struct _Unwind_Context *context,
{
struct rt_sigframe {
int sig;
struct siginfo *pinfo;
siginfo_t *pinfo;
void *puc;
struct siginfo info;
siginfo_t info;
struct ucontext uc;
} *rt_ = context->cfa;
/* The void * cast is necessary to avoid an aliasing warning.

6
external/gpl3/gcc/dist/gcc/config/i386/mmx.md vendored
View File

@ -63,6 +63,7 @@
DONE;
})
;; movd instead of movq is required to handle broken assemblers.
(define_insn "*mov<mode>_internal_rex64"
[(set (match_operand:MMXMODEI8 0 "nonimmediate_operand"
"=rm,r,!?y,!?y ,m ,!y,*Y2,x,x ,m,r,Yi")
@ -81,8 +82,8 @@
%vpxor\t%0, %d0
%vmovq\t{%1, %0|%0, %1}
%vmovq\t{%1, %0|%0, %1}
%vmovq\t{%1, %0|%0, %1}
%vmovq\t{%1, %0|%0, %1}"
%vmovd\t{%1, %0|%0, %1}
%vmovd\t{%1, %0|%0, %1}"
[(set_attr "type" "imov,imov,mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,ssemov,ssemov")
(set_attr "unit" "*,*,*,*,*,mmx,mmx,*,*,*,*,*")
(set_attr "prefix_rep" "*,*,*,*,*,1,1,*,1,*,*,*")
@ -192,6 +193,7 @@
(const_string "orig")))
(set_attr "mode" "DI,DI,DI,DI,DI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
;; movd instead of movq is required to handle broken assemblers.
(define_insn "*movv2sf_internal_rex64"
[(set (match_operand:V2SF 0 "nonimmediate_operand"
"=rm,r ,!?y,!?y ,m ,!y,*Y2,x,x,x,m,r,Yi")

124
external/gpl3/gcc/dist/gcc/config/i386/sse.md vendored
View File

@ -354,18 +354,7 @@
DONE;
})
(define_expand "avx_movup<avxmodesuffixf2c><avxmodesuffix>"
[(set (match_operand:AVXMODEF2P 0 "nonimmediate_operand" "")
(unspec:AVXMODEF2P
[(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "")]
UNSPEC_MOVU))]
"AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
{
if (MEM_P (operands[0]) && MEM_P (operands[1]))
operands[1] = force_reg (<MODE>mode, operands[1]);
})
(define_insn "*avx_movup<avxmodesuffixf2c><avxmodesuffix>"
(define_insn "avx_movup<avxmodesuffixf2c><avxmodesuffix>"
[(set (match_operand:AVXMODEF2P 0 "nonimmediate_operand" "=x,m")
(unspec:AVXMODEF2P
[(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "xm,x")]
@ -391,18 +380,7 @@
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
(define_expand "<sse>_movup<ssemodesuffixf2c>"
[(set (match_operand:SSEMODEF2P 0 "nonimmediate_operand" "")
(unspec:SSEMODEF2P
[(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")]
UNSPEC_MOVU))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
{
if (MEM_P (operands[0]) && MEM_P (operands[1]))
operands[1] = force_reg (<MODE>mode, operands[1]);
})
(define_insn "*<sse>_movup<ssemodesuffixf2c>"
(define_insn "<sse>_movup<ssemodesuffixf2c>"
[(set (match_operand:SSEMODEF2P 0 "nonimmediate_operand" "=x,m")
(unspec:SSEMODEF2P
[(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm,x")]
@ -414,18 +392,7 @@
(set_attr "movu" "1")
(set_attr "mode" "<MODE>")])
(define_expand "avx_movdqu<avxmodesuffix>"
[(set (match_operand:AVXMODEQI 0 "nonimmediate_operand" "")
(unspec:AVXMODEQI
[(match_operand:AVXMODEQI 1 "nonimmediate_operand" "")]
UNSPEC_MOVU))]
"TARGET_AVX"
{
if (MEM_P (operands[0]) && MEM_P (operands[1]))
operands[1] = force_reg (<MODE>mode, operands[1]);
})
(define_insn "*avx_movdqu<avxmodesuffix>"
(define_insn "avx_movdqu<avxmodesuffix>"
[(set (match_operand:AVXMODEQI 0 "nonimmediate_operand" "=x,m")
(unspec:AVXMODEQI
[(match_operand:AVXMODEQI 1 "nonimmediate_operand" "xm,x")]
@ -437,17 +404,7 @@
(set_attr "prefix" "vex")
(set_attr "mode" "<avxvecmode>")])
(define_expand "sse2_movdqu"
[(set (match_operand:V16QI 0 "nonimmediate_operand" "")
(unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "")]
UNSPEC_MOVU))]
"TARGET_SSE2"
{
if (MEM_P (operands[0]) && MEM_P (operands[1]))
operands[1] = force_reg (V16QImode, operands[1]);
})
(define_insn "*sse2_movdqu"
(define_insn "sse2_movdqu"
[(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
(unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
UNSPEC_MOVU))]
@ -1267,15 +1224,15 @@
(match_operand:V4DF 1 "register_operand" "x")
(parallel [(const_int 0)]))
(vec_select:DF (match_dup 1) (parallel [(const_int 1)])))
(plusminus:DF
(vec_select:DF (match_dup 1) (parallel [(const_int 2)]))
(vec_select:DF (match_dup 1) (parallel [(const_int 3)]))))
(vec_concat:V2DF
(plusminus:DF
(vec_select:DF
(match_operand:V4DF 2 "nonimmediate_operand" "xm")
(parallel [(const_int 0)]))
(vec_select:DF (match_dup 2) (parallel [(const_int 1)])))
(vec_select:DF (match_dup 2) (parallel [(const_int 1)]))))
(vec_concat:V2DF
(plusminus:DF
(vec_select:DF (match_dup 1) (parallel [(const_int 2)]))
(vec_select:DF (match_dup 1) (parallel [(const_int 3)])))
(plusminus:DF
(vec_select:DF (match_dup 2) (parallel [(const_int 2)]))
(vec_select:DF (match_dup 2) (parallel [(const_int 3)]))))))]
@ -3904,7 +3861,7 @@
"TARGET_SSE"
{
if (!TARGET_AVX)
operands[1] = force_reg (V4SFmode, operands[1]);
operands[1] = force_reg (SFmode, operands[1]);
})
(define_insn "*vec_dupv4sf_avx"
@ -4551,15 +4508,14 @@
[(set (match_operand:V4DF 0 "register_operand" "=x,x")
(vec_select:V4DF
(vec_concat:V8DF
(match_operand:V4DF 1 "nonimmediate_operand" "xm,x")
(match_operand:V4DF 2 "nonimmediate_operand" " 1,xm"))
(match_operand:V4DF 1 "nonimmediate_operand" " x,m")
(match_operand:V4DF 2 "nonimmediate_operand" "xm,1"))
(parallel [(const_int 0) (const_int 4)
(const_int 2) (const_int 6)])))]
"TARGET_AVX
&& (!MEM_P (operands[1]) || rtx_equal_p (operands[1], operands[2]))"
"TARGET_AVX"
"@
vmovddup\t{%1, %0|%0, %1}
vunpcklpd\t{%2, %1, %0|%0, %1, %2}"
vunpcklpd\t{%2, %1, %0|%0, %1, %2}
vmovddup\t{%1, %0|%0, %1}"
[(set_attr "type" "sselog")
(set_attr "prefix" "vex")
(set_attr "mode" "V4DF")])
@ -4964,24 +4920,22 @@
;; Avoid combining registers from different units in a single alternative,
;; see comment above inline_secondary_memory_needed function in i386.c
(define_insn "sse2_loadhpd"
[(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,o,o,o")
[(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,o,o,o")
(vec_concat:V2DF
(vec_select:DF
(match_operand:V2DF 1 "nonimmediate_operand" " 0,0,x,0,0,0")
(match_operand:V2DF 1 "nonimmediate_operand" " 0,0,0,0,0")
(parallel [(const_int 0)]))
(match_operand:DF 2 "nonimmediate_operand" " m,x,0,x,*f,r")))]
(match_operand:DF 2 "nonimmediate_operand" " m,x,x,*f,r")))]
"TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
movhpd\t{%2, %0|%0, %2}
unpcklpd\t{%2, %0|%0, %2}
shufpd\t{$1, %1, %0|%0, %1, 1}
#
#
#"
[(set_attr "type" "ssemov,sselog,sselog,ssemov,fmov,imov")
(set_attr "prefix_data16" "1,*,*,*,*,*")
(set_attr "length_immediate" "*,*,1,*,*,*")
(set_attr "mode" "V1DF,V2DF,V2DF,DF,DF,DF")])
[(set_attr "type" "ssemov,sselog,ssemov,fmov,imov")
(set_attr "prefix_data16" "1,*,*,*,*")
(set_attr "mode" "V1DF,V2DF,DF,DF,DF")])
(define_split
[(set (match_operand:V2DF 0 "memory_operand" "")
@ -5137,6 +5091,16 @@
(set_attr "length_immediate" "*,*,*,1,*,*")
(set_attr "mode" "DF,V1DF,V1DF,V2DF,V1DF,V1DF")])
(define_expand "vec_dupv2df"
[(set (match_operand:V2DF 0 "register_operand" "")
(vec_duplicate:V2DF
(match_operand:DF 1 "nonimmediate_operand" "")))]
"TARGET_SSE2"
{
if (!TARGET_SSE3)
operands[1] = force_reg (DFmode, operands[1]);
})
(define_insn "*vec_dupv2df_sse3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
(vec_duplicate:V2DF
@ -5147,7 +5111,7 @@
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "DF")])
(define_insn "vec_dupv2df"
(define_insn "*vec_dupv2df"
[(set (match_operand:V2DF 0 "register_operand" "=x")
(vec_duplicate:V2DF
(match_operand:DF 1 "register_operand" "0")))]
@ -7473,9 +7437,8 @@
"@
#
#
%vmov{q}\t{%1, %0|%0, %1}"
mov{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "*,*,imov")
(set_attr "prefix" "*,*,maybe_vex")
(set_attr "mode" "*,*,DI")])
(define_insn "*sse2_storeq"
@ -7513,11 +7476,11 @@
vmovhps\t{%1, %0|%0, %1}
vpsrldq\t{$8, %1, %0|%0, %1, 8}
vmovq\t{%H1, %0|%0, %H1}
vmov{q}\t{%H1, %0|%0, %H1}"
mov{q}\t{%H1, %0|%0, %H1}"
[(set_attr "type" "ssemov,sseishft1,ssemov,imov")
(set_attr "length_immediate" "*,1,*,*")
(set_attr "memory" "*,none,*,*")
(set_attr "prefix" "vex")
(set_attr "prefix" "vex,vex,vex,orig")
(set_attr "mode" "V2SF,TI,TI,DI")])
(define_insn "*vec_extractv2di_1_rex64"
@ -7795,6 +7758,7 @@
(const_string "vex")))
(set_attr "mode" "TI,TI,TI,TI,TI,V2SF")])
;; movd instead of movq is required to handle broken assemblers.
(define_insn "*vec_concatv2di_rex64_sse4_1"
[(set (match_operand:V2DI 0 "register_operand" "=x ,x ,Yi,!x,x,x,x")
(vec_concat:V2DI
@ -7804,7 +7768,7 @@
"@
pinsrq\t{$0x1, %2, %0|%0, %2, 0x1}
movq\t{%1, %0|%0, %1}
movq\t{%1, %0|%0, %1}
movd\t{%1, %0|%0, %1}
movq2dq\t{%1, %0|%0, %1}
punpcklqdq\t{%2, %0|%0, %2}
movlhps\t{%2, %0|%0, %2}
@ -7815,6 +7779,7 @@
(set_attr "length_immediate" "1,*,*,*,*,*,*")
(set_attr "mode" "TI,TI,TI,TI,TI,V4SF,V2SF")])
;; movd instead of movq is required to handle broken assemblers.
(define_insn "*vec_concatv2di_rex64_sse"
[(set (match_operand:V2DI 0 "register_operand" "=Y2 ,Yi,!Y2,Y2,x,x")
(vec_concat:V2DI
@ -7823,7 +7788,7 @@
"TARGET_64BIT && TARGET_SSE"
"@
movq\t{%1, %0|%0, %1}
movq\t{%1, %0|%0, %1}
movd\t{%1, %0|%0, %1}
movq2dq\t{%1, %0|%0, %1}
punpcklqdq\t{%2, %0|%0, %2}
movlhps\t{%2, %0|%0, %2}
@ -10576,8 +10541,8 @@
[(set (match_operand:SSEMODE 0 "register_operand" "=x,x")
(if_then_else:SSEMODE
(match_operand:SSEMODE 3 "nonimmediate_operand" "x,m")
(match_operand:SSEMODE 1 "vector_move_operand" "x,x")
(match_operand:SSEMODE 2 "vector_move_operand" "xm,x")))]
(match_operand:SSEMODE 1 "register_operand" "x,x")
(match_operand:SSEMODE 2 "nonimmediate_operand" "xm,x")))]
"TARGET_XOP"
"vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "sse4arg")])
@ -10586,8 +10551,8 @@
[(set (match_operand:AVX256MODE 0 "register_operand" "=x,x")
(if_then_else:AVX256MODE
(match_operand:AVX256MODE 3 "nonimmediate_operand" "x,m")
(match_operand:AVX256MODE 1 "vector_move_operand" "x,x")
(match_operand:AVX256MODE 2 "vector_move_operand" "xm,x")))]
(match_operand:AVX256MODE 1 "register_operand" "x,x")
(match_operand:AVX256MODE 2 "nonimmediate_operand" "xm,x")))]
"TARGET_XOP"
"vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "sse4arg")])
@ -12136,8 +12101,7 @@
[(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
(unspec:AVXMODEF2P
[(match_operand:AVXMODEF2P 1 "memory_operand" "m")
(match_operand:<avxpermvecmode> 2 "register_operand" "x")
(match_dup 0)]
(match_operand:<avxpermvecmode> 2 "register_operand" "x")]
UNSPEC_MASKLOAD))]
"TARGET_AVX"
"vmaskmovp<avxmodesuffixf2c>\t{%1, %2, %0|%0, %2, %1}"

14
external/gpl3/gcc/dist/gcc/config/i386/winnt-cxx.c vendored
View File

@ -101,6 +101,20 @@ i386_pe_adjust_class_at_definition (tree t)
if (lookup_attribute ("dllexport", TYPE_ATTRIBUTES (t)) != NULL_TREE)
{
tree tmv = TYPE_MAIN_VARIANT (t);
/* Make sure that we set dllexport attribute to typeinfo's
base declaration, as otherwise it would fail to be exported as
it isn't a class-member. */
if (tmv != NULL_TREE
&& CLASSTYPE_TYPEINFO_VAR (tmv) != NULL_TREE)
{
tree na, ti_decl = CLASSTYPE_TYPEINFO_VAR (tmv);
na = tree_cons (get_identifier ("dllexport"), NULL_TREE,
NULL_TREE);
decl_attributes (&ti_decl, na, 0);
}
/* Check static VAR_DECL's. */
for (member = TYPE_FIELDS (t); member; member = TREE_CHAIN (member))
if (TREE_CODE (member) == VAR_DECL)

6
external/gpl3/gcc/dist/gcc/config/ia64/linux-unwind.h vendored
View File

@ -1,5 +1,5 @@
/* DWARF2 EH unwinding support for IA64 Linux.
Copyright (C) 2004, 2005, 2009 Free Software Foundation, Inc.
Copyright (C) 2004, 2005, 2009, 2012 Free Software Foundation, Inc.
This file is part of GCC.
@ -47,7 +47,7 @@ ia64_fallback_frame_state (struct _Unwind_Context *context,
struct sigframe {
char scratch[16];
unsigned long sig_number;
struct siginfo *info;
siginfo_t *info;
struct sigcontext *sc;
} *frame_ = (struct sigframe *)context->psp;
struct sigcontext *sc = frame_->sc;
@ -137,7 +137,7 @@ ia64_handle_unwabi (struct _Unwind_Context *context, _Unwind_FrameState *fs)
struct sigframe {
char scratch[16];
unsigned long sig_number;
struct siginfo *info;
siginfo_t *info;
struct sigcontext *sc;
} *frame = (struct sigframe *)context->psp;
struct sigcontext *sc = frame->sc;

2
external/gpl3/gcc/dist/gcc/config/lm32/t-lm32 vendored
View File

@ -1,2 +1,2 @@
# for multilib
MULTILIB_OPTIONS = mmultiply-enabled mbarrel-shift-enabled
MULTILIB_OPTIONS = mbarrel-shift-enabled mmultiply-enabled mdivide-enabled msign-extend-enabled

5
external/gpl3/gcc/dist/gcc/config/mips/linux-unwind.h vendored
View File

@ -1,5 +1,6 @@
/* DWARF2 EH unwinding support for MIPS Linux.
Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009, 2012 Free Software
Foundation, Inc.
This file is part of GCC.
@ -75,7 +76,7 @@ mips_fallback_frame_state (struct _Unwind_Context *context,
struct rt_sigframe {
u_int32_t ass[4]; /* Argument save space for o32. */
u_int32_t trampoline[2];
struct siginfo info;
siginfo_t info;
_sig_ucontext_t uc;
} *rt_ = context->cfa;
sc = &rt_->uc.uc_mcontext;

59
external/gpl3/gcc/dist/gcc/config/mips/mips.c vendored
View File

@ -1162,7 +1162,7 @@ static const struct mips_rtx_cost_data mips_rtx_cost_data[PROCESSOR_MAX] = {
}
};
static rtx mips_find_pic_call_symbol (rtx, rtx);
static rtx mips_find_pic_call_symbol (rtx, rtx, bool);
/* This hash table keeps track of implicit "mips16" and "nomips16" attributes
for -mflip_mips16. It maps decl names onto a boolean mode setting. */
@ -9007,6 +9007,11 @@ mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
static bool
mips_cfun_call_saved_reg_p (unsigned int regno)
{
/* If the user makes an ordinarily-call-saved register global,
that register is no longer call-saved. */
if (global_regs[regno])
return false;
/* Interrupt handlers need to save extra registers. */
if (cfun->machine->interrupt_handler_p
&& mips_interrupt_extra_call_saved_reg_p (regno))
@ -14040,12 +14045,16 @@ mips_call_expr_from_insn (rtx insn, rtx *second_call)
}
/* REG is set in DEF. See if the definition is one of the ways we load a
register with a symbol address for a mips_use_pic_fn_addr_reg_p call. If
it is return the symbol reference of the function, otherwise return
NULL_RTX. */
register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
If it is, return the symbol reference of the function, otherwise return
NULL_RTX.
If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
the values of source registers, otherwise treat such registers as
having an unknown value. */
static rtx
mips_pic_call_symbol_from_set (df_ref def, rtx reg)
mips_pic_call_symbol_from_set (df_ref def, rtx reg, bool recurse_p)
{
rtx def_insn, set;
@ -14072,21 +14081,39 @@ mips_pic_call_symbol_from_set (df_ref def, rtx reg)
return symbol;
}
/* Follow simple register copies. */
if (REG_P (src))
return mips_find_pic_call_symbol (def_insn, src);
/* Follow at most one simple register copy. Such copies are
interesting in cases like:
for (...)
{
locally_binding_fn (...);
}
and:
locally_binding_fn (...);
...
locally_binding_fn (...);
where the load of locally_binding_fn can legitimately be
hoisted or shared. However, we do not expect to see complex
chains of copies, so a full worklist solution to the problem
would probably be overkill. */
if (recurse_p && REG_P (src))
return mips_find_pic_call_symbol (def_insn, src, false);
}
return NULL_RTX;
}
/* Find the definition of the use of REG in INSN. See if the definition is
one of the ways we load a register with a symbol address for a
mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference of
the function, otherwise return NULL_RTX. */
/* Find the definition of the use of REG in INSN. See if the definition
is one of the ways we load a register with a symbol address for a
mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
of the function, otherwise return NULL_RTX. RECURSE_P is as for
mips_pic_call_symbol_from_set. */
static rtx
mips_find_pic_call_symbol (rtx insn, rtx reg)
mips_find_pic_call_symbol (rtx insn, rtx reg, bool recurse_p)
{
df_ref use;
struct df_link *defs;
@ -14098,7 +14125,7 @@ mips_find_pic_call_symbol (rtx insn, rtx reg)
defs = DF_REF_CHAIN (use);
if (!defs)
return NULL_RTX;
symbol = mips_pic_call_symbol_from_set (defs->ref, reg);
symbol = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
if (!symbol)
return NULL_RTX;
@ -14107,7 +14134,7 @@ mips_find_pic_call_symbol (rtx insn, rtx reg)
{
rtx other;
other = mips_pic_call_symbol_from_set (defs->ref, reg);
other = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
if (!rtx_equal_p (symbol, other))
return NULL_RTX;
}
@ -14178,7 +14205,7 @@ mips_annotate_pic_calls (void)
if (!REG_P (reg))
continue;
symbol = mips_find_pic_call_symbol (insn, reg);
symbol = mips_find_pic_call_symbol (insn, reg, true);
if (symbol)
{
mips_annotate_pic_call_expr (call, symbol);

2
external/gpl3/gcc/dist/gcc/config/mips/mips.md vendored
View File

@ -4806,7 +4806,7 @@
;; of _gp from the start of this function. Operand 1 is the incoming
;; function address.
(define_insn_and_split "loadgp_newabi_<mode>"
[(set (match_operand:P 0 "register_operand" "=d")
[(set (match_operand:P 0 "register_operand" "=&d")
(unspec:P [(match_operand:P 1)
(match_operand:P 2 "register_operand" "d")]
UNSPEC_LOADGP))]

4
external/gpl3/gcc/dist/gcc/config/pa/linux-unwind.h vendored
View File

@ -1,5 +1,5 @@
/* DWARF2 EH unwinding support for PA Linux.
Copyright (C) 2004, 2005, 2009 Free Software Foundation, Inc.
Copyright (C) 2004, 2005, 2009, 2012 Free Software Foundation, Inc.
This file is part of GCC.
@ -63,7 +63,7 @@ pa32_fallback_frame_state (struct _Unwind_Context *context,
int i;
struct sigcontext *sc;
struct rt_sigframe {
struct siginfo info;
siginfo_t info;
struct ucontext uc;
} *frame;

2
external/gpl3/gcc/dist/gcc/config/pa/pa-protos.h vendored
View File

@ -79,7 +79,6 @@ extern int move_src_operand (rtx, enum machine_mode);
extern int prefetch_cc_operand (rtx, enum machine_mode);
extern int prefetch_nocc_operand (rtx, enum machine_mode);
extern int and_operand (rtx, enum machine_mode);
extern int ior_operand (rtx, enum machine_mode);
extern int arith32_operand (rtx, enum machine_mode);
extern int uint32_operand (rtx, enum machine_mode);
extern int reg_before_reload_operand (rtx, enum machine_mode);
@ -94,7 +93,6 @@ extern int ireg_or_int5_operand (rtx, enum machine_mode);
extern int fmpyaddoperands (rtx *);
extern int fmpysuboperands (rtx *);
extern int call_operand_address (rtx, enum machine_mode);
extern int ior_operand (rtx, enum machine_mode);
extern void emit_bcond_fp (rtx[]);
extern int emit_move_sequence (rtx *, enum machine_mode, rtx);
extern int emit_hpdiv_const (rtx *, int);

47
external/gpl3/gcc/dist/gcc/config/pa/pa.md vendored
View File

@ -811,7 +811,7 @@
(match_operand:DI 3 "arith11_operand" "rI"))
(match_operand:DI 1 "register_operand" "r")))]
"TARGET_64BIT"
"sub%I3,* %3,%2,%%r0\;add,dc %%r0,%1,%0"
"sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
[(set_attr "type" "binary")
(set_attr "length" "8")])
@ -833,7 +833,7 @@
(match_operand:DI 3 "register_operand" "r"))
(match_operand:DI 1 "register_operand" "r")))]
"TARGET_64BIT"
"sub,* %2,%3,%%r0\;add,dc %%r0,%1,%0"
"sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
[(set_attr "type" "binary")
(set_attr "length" "8")])
@ -856,7 +856,7 @@
(match_operand:DI 3 "int11_operand" "I"))
(match_operand:DI 1 "register_operand" "r")))]
"TARGET_64BIT"
"addi,* %k3,%2,%%r0\;add,dc %%r0,%1,%0"
"addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
[(set_attr "type" "binary")
(set_attr "length" "8")])
@ -902,7 +902,7 @@
(gtu:DI (match_operand:DI 2 "register_operand" "r")
(match_operand:DI 3 "arith11_operand" "rI"))))]
"TARGET_64BIT"
"sub%I3,* %3,%2,%%r0\;sub,db %1,%%r0,%0"
"sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
[(set_attr "type" "binary")
(set_attr "length" "8")])
@ -924,7 +924,7 @@
(match_operand:DI 3 "arith11_operand" "rI")))
(match_operand:DI 4 "register_operand" "r")))]
"TARGET_64BIT"
"sub%I3,* %3,%2,%%r0\;sub,db %1,%4,%0"
"sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
[(set_attr "type" "binary")
(set_attr "length" "8")])
@ -946,7 +946,7 @@
(ltu:DI (match_operand:DI 2 "register_operand" "r")
(match_operand:DI 3 "register_operand" "r"))))]
"TARGET_64BIT"
"sub,* %2,%3,%%r0\;sub,db %1,%%r0,%0"
"sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
[(set_attr "type" "binary")
(set_attr "length" "8")])
@ -968,7 +968,7 @@
(match_operand:DI 3 "register_operand" "r")))
(match_operand:DI 4 "register_operand" "r")))]
"TARGET_64BIT"
"sub,* %2,%3,%%r0\;sub,db %1,%4,%0"
"sub %2,%3,%%r0\;sub,db %1,%4,%0"
[(set_attr "type" "binary")
(set_attr "length" "8")])
@ -991,7 +991,7 @@
(leu:DI (match_operand:DI 2 "register_operand" "r")
(match_operand:DI 3 "int11_operand" "I"))))]
"TARGET_64BIT"
"addi,* %k3,%2,%%r0\;sub,db %1,%%r0,%0"
"addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
[(set_attr "type" "binary")
(set_attr "length" "8")])
@ -1013,7 +1013,7 @@
(match_operand:DI 3 "int11_operand" "I")))
(match_operand:DI 4 "register_operand" "r")))]
"TARGET_64BIT"
"addi,* %k3,%2,%%r0\;sub,db %1,%4,%0"
"addi %k3,%2,%%r0\;sub,db %1,%4,%0"
[(set_attr "type" "binary")
(set_attr "length" "8")])
@ -5686,7 +5686,7 @@
(define_expand "iordi3"
[(set (match_operand:DI 0 "register_operand" "")
(ior:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "ior_operand" "")))]
(match_operand:DI 2 "reg_or_cint_ior_operand" "")))]
""
"
{
@ -5707,7 +5707,7 @@
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r,r")
(ior:DI (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "ior_operand" "M,i")))]
(match_operand:DI 2 "cint_ior_operand" "M,i")))]
"TARGET_64BIT"
"* return output_64bit_ior (operands); "
[(set_attr "type" "binary,shift")
@ -5726,19 +5726,14 @@
(define_expand "iorsi3"
[(set (match_operand:SI 0 "register_operand" "")
(ior:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "arith32_operand" "")))]
(match_operand:SI 2 "reg_or_cint_ior_operand" "")))]
""
"
{
if (! (ior_operand (operands[2], SImode)
|| register_operand (operands[2], SImode)))
operands[2] = force_reg (SImode, operands[2]);
}")
"")
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r,r")
(ior:SI (match_operand:SI 1 "register_operand" "0,0")
(match_operand:SI 2 "ior_operand" "M,i")))]
(match_operand:SI 2 "cint_ior_operand" "M,i")))]
""
"* return output_ior (operands); "
[(set_attr "type" "binary,shift")
@ -6566,7 +6561,7 @@
""
"*
{
int x = INTVAL (operands[1]);
unsigned HOST_WIDE_INT x = UINTVAL (operands[1]);
operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
operands[1] = GEN_INT ((x & 0xf) - 0x10);
return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
@ -6584,7 +6579,7 @@
"exact_log2 (INTVAL (operands[1]) + 1) > 0"
"*
{
int x = INTVAL (operands[1]);
HOST_WIDE_INT x = INTVAL (operands[1]);
operands[2] = GEN_INT (exact_log2 (x + 1));
return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
}"
@ -6601,7 +6596,7 @@
"INTVAL (operands[1]) == -2"
"*
{
int x = INTVAL (operands[1]);
HOST_WIDE_INT x = INTVAL (operands[1]);
operands[2] = GEN_INT (exact_log2 ((~x) + 1));
return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
}"
@ -6665,7 +6660,7 @@
"TARGET_64BIT"
"*
{
int x = INTVAL (operands[1]);
unsigned HOST_WIDE_INT x = UINTVAL (operands[1]);
operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
operands[1] = GEN_INT ((x & 0x1f) - 0x20);
return \"depdi,z %1,%%sar,%2,%0\";
@ -6683,7 +6678,7 @@
"TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) > 0"
"*
{
int x = INTVAL (operands[1]);
HOST_WIDE_INT x = INTVAL (operands[1]);
operands[2] = GEN_INT (exact_log2 (x + 1));
return \"depdi -1,%%sar,%2,%0\";
}"
@ -6700,7 +6695,7 @@
"TARGET_64BIT && INTVAL (operands[1]) == -2"
"*
{
int x = INTVAL (operands[1]);
HOST_WIDE_INT x = INTVAL (operands[1]);
operands[2] = GEN_INT (exact_log2 ((~x) + 1));
return \"depdi 0,%%sar,%2,%0\";
}"
@ -7131,7 +7126,7 @@
{
rtx index = gen_reg_rtx (SImode);
operands[1] = GEN_INT (-INTVAL (operands[1]));
operands[1] = gen_int_mode (-INTVAL (operands[1]), SImode);
if (!INT_14_BITS (operands[1]))
operands[1] = force_reg (SImode, operands[1]);
emit_insn (gen_addsi3 (index, operands[0], operands[1]));

20
external/gpl3/gcc/dist/gcc/config/pa/predicates.md vendored
View File

@ -411,15 +411,19 @@
;; True iff depi can be used to compute (reg | OP).
(define_predicate "ior_operand"
(match_code "const_int")
{
return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
})
(define_predicate "cint_ior_operand"
(and (match_code "const_int")
(match_test "ior_mask_p (INTVAL (op))")))
;; True iff OP is a CONST_INT of the forms 0...0xxxx or
;; 0...01...1xxxx. Such values can be the left hand side x in (x <<
;; r), using the zvdepi instruction.
;; True iff OP can be used to compute (reg | OP).
(define_predicate "reg_or_cint_ior_operand"
(ior (match_operand 0 "register_operand")
(match_operand 0 "cint_ior_operand")))
;; True iff OP is a CONST_INT of the forms 0...0xxxx, 0...01...1xxxx,
;; or 1...1xxxx. Such values can be the left hand side x in (x << r),
;; using the zvdepi instruction.
(define_predicate "lhs_lshift_cint_operand"
(match_code "const_int")

20
external/gpl3/gcc/dist/gcc/config/rs6000/altivec.md vendored
View File

@ -497,7 +497,7 @@
[(set (match_operand:VM 0 "altivec_register_operand" "=v")
(if_then_else:VM
(ne:CC (match_operand:VM 1 "altivec_register_operand" "v")
(const_int 0))
(match_operand:VM 4 "zero_constant" ""))
(match_operand:VM 2 "altivec_register_operand" "v")
(match_operand:VM 3 "altivec_register_operand" "v")))]
"VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
@ -508,7 +508,7 @@
[(set (match_operand:VM 0 "altivec_register_operand" "=v")
(if_then_else:VM
(ne:CCUNS (match_operand:VM 1 "altivec_register_operand" "v")
(const_int 0))
(match_operand:VM 4 "zero_constant" ""))
(match_operand:VM 2 "altivec_register_operand" "v")
(match_operand:VM 3 "altivec_register_operand" "v")))]
"VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
@ -2396,8 +2396,8 @@
(define_insn "altivec_stvlx"
[(parallel
[(set (match_operand:V4SI 0 "memory_operand" "=Z")
(match_operand:V4SI 1 "register_operand" "v"))
[(set (match_operand:V16QI 0 "memory_operand" "=Z")
(match_operand:V16QI 1 "register_operand" "v"))
(unspec [(const_int 0)] UNSPEC_STVLX)])]
"TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
"stvlx %1,%y0"
@ -2405,8 +2405,8 @@
(define_insn "altivec_stvlxl"
[(parallel
[(set (match_operand:V4SI 0 "memory_operand" "=Z")
(match_operand:V4SI 1 "register_operand" "v"))
[(set (match_operand:V16QI 0 "memory_operand" "=Z")
(match_operand:V16QI 1 "register_operand" "v"))
(unspec [(const_int 0)] UNSPEC_STVLXL)])]
"TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
"stvlxl %1,%y0"
@ -2414,8 +2414,8 @@
(define_insn "altivec_stvrx"
[(parallel
[(set (match_operand:V4SI 0 "memory_operand" "=Z")
(match_operand:V4SI 1 "register_operand" "v"))
[(set (match_operand:V16QI 0 "memory_operand" "=Z")
(match_operand:V16QI 1 "register_operand" "v"))
(unspec [(const_int 0)] UNSPEC_STVRX)])]
"TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
"stvrx %1,%y0"
@ -2423,8 +2423,8 @@
(define_insn "altivec_stvrxl"
[(parallel
[(set (match_operand:V4SI 0 "memory_operand" "=Z")
(match_operand:V4SI 1 "register_operand" "v"))
[(set (match_operand:V16QI 0 "memory_operand" "=Z")
(match_operand:V16QI 1 "register_operand" "v"))
(unspec [(const_int 0)] UNSPEC_STVRXL)])]
"TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
"stvrxl %1,%y0"

32
external/gpl3/gcc/dist/gcc/config/rs6000/rs6000.h vendored
View File

@ -1038,10 +1038,9 @@ extern unsigned rs6000_pointer_size;
/* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate
enough space to account for vectors in FP regs. */
#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
(TARGET_VSX \
&& ((MODE) == VOIDmode || VSX_VECTOR_MODE (MODE) \
|| ALTIVEC_VECTOR_MODE (MODE)) \
#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
(TARGET_VSX \
&& ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \
&& FP_REGNO_P (REGNO) \
? V2DFmode \
: choose_hard_reg_mode ((REGNO), (NREGS), false))
@ -1057,25 +1056,16 @@ extern unsigned rs6000_pointer_size;
((MODE) == V4SFmode \
|| (MODE) == V2DFmode) \
#define VSX_SCALAR_MODE(MODE) \
((MODE) == DFmode)
#define VSX_MODE(MODE) \
(VSX_VECTOR_MODE (MODE) \
|| VSX_SCALAR_MODE (MODE))
#define VSX_MOVE_MODE(MODE) \
(VSX_VECTOR_MODE (MODE) \
|| VSX_SCALAR_MODE (MODE) \
|| ALTIVEC_VECTOR_MODE (MODE) \
|| (MODE) == TImode)
#define ALTIVEC_VECTOR_MODE(MODE) \
((MODE) == V16QImode \
|| (MODE) == V8HImode \
|| (MODE) == V4SFmode \
|| (MODE) == V4SImode)
#define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \
(ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \
|| (MODE) == V2DImode)
#define SPE_VECTOR_MODE(MODE) \
((MODE) == V4HImode \
|| (MODE) == V2SFmode \
@ -1118,10 +1108,10 @@ extern unsigned rs6000_pointer_size;
? ALTIVEC_VECTOR_MODE (MODE2) \
: ALTIVEC_VECTOR_MODE (MODE2) \
? ALTIVEC_VECTOR_MODE (MODE1) \
: VSX_VECTOR_MODE (MODE1) \
? VSX_VECTOR_MODE (MODE2) \
: VSX_VECTOR_MODE (MODE2) \
? VSX_VECTOR_MODE (MODE1) \
: ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \
? ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \
: ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \
? ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \
: 1)
/* Post-reload, we can't use any new AltiVec registers, as we already

58
external/gpl3/gcc/dist/gcc/config/rs6000/rs6000.md vendored
View File

@ -2483,7 +2483,18 @@
if (GET_CODE (addr1) == PLUS)
{
emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
if (TARGET_AVOID_XFORM)
{
emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
addr2 = op2;
}
else
addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
}
else if (TARGET_AVOID_XFORM)
{
emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
addr2 = op2;
}
else
{
@ -2533,7 +2544,18 @@
if (GET_CODE (addr1) == PLUS)
{
emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
if (TARGET_AVOID_XFORM)
{
emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
addr2 = op2;
}
else
addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
}
else if (TARGET_AVOID_XFORM)
{
emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
addr2 = op2;
}
else
{
@ -2614,7 +2636,18 @@
if (GET_CODE (addr1) == PLUS)
{
emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
if (TARGET_AVOID_XFORM)
{
emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
addr2 = op2;
}
else
addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
}
else if (TARGET_AVOID_XFORM)
{
emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
addr2 = op2;
}
else
{
@ -2659,7 +2692,18 @@
if (GET_CODE (addr1) == PLUS)
{
emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
if (TARGET_AVOID_XFORM)
{
emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
addr2 = op2;
}
else
addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
}
else if (TARGET_AVOID_XFORM)
{
emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
addr2 = op2;
}
else
{
@ -12473,7 +12517,11 @@
[(set (match_operand 0 "memory_operand" "=m")
(unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
""
"{st%U0%X0|stw%U0%X0} 0,%0"
"*
{
operands[1] = gen_rtx_REG (Pmode, 0);
return \"{st%U0%X0|stw%U0%X0} %1,%0\";
}"
[(set_attr "type" "store")
(set_attr "length" "4")])

96
external/gpl3/gcc/dist/gcc/config/rs6000/vector.md vendored
View File

@ -441,27 +441,115 @@
"VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
"")
(define_insn_and_split "*vector_uneq<mode>"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(uneq:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
(match_operand:VEC_F 2 "vfloat_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"#"
""
[(set (match_dup 3)
(gt:VEC_F (match_dup 1)
(match_dup 2)))
(set (match_dup 4)
(gt:VEC_F (match_dup 2)
(match_dup 1)))
(set (match_dup 0)
(not:VEC_F (ior:VEC_F (match_dup 3)
(match_dup 4))))]
"
{
operands[3] = gen_reg_rtx (<MODE>mode);
operands[4] = gen_reg_rtx (<MODE>mode);
}")
(define_insn_and_split "*vector_ltgt<mode>"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(ltgt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
(match_operand:VEC_F 2 "vfloat_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"#"
""
[(set (match_dup 3)
(gt:VEC_F (match_dup 1)
(match_dup 2)))
(set (match_dup 4)
(gt:VEC_F (match_dup 2)
(match_dup 1)))
(set (match_dup 0)
(ior:VEC_F (match_dup 3)
(match_dup 4)))]
"
{
operands[3] = gen_reg_rtx (<MODE>mode);
operands[4] = gen_reg_rtx (<MODE>mode);
}")
(define_insn_and_split "*vector_ordered<mode>"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(ordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
(match_operand:VEC_F 2 "vfloat_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"#"
""
[(set (match_dup 3)
(ge:VEC_F (match_dup 1)
(match_dup 2)))
(set (match_dup 4)
(ge:VEC_F (match_dup 2)
(match_dup 1)))
(set (match_dup 0)
(ior:VEC_F (match_dup 3)
(match_dup 4)))]
"
{
operands[3] = gen_reg_rtx (<MODE>mode);
operands[4] = gen_reg_rtx (<MODE>mode);
}")
(define_insn_and_split "*vector_unordered<mode>"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(unordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
(match_operand:VEC_F 2 "vfloat_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"#"
""
[(set (match_dup 3)
(ge:VEC_F (match_dup 1)
(match_dup 2)))
(set (match_dup 4)
(ge:VEC_F (match_dup 2)
(match_dup 1)))
(set (match_dup 0)
(not:VEC_F (ior:VEC_F (match_dup 3)
(match_dup 4))))]
"
{
operands[3] = gen_reg_rtx (<MODE>mode);
operands[4] = gen_reg_rtx (<MODE>mode);
}")
;; Note the arguments for __builtin_altivec_vsel are op2, op1, mask
;; which is in the reverse order that we want
(define_expand "vector_select_<mode>"
[(set (match_operand:VEC_L 0 "vlogical_operand" "")
(if_then_else:VEC_L
(ne:CC (match_operand:VEC_L 3 "vlogical_operand" "")
(const_int 0))
(match_dup 4))
(match_operand:VEC_L 2 "vlogical_operand" "")
(match_operand:VEC_L 1 "vlogical_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
"operands[4] = CONST0_RTX (<MODE>mode);")
(define_expand "vector_select_<mode>_uns"
[(set (match_operand:VEC_L 0 "vlogical_operand" "")
(if_then_else:VEC_L
(ne:CCUNS (match_operand:VEC_L 3 "vlogical_operand" "")
(const_int 0))
(match_dup 4))
(match_operand:VEC_L 2 "vlogical_operand" "")
(match_operand:VEC_L 1 "vlogical_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
"operands[4] = CONST0_RTX (<MODE>mode);")
;; Expansions that compare vectors producing a vector result and a predicate,
;; setting CR6 to indicate a combined status

8
external/gpl3/gcc/dist/gcc/config/rs6000/vsx.md vendored
View File

@ -844,7 +844,7 @@
[(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")
(if_then_else:VSX_L
(ne:CC (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,wa")
(const_int 0))
(match_operand:VSX_L 4 "zero_constant" ""))
(match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,wa")
(match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,wa")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
@ -855,7 +855,7 @@
[(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")
(if_then_else:VSX_L
(ne:CCUNS (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,wa")
(const_int 0))
(match_operand:VSX_L 4 "zero_constant" ""))
(match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,wa")
(match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,wa")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
@ -1161,9 +1161,9 @@
"VECTOR_MEM_VSX_P (<MODE>mode)"
{
if (INTVAL (operands[3]) == 0)
return \"xxpermdi %x0,%x1,%x2,1\";
return \"xxpermdi %x0,%x2,%x1,1\";
else if (INTVAL (operands[3]) == 1)
return \"xxpermdi %x0,%x2,%x1,0\";
return \"xxpermdi %x0,%x1,%x2,0\";
else
gcc_unreachable ();
}

2
external/gpl3/gcc/dist/gcc/config/rx/rx.c vendored
View File

@ -2158,10 +2158,10 @@ rx_expand_builtin (tree exp,
if (! valid_psw_flag (op, "clrpsw"))
return NULL_RTX;
return rx_expand_void_builtin_1_arg (op, gen_clrpsw, false);
case RX_BUILTIN_SETPSW:
if (! valid_psw_flag (op, "setpsw"))
return NULL_RTX;
return rx_expand_void_builtin_1_arg (op, gen_setpsw, false);
case RX_BUILTIN_SETPSW:
case RX_BUILTIN_INT: return rx_expand_void_builtin_1_arg
(op, gen_int, false);
case RX_BUILTIN_MACHI: return rx_expand_builtin_mac (exp, gen_machi);

2
external/gpl3/gcc/dist/gcc/config/rx/rx.h vendored
View File

@ -168,7 +168,7 @@ extern enum rx_cpu_types rx_cpu_type;
#define HANDLE_PRAGMA_PACK_PUSH_POP 1
#define HAVE_PRE_DECCREMENT 1
#define HAVE_PRE_DECREMENT 1
#define HAVE_POST_INCREMENT 1
#define MOVE_RATIO(SPEED) ((SPEED) ? 4 : 2)

64
external/gpl3/gcc/dist/gcc/config/rx/rx.md vendored
View File

@ -709,24 +709,24 @@
(clobber (reg:CC CC_REG))])]
""
{
/* ??? Support other conditions via cstore into a temporary? */
if (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE)
FAIL;
/* One operand must be a constant. */
if (!CONSTANT_P (operands[2]) && !CONSTANT_P (operands[3]))
/* One operand must be a constant or a register, the other must be a register. */
if ( ! CONSTANT_P (operands[2])
&& ! CONSTANT_P (operands[3])
&& ! (REG_P (operands[2]) && REG_P (operands[3])))
FAIL;
})
(define_insn_and_split "*movsicc"
[(set (match_operand:SI 0 "register_operand" "=r,r")
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
(if_then_else:SI
(match_operator 5 "rx_z_comparison_operator"
[(match_operand:SI 3 "register_operand" "r,r")
(match_operand:SI 4 "rx_source_operand" "riQ,riQ")])
(match_operand:SI 1 "nonmemory_operand" "i,ri")
(match_operand:SI 2 "nonmemory_operand" "ri,i")))
(match_operator 5 "comparison_operator"
[(match_operand:SI 3 "register_operand" "r,r,r")
(match_operand:SI 4 "rx_source_operand" "riQ,riQ,riQ")])
(match_operand:SI 1 "nonmemory_operand" "i,ri,r")
(match_operand:SI 2 "nonmemory_operand" "ri,i,r")))
(clobber (reg:CC CC_REG))]
"CONSTANT_P (operands[1]) || CONSTANT_P (operands[2])"
"(CONSTANT_P (operands[1]) || CONSTANT_P (operands[2]))
|| (REG_P (operands[1]) && REG_P (operands[2]))"
"#"
"&& reload_completed"
[(const_int 0)]
@ -743,8 +743,11 @@
op1 = operands[1];
op2 = operands[2];
/* If OP2 is the constant, reverse the sense of the move. */
if (!CONSTANT_P (operands[1]))
/* If OP2 is the constant, reverse the sense of the move.
Likewise if both operands are registers but OP1 == OP0. */
if ((! CONSTANT_P (operands[1]) && CONSTANT_P (operands[2]))
|| (REG_P (operands[1]) && REG_P (operands[2])
&& rtx_equal_p (op0, op1)))
{
x = op1, op1 = op2, op2 = x;
cmp_code = reverse_condition (cmp_code);
@ -753,7 +756,7 @@
/* If OP2 does not match the output, copy it into place. We have allowed
these alternatives so that the destination can legitimately be one of
the comparison operands without increasing register pressure. */
if (!rtx_equal_p (op0, op2))
if (! rtx_equal_p (op0, op2))
emit_move_insn (op0, op2);
x = gen_rtx_fmt_ee (cmp_code, VOIDmode, flags, const0_rtx);
@ -769,16 +772,33 @@
[(reg CC_REG) (const_int 0)])
(match_operand:SI 1 "immediate_operand" "Sint08,Sint16,Sint24,i")
(match_dup 0)))]
"reload_completed"
{
if (GET_CODE (operands[2]) == EQ)
return "stz\t%1, %0";
else
return "stnz\t%1, %0";
}
"reload_completed
&& ((GET_CODE (operands[2]) == EQ) || (GET_CODE (operands[2]) == NE))"
{
if (GET_CODE (operands[2]) == EQ)
return "stz\t%1, %0";
else
return "stnz\t%1, %0";
}
[(set_attr "length" "4,5,6,7")]
)
(define_insn "*stcc_reg"
[(set (match_operand:SI 0 "register_operand" "+r,r,r,r,r,r")
(if_then_else:SI
(match_operator 2 "comparison_operator"
[(reg CC_REG) (const_int 0)])
(match_operand:SI 1 "nonmemory_operand"
"r,Uint04,Sint08,Sint16,Sint24,i")
(match_dup 0)))]
"reload_completed"
{
PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
return "b%B2 1f\n\tmov %1, %0\n1:";
}
[(set_attr "length" "3,3,4,5,6,7")]
)
;; Arithmetic Instructions
(define_insn "abssi2"

9
external/gpl3/gcc/dist/gcc/config/sh/linux-unwind.h vendored
View File

@ -1,5 +1,6 @@
/* DWARF2 EH unwinding support for SH Linux.
Copyright (C) 2004, 2005, 2006, 2007, 2009 Free Software Foundation, Inc.
Copyright (C) 2004, 2005, 2006, 2007, 2009, 2012 Free Software Foundation,
Inc.
This file is part of GCC.
@ -80,9 +81,9 @@ shmedia_fallback_frame_state (struct _Unwind_Context *context,
&& (*(unsigned long *) (pc+11) == 0x6ff0fff0))
{
struct rt_sigframe {
struct siginfo *pinfo;
siginfo_t *pinfo;
void *puc;
struct siginfo info;
siginfo_t info;
struct ucontext uc;
} *rt_ = context->cfa;
/* The void * cast is necessary to avoid an aliasing warning.
@ -179,7 +180,7 @@ sh_fallback_frame_state (struct _Unwind_Context *context,
&& (*(unsigned short *) (pc+14) == 0x00ad))))
{
struct rt_sigframe {
struct siginfo info;
siginfo_t info;
struct ucontext uc;
} *rt_ = context->cfa;
/* The void * cast is necessary to avoid an aliasing warning.

30
external/gpl3/gcc/dist/gcc/config/sh/sh.md vendored
View File

@ -149,6 +149,7 @@
(UNSPEC_DIV_INV_TABLE 37)
(UNSPEC_ASHIFTRT 35)
(UNSPEC_THUNK 36)
(UNSPEC_CHKADD 38)
(UNSPEC_SP_SET 40)
(UNSPEC_SP_TEST 41)
(UNSPEC_MOVUA 42)
@ -8438,6 +8439,22 @@ label:
i++;
}")
;; op0 = op1 + r12 but hide it before reload completed. See the comment
;; in symGOT_load expand.
(define_insn_and_split "chk_guard_add"
[(set (match_operand:SI 0 "register_operand" "=&r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r")
(reg:SI PIC_REG)]
UNSPEC_CHKADD))]
"TARGET_SH1"
"#"
"TARGET_SH1 && reload_completed"
[(set (match_dup 0) (reg:SI PIC_REG))
(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
""
[(set_attr "type" "arith")])
(define_expand "sym_label2reg"
[(set (match_operand:SI 0 "" "")
(const:SI (unspec:SI [(match_operand:SI 1 "" "")
@ -8480,13 +8497,9 @@ label:
else
emit_move_insn (operands[2], operands[1]);
emit_move_insn (operands[3], gen_rtx_PLUS (Pmode,
operands[2],
gen_rtx_REG (Pmode, PIC_REG)));
/* When stack protector inserts codes after the result is set to
R0, @(rX, r12) will cause a spill failure for R0. Don't schedule
insns to avoid combining (set A (plus rX r12)) and (set op0 (mem A))
R0, @(rX, r12) will cause a spill failure for R0. Use a unspec
insn to avoid combining (set A (plus rX r12)) and (set op0 (mem A))
when rX is a GOT address for the guard symbol. Ugly but doesn't
matter because this is a rare situation. */
if (!TARGET_SHMEDIA
@ -8496,7 +8509,10 @@ label:
&& GET_CODE (XVECEXP (XEXP (operands[1], 0), 0, 0)) == SYMBOL_REF
&& strcmp (XSTR (XVECEXP (XEXP (operands[1], 0), 0, 0), 0),
\"__stack_chk_guard\") == 0)
emit_insn (gen_blockage ());
emit_insn (gen_chk_guard_add (operands[3], operands[2]));
else
emit_move_insn (operands[3], gen_rtx_PLUS (Pmode, operands[2],
gen_rtx_REG (Pmode, PIC_REG)));
/* N.B. This is not constant for a GOTPLT relocation. */
mem = gen_rtx_MEM (Pmode, operands[3]);

7
external/gpl3/gcc/dist/gcc/config/sparc/sol2-64.h vendored
View File

@ -1,7 +1,7 @@
/* Definitions of target machine for GCC, for bi-arch SPARC
running Solaris 2, defaulting to 64-bit code generation.
Copyright (C) 1999, 2010 Free Software Foundation, Inc.
Copyright (C) 1999, 2010, 2011 Free Software Foundation, Inc.
This file is part of GCC.
@ -19,7 +19,4 @@ You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_V9 + MASK_PTR64 + MASK_64BIT /* + MASK_HARD_QUAD */ + \
MASK_STACK_BIAS + MASK_APP_REGS + MASK_FPU + MASK_LONG_DOUBLE_128)
#define TARGET_64BIT_DEFAULT 1

12
external/gpl3/gcc/dist/gcc/config/sparc/sol2-unwind.h vendored
View File

@ -123,10 +123,10 @@ sparc64_fallback_frame_state (struct _Unwind_Context *context,
/* This matches the call_user_handler pattern for Solaris 10.
There are 2 cases so we look for the return address of the
caller's caller frame in order to do more pattern matching. */
unsigned int sah_pattern
= *(unsigned int *)(*(unsigned long *)(this_cfa + 176 + 15*8) - 4);
unsigned long sah_address
= *(unsigned long *)(this_cfa + 176 + 15*8);
if (sah_pattern == 0x92100019)
if (sah_address && *(unsigned int *)(sah_address - 4) == 0x92100019)
/* This is the same setup as for Solaris 9, see below. */
regs_off = 176 + 176 + 176 + 304;
else
@ -371,10 +371,10 @@ sparc_fallback_frame_state (struct _Unwind_Context *context,
/* This matches the call_user_handler pattern for Solaris 10.
There are 2 cases so we look for the return address of the
caller's caller frame in order to do more pattern matching. */
unsigned int sah_pattern
= *(unsigned int *)(*(unsigned int *)(this_cfa + 96 + 15*4) - 4);
unsigned int sah_address
= *(unsigned int *)(this_cfa + 96 + 15*4);
if (sah_pattern == 0x92100019)
if (sah_address && *(unsigned int *)(sah_address - 4) == 0x92100019)
/* This is the same setup as for Solaris 9, see below. */
regs_off = 96 + 96 + 96 + 160;
else

15
external/gpl3/gcc/dist/gcc/config/sparc/sol2.h vendored
View File

@ -153,11 +153,18 @@ along with GCC; see the file COPYING3. If not see
#undef SUN_INTEGER_MULTIPLY_64
#define SUN_INTEGER_MULTIPLY_64 1
/* Solaris allows 64 bit out and global registers in 32 bit mode.
sparc_override_options will disable V8+ if not generating V9 code. */
/* Solaris allows 64-bit out and global registers to be used in 32-bit mode.
sparc_override_options will disable V8+ if either not generating V9 code
or generating 64-bit code. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_V8PLUS + MASK_APP_REGS + MASK_FPU \
+ MASK_LONG_DOUBLE_128)
#ifdef TARGET_64BIT_DEFAULT
#define TARGET_DEFAULT \
(MASK_V9 + MASK_64BIT + MASK_PTR64 + MASK_STACK_BIAS + \
MASK_V8PLUS + MASK_APP_REGS + MASK_FPU + MASK_LONG_DOUBLE_128)
#else
#define TARGET_DEFAULT \
(MASK_V8PLUS + MASK_APP_REGS + MASK_FPU + MASK_LONG_DOUBLE_128)
#endif
/* Solaris-specific #pragmas are implemented on top of attributes. Hook in
the bits from config/sol2.c. */

1
external/gpl3/gcc/dist/gcc/config/sparc/sparc-protos.h vendored
View File

@ -48,6 +48,7 @@ extern bool sparc_can_use_return_insn_p (void);
extern int check_pic (int);
extern int short_branch (int, int);
extern void sparc_profile_hook (int);
extern void sparc_optimization_options (int, int);
extern void sparc_override_options (void);
extern void sparc_output_scratch_registers (FILE *);

59
external/gpl3/gcc/dist/gcc/config/sparc/sparc.c vendored
View File

@ -627,6 +627,17 @@ sparc_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
return true;
}
/* Specify default optimizations. */
void
sparc_optimization_options (int l ATTRIBUTE_UNUSED, int s ATTRIBUTE_UNUSED)
{
/* Disable save slot sharing for call-clobbered registers by default.
The IRA sharing algorithm works on single registers only and this
pessimizes for double floating-point registers. */
flag_ira_share_save_slots = 0;
}
/* Validate and override various options, and do some machine dependent
initialization. */
@ -2767,11 +2778,6 @@ eligible_for_return_delay (rtx trial)
if (get_attr_length (trial) != 1)
return 0;
/* If there are any call-saved registers, we should scan TRIAL if it
does not reference them. For now just make it easy. */
if (num_gfregs)
return 0;
/* If the function uses __builtin_eh_return, the eh_return machinery
occupies the delay slot. */
if (crtl->calls_eh_return)
@ -4093,7 +4099,7 @@ save_or_restore_regs (int low, int high, rtx base, int offset, int action)
emit_move_insn (gen_rtx_REG (mode, regno), mem);
/* Always preserve double-word alignment. */
offset = (offset + 7) & -8;
offset = (offset + 8) & -8;
}
}
@ -4200,7 +4206,7 @@ sparc_expand_prologue (void)
example, the regrename pass has special provisions to not rename to
non-leaf registers in a leaf function. */
sparc_leaf_function_p
= optimize > 0 && leaf_function_p () && only_leaf_regs_used ();
= optimize > 0 && current_function_is_leaf && only_leaf_regs_used ();
/* Need to use actual_fsize, since we are also allocating
space for our callee (and our own register save area). */
@ -4230,8 +4236,9 @@ sparc_expand_prologue (void)
else if (actual_fsize <= 8192)
{
insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
/* %sp is still the CFA register. */
RTX_FRAME_RELATED_P (insn) = 1;
/* %sp is still the CFA register. */
insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096-actual_fsize)));
}
@ -4253,8 +4260,18 @@ sparc_expand_prologue (void)
else if (actual_fsize <= 8192)
{
insn = emit_insn (gen_save_register_window (GEN_INT (-4096)));
/* %sp is not the CFA register anymore. */
emit_insn (gen_stack_pointer_inc (GEN_INT (4096-actual_fsize)));
/* Make sure no %fp-based store is issued until after the frame is
established. The offset between the frame pointer and the stack
pointer is calculated relative to the value of the stack pointer
at the end of the function prologue, and moving instructions that
access the stack via the frame pointer between the instructions
that decrement the stack pointer could result in accessing the
register window save area, which is volatile. */
emit_insn (gen_frame_blockage ());
}
else
{
@ -4324,6 +4341,7 @@ bool
sparc_can_use_return_insn_p (void)
{
return sparc_prologue_data_valid_p
&& num_gfregs == 0
&& (actual_fsize == 0 || !sparc_leaf_function_p);
}
@ -4425,18 +4443,20 @@ output_return (rtx insn)
machinery occupies the delay slot. */
gcc_assert (! final_sequence);
if (! flag_delayed_branch)
fputs ("\tadd\t%fp, %g1, %fp\n", asm_out_file);
if (flag_delayed_branch)
{
if (TARGET_V9)
fputs ("\treturn\t%i7+8\n", asm_out_file);
else
fputs ("\trestore\n\tjmp\t%o7+8\n", asm_out_file);
if (TARGET_V9)
fputs ("\treturn\t%i7+8\n", asm_out_file);
fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file);
}
else
fputs ("\trestore\n\tjmp\t%o7+8\n", asm_out_file);
if (flag_delayed_branch)
fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file);
else
fputs ("\t nop\n", asm_out_file);
{
fputs ("\trestore\n\tadd\t%sp, %g1, %sp\n", asm_out_file);
fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file);
}
}
else if (final_sequence)
{
@ -9104,6 +9124,7 @@ sparc_file_end (void)
void_list_node));
DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
NULL_TREE, void_type_node);
TREE_PUBLIC (decl) = 1;
TREE_STATIC (decl) = 1;
make_decl_one_only (decl, DECL_ASSEMBLER_NAME (decl));
DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
@ -9267,7 +9288,7 @@ sparc_expand_compare_and_swap_12 (rtx result, rtx mem, rtx oldval, rtx newval)
bool
sparc_frame_pointer_required (void)
{
return !(leaf_function_p () && only_leaf_regs_used ());
return !(current_function_is_leaf && only_leaf_regs_used ());
}
/* The way this is structured, we can't eliminate SFP in favor of SP

4
external/gpl3/gcc/dist/gcc/config/sparc/sparc.h vendored
View File

@ -414,6 +414,7 @@ extern enum cmodel sparc_cmodel;
%{mcpu=sparclite:-Asparclite} \
%{mcpu=sparclite86x:-Asparclite} \
%{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
%{mcpu=v8:-Av8} \
%{mv8plus:-Av8plus} \
%{mcpu=v9:-Av9} \
%{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
@ -501,7 +502,8 @@ extern enum cmodel sparc_cmodel;
#define CAN_DEBUG_WITHOUT_FP
/* Option handling. */
#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
sparc_optimization_options ((LEVEL), (SIZE))
#define OVERRIDE_OPTIONS sparc_override_options ()
/* Mask of all CPU selection flags. */

63
external/gpl3/gcc/dist/gcc/config/sparc/sparc.md vendored
View File

@ -28,6 +28,7 @@
[(UNSPEC_MOVE_PIC 0)
(UNSPEC_UPDATE_RETURN 1)
(UNSPEC_LOAD_PCREL_SYM 2)
(UNSPEC_FRAME_BLOCKAGE 3)
(UNSPEC_MOVE_PIC_LABEL 5)
(UNSPEC_SETH44 6)
(UNSPEC_SETM44 7)
@ -2477,11 +2478,9 @@
(match_operand:I 3 "arith10_operand" "")))]
"TARGET_V9 && !(<I:MODE>mode == DImode && TARGET_ARCH32)"
{
enum rtx_code code = GET_CODE (operands[1]);
rtx cc_reg;
if (GET_MODE (XEXP (operands[1], 0)) == DImode
&& ! TARGET_ARCH64)
if (GET_MODE (XEXP (operands[1], 0)) == DImode && !TARGET_ARCH64)
FAIL;
if (GET_MODE (XEXP (operands[1], 0)) == TFmode && !TARGET_HARD_QUAD)
@ -2492,12 +2491,14 @@
if (XEXP (operands[1], 1) == const0_rtx
&& GET_CODE (XEXP (operands[1], 0)) == REG
&& GET_MODE (XEXP (operands[1], 0)) == DImode
&& v9_regcmp_p (code))
&& v9_regcmp_p (GET_CODE (operands[1])))
cc_reg = XEXP (operands[1], 0);
else
cc_reg = gen_compare_reg (operands[1]);
operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
operands[1]
= gen_rtx_fmt_ee (GET_CODE (operands[1]), GET_MODE (cc_reg), cc_reg,
const0_rtx);
})
(define_expand "mov<F:mode>cc"
@ -2507,11 +2508,9 @@
(match_operand:F 3 "register_operand" "")))]
"TARGET_V9 && TARGET_FPU"
{
enum rtx_code code = GET_CODE (operands[1]);
rtx cc_reg;
if (GET_MODE (XEXP (operands[1], 0)) == DImode
&& ! TARGET_ARCH64)
if (GET_MODE (XEXP (operands[1], 0)) == DImode && !TARGET_ARCH64)
FAIL;
if (GET_MODE (XEXP (operands[1], 0)) == TFmode && !TARGET_HARD_QUAD)
@ -2522,12 +2521,14 @@
if (XEXP (operands[1], 1) == const0_rtx
&& GET_CODE (XEXP (operands[1], 0)) == REG
&& GET_MODE (XEXP (operands[1], 0)) == DImode
&& v9_regcmp_p (code))
&& v9_regcmp_p (GET_CODE (operands[1])))
cc_reg = XEXP (operands[1], 0);
else
cc_reg = gen_compare_reg (operands[1]);
operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
operands[1]
= gen_rtx_fmt_ee (GET_CODE (operands[1]), GET_MODE (cc_reg), cc_reg,
const0_rtx);
})
;; Conditional move define_insns
@ -6315,9 +6316,7 @@
(if_then_else (eq_attr "isa" "v9")
(const_int 2)
(const_int 3))
(if_then_else (eq_attr "isa" "v9")
(const_int 3)
(const_int 4)))
(const_int 4))
(eq_attr "empty_delay_slot" "true")
(if_then_else (eq_attr "delayed_branch" "true")
(const_int 2)
@ -6333,6 +6332,25 @@
""
[(set_attr "length" "0")])
;; Do not schedule instructions accessing memory before this point.
(define_expand "frame_blockage"
[(set (match_dup 0)
(unspec:BLK [(match_dup 1)] UNSPEC_FRAME_BLOCKAGE))]
""
{
operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
MEM_VOLATILE_P (operands[0]) = 1;
operands[1] = stack_pointer_rtx;
})
(define_insn "*frame_blockage<P:mode>"
[(set (match_operand:BLK 0 "" "")
(unspec:BLK [(match_operand:P 1 "" "")] UNSPEC_FRAME_BLOCKAGE))]
""
""
[(set_attr "length" "0")])
(define_expand "probe_stack"
[(set (match_operand 0 "memory_operand" "") (const_int 0))]
""
@ -6491,8 +6509,8 @@
(const_int 4)))])
;; For __builtin_setjmp we need to flush register windows iff the function
;; calls alloca as well, because otherwise the register window might be
;; saved after %sp adjustment and thus setjmp would crash
;; calls alloca as well, because otherwise the current register window might
;; be saved after the %sp adjustment and thus setjmp would crash.
(define_expand "builtin_setjmp_setup"
[(match_operand 0 "register_operand" "r")]
""
@ -6531,19 +6549,26 @@
(eq_attr "pic" "true")
(const_int 4)] (const_int 3)))])
;; Pattern for use after a setjmp to store FP and the return register
;; into the stack area.
;; Pattern for use after a setjmp to store registers into the save area.
(define_expand "setjmp"
[(const_int 0)]
""
{
rtx mem;
if (flag_pic)
{
mem = gen_rtx_MEM (Pmode,
plus_constant (stack_pointer_rtx,
SPARC_STACK_BIAS + 7 * UNITS_PER_WORD));
emit_insn (gen_rtx_SET (VOIDmode, mem, pic_offset_table_rtx));
}
mem = gen_rtx_MEM (Pmode,
plus_constant (stack_pointer_rtx,
SPARC_STACK_BIAS + 14 * UNITS_PER_WORD));
emit_insn (gen_rtx_SET (VOIDmode, mem, frame_pointer_rtx));
emit_insn (gen_rtx_SET (VOIDmode, mem, hard_frame_pointer_rtx));
mem = gen_rtx_MEM (Pmode,
plus_constant (stack_pointer_rtx,

4
external/gpl3/gcc/dist/gcc/config/xtensa/linux-unwind.h vendored
View File

@ -1,5 +1,5 @@
/* DWARF2 EH unwinding support for Xtensa.
Copyright (C) 2008, 2009 Free Software Foundation, Inc.
Copyright (C) 2008, 2009, 2012 Free Software Foundation, Inc.
This file is part of GCC.
@ -62,7 +62,7 @@ xtensa_fallback_frame_state (struct _Unwind_Context *context,
struct sigcontext *sc;
struct rt_sigframe {
struct siginfo info;
siginfo_t info;
struct ucontext uc;
} *rt_;

9
external/gpl3/gcc/dist/gcc/convert.c vendored
View File

@ -728,6 +728,15 @@ convert_to_integer (tree type, tree expr)
tree arg0 = get_unwidened (TREE_OPERAND (expr, 0), type);
tree arg1 = get_unwidened (TREE_OPERAND (expr, 1), type);
/* Do not try to narrow operands of pointer subtraction;
that will interfere with other folding. */
if (ex_form == MINUS_EXPR
&& CONVERT_EXPR_P (arg0)
&& CONVERT_EXPR_P (arg1)
&& POINTER_TYPE_P (TREE_TYPE (TREE_OPERAND (arg0, 0)))
&& POINTER_TYPE_P (TREE_TYPE (TREE_OPERAND (arg1, 0))))
break;
if (outprec >= BITS_PER_WORD
|| TRULY_NOOP_TRUNCATION (outprec, inprec)
|| inprec > TYPE_PRECISION (TREE_TYPE (arg0))

80
external/gpl3/gcc/dist/gcc/cp/ChangeLog vendored
View File

@ -1,3 +1,83 @@
2012-07-02 Release Manager
* GCC 4.5.4 released.
2012-01-19 Kai Tietz <ktietz@redhat.com>
PR c++/51344
* decl2.c (save_template_attributes): Use merge_attributes
instead of chaining up via TREE_CHAIN.
2011-12-20 Dodji Seketeli <dodji@redhat.com>
PR debug/49951
* decl.c (cxx_maybe_build_cleanup): Don't set location of the call
to the destructor.
2011-12-13 Jason Merrill <jason@redhat.com>
PR c++/51406
PR c++/51161
* typeck.c (build_static_cast_1): Fix cast of lvalue to
base rvalue reference.
2011-10-19 Jason Merrill <jason@redhat.com>
PR c++/50793
* tree.c (bot_manip): Propagate AGGR_INIT_ZERO_FIRST.
2011-10-13 Jason Merrill <jason@redhat.com>
PR c++/50618
* init.c (expand_aggr_init_1): Don't zero-initialize virtual
bases of a base subobject.
2011-10-11 Janis Johnson <janisjo@codesourcery.com>
PR c++/44473
* mangle.c (write_type): Handle CV qualifiers for decimal classes.
2011-07-19 Jakub Jelinek <jakub@redhat.com>
Backport from mainline
2011-07-07 Jakub Jelinek <jakub@redhat.com>
PR c/49644
* typeck.c (cp_build_binary_op): For MULT_EXPR and TRUNC_DIV_EXPR with
one non-complex and one complex argument, call save_expr on both
operands.
2011-06-23 Jason Merrill <jason@redhat.com>
PR c++/49440
* class.c (set_linkage_according_to_type): Hand off to
determine_visibility.
2011-05-31 Duncan Sands <baldrick@free.fr>
Backported from 4.6 branch
2011-03-09 Martin Jambor <mjambor@suse.cz>
PR tree-optimization/47714
* method.c (use_thunk): Clear addressable flag of thunk arguments.
2011-05-20 Jason Merrill <jason@redhat.com>
PR c++/48873
* tree.c (stabilize_expr): Don't make gratuitous copies of classes.
2011-05-09 Jason Merrill <jason@redhat.com>
PR c++/48936
* decl2.c (mark_used): Instantiate constant variables even
in unevaluated context.
2011-04-27 Jason Merrill <jason@redhat.com>
PR c++/48046
* parser.c (cp_parser_diagnose_invalid_type_name): Commit
to tentative parse sooner.
2011-04-28 Release Manager
* GCC 4.5.3 released.

17
external/gpl3/gcc/dist/gcc/cp/class.c vendored
View File

@ -681,21 +681,10 @@ get_vtable_name (tree type)
the abstract. */
void
set_linkage_according_to_type (tree type, tree decl)
set_linkage_according_to_type (tree type ATTRIBUTE_UNUSED, tree decl)
{
/* If TYPE involves a local class in a function with internal
linkage, then DECL should have internal linkage too. Other local
classes have no linkage -- but if their containing functions
have external linkage, it makes sense for DECL to have external
linkage too. That will allow template definitions to be merged,
for example. */
if (no_linkage_check (type, /*relaxed_p=*/true))
{
TREE_PUBLIC (decl) = 0;
DECL_INTERFACE_KNOWN (decl) = 1;
}
else
TREE_PUBLIC (decl) = 1;
TREE_PUBLIC (decl) = 1;
determine_visibility (decl);
}
/* Create a VAR_DECL for a primary or secondary vtable for CLASS_TYPE.

9
external/gpl3/gcc/dist/gcc/cp/decl.c vendored
View File

@ -12877,8 +12877,17 @@ cxx_maybe_build_cleanup (tree decl)
cleanup = call;
}
/* build_delete sets the location of the destructor call to the
current location, even though the destructor is going to be
called later, at the end of the current scope. This can lead to
a "jumpy" behaviour for users of debuggers when they step around
the end of the block. So let's unset the location of the
destructor call instead. */
if (cleanup != NULL && EXPR_P (cleanup))
SET_EXPR_LOCATION (cleanup, UNKNOWN_LOCATION);
return cleanup;
}
/* When a stmt has been parsed, this function is called. */

28
external/gpl3/gcc/dist/gcc/cp/decl2.c vendored
View File

@ -1189,9 +1189,9 @@ save_template_attributes (tree *attr_p, tree *decl_p)
old_attrs = *q;
/* Place the late attributes at the beginning of the attribute
/* Merge the late attributes at the beginning with the attribute
list. */
TREE_CHAIN (tree_last (late_attrs)) = *q;
late_attrs = merge_attributes (late_attrs, *q);
*q = late_attrs;
if (!DECL_P (*decl_p) && *decl_p == TYPE_MAIN_VARIANT (*decl_p))
@ -3991,8 +3991,6 @@ possibly_inlined_p (tree decl)
void
mark_used (tree decl)
{
HOST_WIDE_INT saved_processing_template_decl = 0;
/* If DECL is a BASELINK for a single function, then treat it just
like the DECL for the function. Otherwise, if the BASELINK is
for an overloaded function, we don't know which function was
@ -4029,9 +4027,6 @@ mark_used (tree decl)
error ("used here");
return;
}
/* If we don't need a value, then we don't need to synthesize DECL. */
if (cp_unevaluated_operand != 0)
return;
/* We can only check DECL_ODR_USED on variables or functions with
DECL_LANG_SPECIFIC set, and these are also the only decls that we
@ -4059,9 +4054,10 @@ mark_used (tree decl)
DECL. However, if DECL is a static data member initialized with
a constant, we need the value right now because a reference to
such a data member is not value-dependent. */
if (TREE_CODE (decl) == VAR_DECL
&& DECL_INITIALIZED_BY_CONSTANT_EXPRESSION_P (decl)
&& DECL_CLASS_SCOPE_P (decl))
if (DECL_INTEGRAL_CONSTANT_VAR_P (decl)
&& !DECL_INITIAL (decl)
&& DECL_LANG_SPECIFIC (decl)
&& DECL_TEMPLATE_INSTANTIATION (decl))
{
/* Don't try to instantiate members of dependent types. We
cannot just use dependent_type_p here because this function
@ -4071,12 +4067,14 @@ mark_used (tree decl)
if (CLASSTYPE_TEMPLATE_INFO ((DECL_CONTEXT (decl)))
&& uses_template_parms (CLASSTYPE_TI_ARGS (DECL_CONTEXT (decl))))
return;
/* Pretend that we are not in a template, even if we are, so
that the static data member initializer will be processed. */
saved_processing_template_decl = processing_template_decl;
processing_template_decl = 0;
instantiate_decl (decl, /*defer_ok=*/false,
/*expl_inst_class_mem_p=*/false);
}
/* If we don't need a value, then we don't need to synthesize DECL. */
if (cp_unevaluated_operand != 0)
return;
if (processing_template_decl)
return;
@ -4149,8 +4147,6 @@ mark_used (tree decl)
need. Therefore, we always try to defer instantiation. */
instantiate_decl (decl, /*defer_ok=*/true,
/*expl_inst_class_mem_p=*/false);
processing_template_decl = saved_processing_template_decl;
}
#include "gt-cp-decl2.h"

7
external/gpl3/gcc/dist/gcc/cp/init.c vendored
View File

@ -1460,7 +1460,12 @@ expand_aggr_init_1 (tree binfo, tree true_exp, tree exp, tree init, int flags,
zero out the object first. */
else if (TYPE_NEEDS_CONSTRUCTING (type))
{
init = build_zero_init (type, NULL_TREE, /*static_storage_p=*/false);
tree field_size = NULL_TREE;
if (exp != true_exp && CLASSTYPE_AS_BASE (type) != type)
/* Don't clobber already initialized virtual bases. */
field_size = TYPE_SIZE (CLASSTYPE_AS_BASE (type));
init = build_zero_init_1 (type, NULL_TREE, /*static_storage_p=*/false,
field_size);
init = build2 (INIT_EXPR, type, exp, init);
finish_expr_stmt (init);
/* And then call the constructor. */

11
external/gpl3/gcc/dist/gcc/cp/mangle.c vendored
View File

@ -1778,11 +1778,6 @@ write_type (tree type)
if (find_substitution (type))
return;
/* According to the C++ ABI, some library classes are passed the
same as the scalar type of their single member and use the same
mangling. */
if (TREE_CODE (type) == RECORD_TYPE && TYPE_TRANSPARENT_AGGR (type))
type = TREE_TYPE (first_field (type));
if (write_CV_qualifiers_for_type (type) > 0)
/* If TYPE was CV-qualified, we just wrote the qualifiers; now
@ -1802,6 +1797,12 @@ write_type (tree type)
/* See through any typedefs. */
type = TYPE_MAIN_VARIANT (type);
/* According to the C++ ABI, some library classes are passed the
same as the scalar type of their single member and use the same
mangling. */
if (TREE_CODE (type) == RECORD_TYPE && TYPE_TRANSPARENT_AGGR (type))
type = TREE_TYPE (first_field (type));
if (TYPE_PTRMEM_P (type))
write_pointer_to_member_type (type);
else

1
external/gpl3/gcc/dist/gcc/cp/method.c vendored
View File

@ -374,6 +374,7 @@ use_thunk (tree thunk_fndecl, bool emit_p)
DECL_CONTEXT (x) = thunk_fndecl;
SET_DECL_RTL (x, NULL_RTX);
DECL_HAS_VALUE_EXPR_P (x) = 0;
TREE_ADDRESSABLE (x) = 0;
t = x;
}
a = nreverse (t);

2
external/gpl3/gcc/dist/gcc/cp/parser.c vendored
View File

@ -2333,6 +2333,7 @@ cp_parser_diagnose_invalid_type_name (cp_parser *parser,
location_t location)
{
tree decl, old_scope;
cp_parser_commit_to_tentative_parse (parser);
/* Try to lookup the identifier. */
old_scope = parser->scope;
parser->scope = scope;
@ -2423,7 +2424,6 @@ cp_parser_diagnose_invalid_type_name (cp_parser *parser,
else
gcc_unreachable ();
}
cp_parser_commit_to_tentative_parse (parser);
}
/* Check for a common situation where a type-name should be present,

9
external/gpl3/gcc/dist/gcc/cp/tree.c vendored
View File

@ -1732,7 +1732,11 @@ bot_manip (tree* tp, int* walk_subtrees, void* data)
tree u;
if (TREE_CODE (TREE_OPERAND (t, 1)) == AGGR_INIT_EXPR)
u = build_cplus_new (TREE_TYPE (t), TREE_OPERAND (t, 1));
{
u = build_cplus_new (TREE_TYPE (t), TREE_OPERAND (t, 1));
if (AGGR_INIT_ZERO_FIRST (TREE_OPERAND (t, 1)))
AGGR_INIT_ZERO_FIRST (TREE_OPERAND (u, 1)) = true;
}
else
u = build_target_expr_with_type (TREE_OPERAND (t, 1), TREE_TYPE (t));
@ -2954,7 +2958,8 @@ stabilize_expr (tree exp, tree* initp)
if (!TREE_SIDE_EFFECTS (exp))
init_expr = NULL_TREE;
else if (!real_lvalue_p (exp)
|| !TYPE_NEEDS_CONSTRUCTING (TREE_TYPE (exp)))
|| (!TYPE_NEEDS_CONSTRUCTING (TREE_TYPE (exp))
&& !TYPE_HAS_NONTRIVIAL_DESTRUCTOR (TREE_TYPE (exp))))
{
init_expr = get_target_expr (exp);
exp = TARGET_EXPR_SLOT (init_expr);

16
external/gpl3/gcc/dist/gcc/cp/typeck.c vendored
View File

@ -4297,6 +4297,7 @@ cp_build_binary_op (location_t location,
{
case MULT_EXPR:
case TRUNC_DIV_EXPR:
op1 = save_expr (op1);
imag = build2 (resultcode, real_type, imag, op1);
/* Fall through. */
case PLUS_EXPR:
@ -4315,6 +4316,7 @@ cp_build_binary_op (location_t location,
switch (code)
{
case MULT_EXPR:
op0 = save_expr (op0);
imag = build2 (resultcode, real_type, op0, imag);
/* Fall through. */
case PLUS_EXPR:
@ -5672,8 +5674,18 @@ build_static_cast_1 (tree type, tree expr, bool c_cast_p,
&& reference_related_p (TREE_TYPE (type), intype)
&& (c_cast_p || at_least_as_qualified_p (TREE_TYPE (type), intype)))
{
expr = build_typed_address (expr, type);
return convert_from_reference (expr);
/* Handle the lvalue case here by casting to lvalue reference and
then changing it to an rvalue reference. Casting an xvalue to
rvalue reference will be handled by the main code path. */
tree lref = cp_build_reference_type (TREE_TYPE (type), false);
result = (perform_direct_initialization_if_possible
(lref, expr, c_cast_p, complain));
result = cp_fold_convert (type, result);
/* Make sure we don't fold back down to a named rvalue reference,
because that would be an lvalue. */
if (DECL_P (result))
result = build1 (NON_LVALUE_EXPR, type, result);
return convert_from_reference (result);
}
orig = expr;

33
external/gpl3/gcc/dist/gcc/df-problems.c vendored
View File

@ -3748,9 +3748,22 @@ df_simulate_find_defs (rtx insn, bitmap defs)
for (def_rec = DF_INSN_UID_DEFS (uid); *def_rec; def_rec++)
{
df_ref def = *def_rec;
/* If the def is to only part of the reg, it does
not kill the other defs that reach here. */
if (!(DF_REF_FLAGS (def) & (DF_REF_PARTIAL | DF_REF_CONDITIONAL)))
bitmap_set_bit (defs, DF_REF_REGNO (def));
}
}
/* Find the set of real DEFs, which are not clobbers, for INSN. */
void
df_simulate_find_noclobber_defs (rtx insn, bitmap defs)
{
df_ref *def_rec;
unsigned int uid = INSN_UID (insn);
for (def_rec = DF_INSN_UID_DEFS (uid); *def_rec; def_rec++)
{
df_ref def = *def_rec;
if (!(DF_REF_FLAGS (def) & (DF_REF_MUST_CLOBBER | DF_REF_MAY_CLOBBER)))
bitmap_set_bit (defs, DF_REF_REGNO (def));
}
}
@ -3903,13 +3916,9 @@ df_simulate_finalize_backwards (basic_block bb, bitmap live)
the block, starting with the first one.
----------------------------------------------------------------------------*/
/* Apply the artificial uses and defs at the top of BB in a forwards
direction. ??? This is wrong; defs mark the point where a pseudo
becomes live when scanning forwards (unless a def is unused). Since
there are no REG_UNUSED notes for artificial defs, passes that
require artificial defs probably should not call this function
unless (as is the case for fwprop) they are correct when liveness
bitmaps are *under*estimated. */
/* Initialize the LIVE bitmap, which should be copied from DF_LIVE_IN or
DF_LR_IN for basic block BB, for forward scanning by marking artificial
defs live. */
void
df_simulate_initialize_forwards (basic_block bb, bitmap live)
@ -3921,7 +3930,7 @@ df_simulate_initialize_forwards (basic_block bb, bitmap live)
{
df_ref def = *def_rec;
if (DF_REF_FLAGS (def) & DF_REF_AT_TOP)
bitmap_clear_bit (live, DF_REF_REGNO (def));
bitmap_set_bit (live, DF_REF_REGNO (def));
}
}
@ -3942,7 +3951,7 @@ df_simulate_one_insn_forwards (basic_block bb, rtx insn, bitmap live)
while here the scan is performed forwards! So, first assume that the
def is live, and if this is not true REG_UNUSED notes will rectify the
situation. */
df_simulate_find_defs (insn, live);
df_simulate_find_noclobber_defs (insn, live);
/* Clear all of the registers that go dead. */
for (link = REG_NOTES (insn); link; link = XEXP (link, 1))

3
external/gpl3/gcc/dist/gcc/df.h vendored
View File

@ -51,7 +51,7 @@ union df_ref_d;
#define DF_RD 3 /* Reaching Defs. */
#define DF_CHAIN 4 /* Def-Use and/or Use-Def Chains. */
#define DF_BYTE_LR 5 /* Subreg tracking lr. */
#define DF_NOTE 6 /* REG_DEF and REG_UNUSED notes. */
#define DF_NOTE 6 /* REG_DEAD and REG_UNUSED notes. */
#define DF_MD 7 /* Multiple Definitions. */
#define DF_LAST_PROBLEM_PLUS1 (DF_MD + 1)
@ -978,6 +978,7 @@ extern void df_note_add_problem (void);
extern void df_md_add_problem (void);
extern void df_md_simulate_artificial_defs_at_top (basic_block, bitmap);
extern void df_md_simulate_one_insn (basic_block, rtx, bitmap);
extern void df_simulate_find_noclobber_defs (rtx, bitmap);
extern void df_simulate_find_defs (rtx, bitmap);
extern void df_simulate_defs (rtx, bitmap);
extern void df_simulate_uses (rtx, bitmap);

2
external/gpl3/gcc/dist/gcc/doc/aot-compile.1 vendored
View File

@ -132,7 +132,7 @@
.\" ========================================================================
.\"
.IX Title "AOT-COMPILE 1"
.TH AOT-COMPILE 1 "2011-04-28" "gcc-4.5.3" "GNU"
.TH AOT-COMPILE 1 "2012-07-02" "gcc-4.5.4" "GNU"
.\" For nroff, turn off justification. Always turn off hyphenation; it makes
.\" way too many mistakes in technical documents.
.if n .ad l

2
external/gpl3/gcc/dist/gcc/doc/cpp.1 vendored
View File

@ -132,7 +132,7 @@
.\" ========================================================================
.\"
.IX Title "CPP 1"
.TH CPP 1 "2011-04-28" "gcc-4.5.3" "GNU"
.TH CPP 1 "2012-07-02" "gcc-4.5.4" "GNU"
.\" For nroff, turn off justification. Always turn off hyphenation; it makes
.\" way too many mistakes in technical documents.
.if n .ad l

2
external/gpl3/gcc/dist/gcc/doc/cpp.info vendored
View File

@ -1,5 +1,5 @@
This is doc/cpp.info, produced by makeinfo version 4.12 from
/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/doc/cpp.texi.
/space/rguenther/gcc-4.5.4/gcc-4.5.4/gcc/doc/cpp.texi.
Copyright (C) 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,

2
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@ -1,5 +1,5 @@
This is doc/cppinternals.info, produced by makeinfo version 4.12 from
/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/doc/cppinternals.texi.
/space/rguenther/gcc-4.5.4/gcc-4.5.4/gcc/doc/cppinternals.texi.
INFO-DIR-SECTION Software development
START-INFO-DIR-ENTRY

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@ -132,7 +132,7 @@
.\" ========================================================================
.\"
.IX Title "FSF-FUNDING 7"
.TH FSF-FUNDING 7 "2011-04-28" "gcc-4.5.3" "GNU"
.TH FSF-FUNDING 7 "2012-07-02" "gcc-4.5.4" "GNU"
.\" For nroff, turn off justification. Always turn off hyphenation; it makes
.\" way too many mistakes in technical documents.
.if n .ad l

2
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@ -132,7 +132,7 @@
.\" ========================================================================
.\"
.IX Title "GCC 1"
.TH GCC 1 "2011-04-28" "gcc-4.5.3" "GNU"
.TH GCC 1 "2012-07-02" "gcc-4.5.4" "GNU"
.\" For nroff, turn off justification. Always turn off hyphenation; it makes
.\" way too many mistakes in technical documents.
.if n .ad l

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@ -132,7 +132,7 @@
.\" ========================================================================
.\"
.IX Title "GC-ANALYZE 1"
.TH GC-ANALYZE 1 "2011-04-28" "gcc-4.5.3" "GNU"
.TH GC-ANALYZE 1 "2012-07-02" "gcc-4.5.4" "GNU"
.\" For nroff, turn off justification. Always turn off hyphenation; it makes
.\" way too many mistakes in technical documents.
.if n .ad l

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@ -132,7 +132,7 @@
.\" ========================================================================
.\"
.IX Title "GCC 1"
.TH GCC 1 "2011-04-28" "gcc-4.5.3" "GNU"
.TH GCC 1 "2012-07-02" "gcc-4.5.4" "GNU"
.\" For nroff, turn off justification. Always turn off hyphenation; it makes
.\" way too many mistakes in technical documents.
.if n .ad l

4
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@ -1,5 +1,5 @@
This is doc/gcc.info, produced by makeinfo version 4.12 from
/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/doc/gcc.texi.
/space/rguenther/gcc-4.5.4/gcc-4.5.4/gcc/doc/gcc.texi.
Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 Free
@ -61,7 +61,7 @@ Introduction
This manual documents how to use the GNU compilers, as well as their
features and incompatibilities, and how to report bugs. It corresponds
to the compilers (GCC) version 4.5.3. The internals of the GNU
to the compilers (GCC) version 4.5.4. The internals of the GNU
compilers, including how to port them to new targets and some
information about how to write front ends for new languages, are
documented in a separate manual. *Note Introduction: (gccint)Top.

154
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@ -1,5 +1,5 @@
This is doc/gccinstall.info, produced by makeinfo version 4.12 from
/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/doc/install.texi.
/space/rguenther/gcc-4.5.4/gcc-4.5.4/gcc/doc/install.texi.
Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
@ -990,7 +990,7 @@ option.
Division by zero checks use the break instruction.
`--with-llsc'
On MIPS targets, make `-mllsc' the default when no `-mno-lsc'
On MIPS targets, make `-mllsc' the default when no `-mno-llsc'
option is passed. This is the default for Linux-based targets, as
the kernel will emulate them if the ISA does not provide them.
@ -4454,80 +4454,80 @@ Node: Configuration15661
Ref: with-gnu-as29803
Ref: with-as30701
Ref: with-gnu-ld32114
Node: Building75589
Node: Testing90900
Node: Final install98680
Node: Binaries103910
Node: Specific105414
Ref: alpha-x-x105920
Ref: alpha-dec-osf106409
Ref: arc-x-elf108710
Ref: arm-x-elf108810
Ref: avr109030
Ref: bfin109672
Ref: cris109914
Ref: crx110730
Ref: dos111393
Ref: x-x-freebsd111716
Ref: h8300-hms113529
Ref: hppa-hp-hpux113881
Ref: hppa-hp-hpux10116252
Ref: hppa-hp-hpux11116665
Ref: x-x-linux-gnu122324
Ref: ix86-x-linux122517
Ref: ix86-x-solaris289122830
Ref: ix86-x-solaris210123676
Ref: ia64-x-linux124906
Ref: ia64-x-hpux125676
Ref: x-ibm-aix126231
Ref: iq2000-x-elf132490
Ref: lm32-x-elf132630
Ref: lm32-x-uclinux132734
Ref: m32c-x-elf132862
Ref: m32r-x-elf132964
Ref: m6811-elf133066
Ref: m6812-elf133216
Ref: m68k-x-x133366
Ref: m68k-x-uclinux134338
Ref: mep-x-elf134701
Ref: mips-x-x134811
Ref: mips-sgi-irix5137488
Ref: mips-sgi-irix6138754
Ref: moxie-x-elf142085
Ref: powerpc-x-x142205
Ref: powerpc-x-darwin142410
Ref: powerpc-x-elf142957
Ref: powerpc-x-linux-gnu143042
Ref: powerpc-x-netbsd143137
Ref: powerpc-x-eabisim143225
Ref: powerpc-x-eabi143351
Ref: powerpcle-x-elf143427
Ref: powerpcle-x-eabisim143519
Ref: powerpcle-x-eabi143652
Ref: rx-x-elf143735
Ref: s390-x-linux143934
Ref: s390x-x-linux144006
Ref: s390x-ibm-tpf144093
Ref: x-x-solaris2144224
Ref: sparc-sun-solaris2148036
Ref: sparc-sun-solaris27150762
Ref: sparc-sun-solaris210153320
Ref: sparc-x-linux153696
Ref: sparc64-x-solaris2153921
Ref: sparcv9-x-solaris2154563
Ref: x-x-vxworks154650
Ref: x86-64-x-x156172
Ref: xtensa-x-elf156500
Ref: xtensa-x-linux157171
Ref: windows157512
Ref: x-x-cygwin159469
Ref: x-x-interix160022
Ref: x-x-mingw32160388
Ref: older160614
Ref: elf162731
Node: Old162989
Node: Configurations166126
Node: GNU Free Documentation License170108
Node: Concept Index192524
Node: Building75590
Node: Testing90901
Node: Final install98681
Node: Binaries103911
Node: Specific105415
Ref: alpha-x-x105921
Ref: alpha-dec-osf106410
Ref: arc-x-elf108711
Ref: arm-x-elf108811
Ref: avr109031
Ref: bfin109673
Ref: cris109915
Ref: crx110731
Ref: dos111394
Ref: x-x-freebsd111717
Ref: h8300-hms113530
Ref: hppa-hp-hpux113882
Ref: hppa-hp-hpux10116253
Ref: hppa-hp-hpux11116666
Ref: x-x-linux-gnu122325
Ref: ix86-x-linux122518
Ref: ix86-x-solaris289122831
Ref: ix86-x-solaris210123677
Ref: ia64-x-linux124907
Ref: ia64-x-hpux125677
Ref: x-ibm-aix126232
Ref: iq2000-x-elf132491
Ref: lm32-x-elf132631
Ref: lm32-x-uclinux132735
Ref: m32c-x-elf132863
Ref: m32r-x-elf132965
Ref: m6811-elf133067
Ref: m6812-elf133217
Ref: m68k-x-x133367
Ref: m68k-x-uclinux134339
Ref: mep-x-elf134702
Ref: mips-x-x134812
Ref: mips-sgi-irix5137489
Ref: mips-sgi-irix6138755
Ref: moxie-x-elf142086
Ref: powerpc-x-x142206
Ref: powerpc-x-darwin142411
Ref: powerpc-x-elf142958
Ref: powerpc-x-linux-gnu143043
Ref: powerpc-x-netbsd143138
Ref: powerpc-x-eabisim143226
Ref: powerpc-x-eabi143352
Ref: powerpcle-x-elf143428
Ref: powerpcle-x-eabisim143520
Ref: powerpcle-x-eabi143653
Ref: rx-x-elf143736
Ref: s390-x-linux143935
Ref: s390x-x-linux144007
Ref: s390x-ibm-tpf144094
Ref: x-x-solaris2144225
Ref: sparc-sun-solaris2148037
Ref: sparc-sun-solaris27150763
Ref: sparc-sun-solaris210153321
Ref: sparc-x-linux153697
Ref: sparc64-x-solaris2153922
Ref: sparcv9-x-solaris2154564
Ref: x-x-vxworks154651
Ref: x86-64-x-x156173
Ref: xtensa-x-elf156501
Ref: xtensa-x-linux157172
Ref: windows157513
Ref: x-x-cygwin159470
Ref: x-x-interix160023
Ref: x-x-mingw32160389
Ref: older160615
Ref: elf162732
Node: Old162990
Node: Configurations166127
Node: GNU Free Documentation License170109
Node: Concept Index192525

End Tag Table

456
external/gpl3/gcc/dist/gcc/doc/gccint.info vendored
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@ -1,5 +1,5 @@
This is doc/gccint.info, produced by makeinfo version 4.12 from
/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/doc/gccint.texi.
/space/rguenther/gcc-4.5.4/gcc-4.5.4/gcc/doc/gccint.texi.
Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010 Free
@ -61,7 +61,7 @@ Introduction
This manual documents the internals of the GNU compilers, including how
to port them to new targets and some information about how to write
front ends for new languages. It corresponds to the compilers
(GCC) version 4.5.3. The use of the GNU compilers is documented in a
(GCC) version 4.5.4. The use of the GNU compilers is documented in a
separate manual. *Note Introduction: (gcc)Top.
This manual is mainly a reference manual rather than a tutorial. It
@ -21834,9 +21834,10 @@ pattern to accomplish a certain task.
beginning of each string. The instruction is not allowed to
prefetch more than one byte at a time since either string may end
in the first byte and reading past that may access an invalid page
or segment and cause a fault. The effect of the instruction is to
store a value in operand 0 whose sign indicates the result of the
comparison.
or segment and cause a fault. The comparison terminates early if
the fetched bytes are different or if they are equal to zero. The
effect of the instruction is to store a value in operand 0 whose
sign indicates the result of the comparison.
`cmpstrM'
String compare instruction, without known maximum length. Operand
@ -21854,17 +21855,20 @@ pattern to accomplish a certain task.
instruction is not allowed to prefetch more than one byte at a
time since either string may end in the first byte and reading
past that may access an invalid page or segment and cause a fault.
The effect of the instruction is to store a value in operand 0
whose sign indicates the result of the comparison.
The comparison will terminate when the fetched bytes are different
or if they are equal to zero. The effect of the instruction is to
store a value in operand 0 whose sign indicates the result of the
comparison.
`cmpmemM'
Block compare instruction, with five operands like the operands of
`cmpstrM'. The two memory blocks specified are compared byte by
byte in lexicographic order starting at the beginning of each
block. Unlike `cmpstrM' the instruction can prefetch any bytes in
the two memory blocks. The effect of the instruction is to store
a value in operand 0 whose sign indicates the result of the
comparison.
the two memory blocks. Also unlike `cmpstrM' the comparison will
not stop if both bytes are zero. The effect of the instruction is
to store a value in operand 0 whose sign indicates the result of
the comparison.
`strlenM'
Compute the length of a string, with three operands. Operand 0 is
@ -42401,7 +42405,7 @@ Concept Index
(line 6)
* ADDITIONAL_REGISTER_NAMES: Instruction Output. (line 15)
* addM3 instruction pattern: Standard Names. (line 216)
* addMODEcc instruction pattern: Standard Names. (line 886)
* addMODEcc instruction pattern: Standard Names. (line 890)
* addr_diff_vec: Side Effects. (line 302)
* addr_diff_vec, length of: Insn Lengths. (line 26)
* ADDR_EXPR: Storage References. (line 6)
@ -42418,7 +42422,7 @@ Concept Index
* alias: Alias analysis. (line 6)
* ALL_COP_ADDITIONAL_REGISTER_NAMES: MIPS Coprocessors. (line 32)
* ALL_REGS: Register Classes. (line 17)
* allocate_stack instruction pattern: Standard Names. (line 1186)
* allocate_stack instruction pattern: Standard Names. (line 1190)
* alternate entry points: Insns. (line 140)
* anchored addresses: Anchored Addresses. (line 6)
* and: Arithmetic. (line 153)
@ -42603,7 +42607,7 @@ Concept Index
* BLOCK_FOR_INSN, bb_for_stmt: Maintaining the CFG.
(line 40)
* BLOCK_REG_PADDING: Register Arguments. (line 228)
* blockage instruction pattern: Standard Names. (line 1376)
* blockage instruction pattern: Standard Names. (line 1380)
* Blocks: Blocks. (line 6)
* bool: Misc. (line 876)
* BOOL_TYPE_SIZE: Type Layout. (line 44)
@ -42650,10 +42654,10 @@ Concept Index
(line 21)
* build6: Macros and Functions.
(line 22)
* builtin_longjmp instruction pattern: Standard Names. (line 1279)
* builtin_longjmp instruction pattern: Standard Names. (line 1283)
* builtin_setjmp_receiver instruction pattern: Standard Names.
(line 1269)
* builtin_setjmp_setup instruction pattern: Standard Names. (line 1258)
(line 1273)
* builtin_setjmp_setup instruction pattern: Standard Names. (line 1262)
* byte_mode: Machine Modes. (line 336)
* BYTES_BIG_ENDIAN: Storage Layout. (line 24)
* BYTES_BIG_ENDIAN, effect on subreg: Regs and Memory. (line 221)
@ -42664,7 +42668,7 @@ Concept Index
* c_register_pragma_with_expansion: Misc. (line 406)
* call <1>: Side Effects. (line 86)
* call: Flags. (line 239)
* call instruction pattern: Standard Names. (line 933)
* call instruction pattern: Standard Names. (line 937)
* call usage: Calls. (line 10)
* call, in call_insn: Flags. (line 33)
* call, in mem: Flags. (line 99)
@ -42683,13 +42687,13 @@ Concept Index
* call_insn and /u or /i: Flags. (line 29)
* call_insn and /v: Flags. (line 44)
* CALL_INSN_FUNCTION_USAGE: Insns. (line 101)
* call_pop instruction pattern: Standard Names. (line 961)
* call_pop instruction pattern: Standard Names. (line 965)
* CALL_POPS_ARGS: Stack Arguments. (line 130)
* CALL_REALLY_USED_REGISTERS: Register Basics. (line 46)
* CALL_USED_REGISTERS: Register Basics. (line 35)
* call_used_regs: Register Basics. (line 59)
* call_value instruction pattern: Standard Names. (line 953)
* call_value_pop instruction pattern: Standard Names. (line 961)
* call_value instruction pattern: Standard Names. (line 957)
* call_value_pop instruction pattern: Standard Names. (line 965)
* CALLER_SAVE_PROFITABLE: Caller Saves. (line 11)
* calling conventions: Stack and Calling. (line 6)
* calling functions in RTL: Calls. (line 6)
@ -42705,13 +42709,13 @@ Concept Index
* CANONICALIZE_COMPARISON: MODE_CC Condition Codes.
(line 55)
* canonicalize_funcptr_for_compare instruction pattern: Standard Names.
(line 1117)
(line 1121)
* CASE_USE_BIT_TESTS: Misc. (line 54)
* CASE_VECTOR_MODE: Misc. (line 27)
* CASE_VECTOR_PC_RELATIVE: Misc. (line 40)
* CASE_VECTOR_SHORTEN_MODE: Misc. (line 31)
* casesi instruction pattern: Standard Names. (line 1041)
* cbranchMODE4 instruction pattern: Standard Names. (line 922)
* casesi instruction pattern: Standard Names. (line 1045)
* cbranchMODE4 instruction pattern: Standard Names. (line 926)
* cc0 <1>: CC0 Condition Codes.
(line 6)
* cc0: Regs and Memory. (line 307)
@ -42745,7 +42749,7 @@ Concept Index
* change_address: Standard Names. (line 47)
* char: GIMPLE_ASM. (line 53)
* CHAR_TYPE_SIZE: Type Layout. (line 39)
* check_stack instruction pattern: Standard Names. (line 1204)
* check_stack instruction pattern: Standard Names. (line 1208)
* CHImode: Machine Modes. (line 202)
* class definitions, register: Register Classes. (line 6)
* class preference constraints: Class Preferences. (line 6)
@ -42764,15 +42768,15 @@ Concept Index
* CLEANUP_STMT: Statements for C++. (line 6)
* Cleanups: Cleanups. (line 6)
* CLEAR_BY_PIECES_P: Costs. (line 136)
* clear_cache instruction pattern: Standard Names. (line 1520)
* clear_cache instruction pattern: Standard Names. (line 1524)
* CLEAR_INSN_CACHE: Trampolines. (line 99)
* CLEAR_RATIO: Costs. (line 124)
* clobber: Side Effects. (line 100)
* clz: Arithmetic. (line 212)
* CLZ_DEFINED_VALUE_AT_ZERO: Misc. (line 319)
* clzM2 instruction pattern: Standard Names. (line 621)
* cmpmemM instruction pattern: Standard Names. (line 751)
* cmpstrM instruction pattern: Standard Names. (line 732)
* cmpmemM instruction pattern: Standard Names. (line 754)
* cmpstrM instruction pattern: Standard Names. (line 733)
* cmpstrnM instruction pattern: Standard Names. (line 720)
* code generation RTL sequences: Expander Definitions.
(line 6)
@ -42926,9 +42930,9 @@ Concept Index
* CRTSTUFF_T_CFLAGS: Target Fragment. (line 35)
* CRTSTUFF_T_CFLAGS_S: Target Fragment. (line 39)
* CSImode: Machine Modes. (line 202)
* cstoreMODE4 instruction pattern: Standard Names. (line 893)
* cstoreMODE4 instruction pattern: Standard Names. (line 897)
* CTImode: Machine Modes. (line 202)
* ctrapMM4 instruction pattern: Standard Names. (line 1345)
* ctrapMM4 instruction pattern: Standard Names. (line 1349)
* ctz: Arithmetic. (line 220)
* CTZ_DEFINED_VALUE_AT_ZERO: Misc. (line 320)
* ctzM2 instruction pattern: Standard Names. (line 630)
@ -43052,7 +43056,7 @@ Concept Index
* declarations, RTL: RTL Declarations. (line 6)
* DECLARE_LIBRARY_RENAMES: Library Calls. (line 9)
* decrement_and_branch_until_zero instruction pattern: Standard Names.
(line 1079)
(line 1083)
* def_optype_d: Manipulating GIMPLE statements.
(line 94)
* default: GTY Options. (line 81)
@ -43140,8 +43144,8 @@ Concept Index
* DO_COND: Statements for C++. (line 6)
* DO_STMT: Statements for C++. (line 6)
* DOLLARS_IN_IDENTIFIERS: Misc. (line 491)
* doloop_begin instruction pattern: Standard Names. (line 1110)
* doloop_end instruction pattern: Standard Names. (line 1089)
* doloop_begin instruction pattern: Standard Names. (line 1114)
* doloop_end instruction pattern: Standard Names. (line 1093)
* DONE: Expander Definitions.
(line 74)
* DONT_USE_BUILTIN_SETJMP: Exception Region Output.
@ -43182,7 +43186,7 @@ Concept Index
(line 20)
* EH_FRAME_SECTION_NAME: Exception Region Output.
(line 10)
* eh_return instruction pattern: Standard Names. (line 1285)
* eh_return instruction pattern: Standard Names. (line 1289)
* EH_RETURN_DATA_REGNO: Exception Handling. (line 7)
* EH_RETURN_HANDLER_RTX: Exception Handling. (line 39)
* EH_RETURN_STACKADJ_RTX: Exception Handling. (line 22)
@ -43217,7 +43221,7 @@ Concept Index
* enum reg_class: Register Classes. (line 65)
* ENUMERAL_TYPE: Types. (line 6)
* epilogue: Function Entry. (line 6)
* epilogue instruction pattern: Standard Names. (line 1317)
* epilogue instruction pattern: Standard Names. (line 1321)
* EPILOGUE_USES: Function Entry. (line 152)
* eq: Comparisons. (line 52)
* eq and attributes: Expressions. (line 64)
@ -43231,7 +43235,7 @@ Concept Index
* examining SSA_NAMEs: SSA. (line 218)
* exception handling <1>: Exception Handling. (line 6)
* exception handling: Edges. (line 96)
* exception_receiver instruction pattern: Standard Names. (line 1249)
* exception_receiver instruction pattern: Standard Names. (line 1253)
* exclamation point: Multi-Alternative. (line 47)
* exclusion_set: Processor pipeline description.
(line 220)
@ -43251,15 +43255,15 @@ Concept Index
* EXPR_STMT_EXPR: Statements for C++. (line 6)
* expression: Expression trees. (line 6)
* expression codes: RTL Objects. (line 47)
* extendMN2 instruction pattern: Standard Names. (line 808)
* extendMN2 instruction pattern: Standard Names. (line 812)
* extensible constraints: Simple Constraints. (line 163)
* EXTRA_ADDRESS_CONSTRAINT: Old Constraints. (line 123)
* EXTRA_CONSTRAINT: Old Constraints. (line 74)
* EXTRA_CONSTRAINT_STR: Old Constraints. (line 95)
* EXTRA_MEMORY_CONSTRAINT: Old Constraints. (line 100)
* EXTRA_SPECS: Driver. (line 245)
* extv instruction pattern: Standard Names. (line 844)
* extzv instruction pattern: Standard Names. (line 859)
* extv instruction pattern: Standard Names. (line 848)
* extzv instruction pattern: Standard Names. (line 863)
* F in constraint: Simple Constraints. (line 84)
* FAIL: Expander Definitions.
(line 80)
@ -43295,7 +43299,7 @@ Concept Index
* fix: Conversions. (line 66)
* FIX_TRUNC_EXPR: Unary and Binary Expressions.
(line 6)
* fix_truncMN2 instruction pattern: Standard Names. (line 795)
* fix_truncMN2 instruction pattern: Standard Names. (line 799)
* fixed register: Register Basics. (line 15)
* fixed-point fractional library: Fixed-point fractional library routines.
(line 6)
@ -43306,10 +43310,10 @@ Concept Index
* FIXED_POINT_TYPE: Types. (line 6)
* FIXED_REGISTERS: Register Basics. (line 15)
* fixed_regs: Register Basics. (line 59)
* fixMN2 instruction pattern: Standard Names. (line 775)
* fixMN2 instruction pattern: Standard Names. (line 779)
* FIXUNS_TRUNC_LIKE_FIX_TRUNC: Misc. (line 100)
* fixuns_truncMN2 instruction pattern: Standard Names. (line 799)
* fixunsMN2 instruction pattern: Standard Names. (line 784)
* fixuns_truncMN2 instruction pattern: Standard Names. (line 803)
* fixunsMN2 instruction pattern: Standard Names. (line 788)
* flags in RTL expression: Flags. (line 6)
* float: Conversions. (line 58)
* FLOAT_EXPR: Unary and Binary Expressions.
@ -43326,8 +43330,8 @@ Concept Index
* Floating Point Emulation: Target Fragment. (line 15)
* floating point emulation library, US Software GOFAST: Library Calls.
(line 44)
* floatMN2 instruction pattern: Standard Names. (line 767)
* floatunsMN2 instruction pattern: Standard Names. (line 771)
* floatMN2 instruction pattern: Standard Names. (line 771)
* floatunsMN2 instruction pattern: Standard Names. (line 775)
* FLOOR_DIV_EXPR: Unary and Binary Expressions.
(line 6)
* FLOOR_MOD_EXPR: Unary and Binary Expressions.
@ -43347,8 +43351,8 @@ Concept Index
* FRACT_TYPE_SIZE: Type Layout. (line 68)
* fractional types: Fixed-point fractional library routines.
(line 6)
* fractMN2 instruction pattern: Standard Names. (line 817)
* fractunsMN2 instruction pattern: Standard Names. (line 832)
* fractMN2 instruction pattern: Standard Names. (line 821)
* fractunsMN2 instruction pattern: Standard Names. (line 836)
* frame layout: Frame Layout. (line 6)
* FRAME_ADDR_RTX: Frame Layout. (line 116)
* FRAME_GROWS_DOWNWARD: Frame Layout. (line 31)
@ -43368,7 +43372,7 @@ Concept Index
* frame_related, in symbol_ref: Flags. (line 183)
* frequency, count, BB_FREQ_BASE: Profile information.
(line 30)
* ftruncM2 instruction pattern: Standard Names. (line 790)
* ftruncM2 instruction pattern: Standard Names. (line 794)
* function <1>: Functions for C++. (line 6)
* function: Functions. (line 6)
* function call conventions: Interface. (line 6)
@ -43950,7 +43954,7 @@ Concept Index
* INCOMING_RETURN_ADDR_RTX: Frame Layout. (line 139)
* INCOMING_STACK_BOUNDARY: Storage Layout. (line 166)
* INDEX_REG_CLASS: Register Classes. (line 134)
* indirect_jump instruction pattern: Standard Names. (line 1037)
* indirect_jump instruction pattern: Standard Names. (line 1041)
* indirect_operand: Machine-Independent Predicates.
(line 71)
* INDIRECT_REF: Storage References. (line 6)
@ -44005,7 +44009,7 @@ Concept Index
(line 6)
* instruction patterns: Patterns. (line 6)
* instruction splitting: Insn Splitting. (line 6)
* insv instruction pattern: Standard Names. (line 862)
* insv instruction pattern: Standard Names. (line 866)
* int: Manipulating GIMPLE statements.
(line 66)
* INT16_TYPE: Type Layout. (line 237)
@ -44048,7 +44052,7 @@ Concept Index
* IV analysis on GIMPLE: Scalar evolutions. (line 6)
* IV analysis on RTL: loop-iv. (line 6)
* jump: Flags. (line 314)
* jump instruction pattern: Standard Names. (line 928)
* jump instruction pattern: Standard Names. (line 932)
* jump instruction patterns: Jump Patterns. (line 6)
* jump instructions and set: Side Effects. (line 56)
* jump, in call_insn: Flags. (line 179)
@ -44101,7 +44105,7 @@ Concept Index
* LE_EXPR: Unary and Binary Expressions.
(line 6)
* leaf functions: Leaf Functions. (line 6)
* leaf_function_p: Standard Names. (line 999)
* leaf_function_p: Standard Names. (line 1003)
* LEAF_REG_REMAP: Leaf Functions. (line 39)
* LEAF_REGISTERS: Leaf Functions. (line 25)
* left rotate: Arithmetic. (line 190)
@ -44277,7 +44281,7 @@ Concept Index
* memory model: Memory model. (line 6)
* memory reference, nonoffsettable: Simple Constraints. (line 246)
* memory references in constraints: Simple Constraints. (line 17)
* memory_barrier instruction pattern: Standard Names. (line 1381)
* memory_barrier instruction pattern: Standard Names. (line 1385)
* MEMORY_MOVE_COST: Costs. (line 29)
* memory_operand: Machine-Independent Predicates.
(line 58)
@ -44337,7 +44341,7 @@ Concept Index
* movM instruction pattern: Standard Names. (line 11)
* movmemM instruction pattern: Standard Names. (line 654)
* movmisalignM instruction pattern: Standard Names. (line 126)
* movMODEcc instruction pattern: Standard Names. (line 873)
* movMODEcc instruction pattern: Standard Names. (line 877)
* movstr instruction pattern: Standard Names. (line 689)
* movstrictM instruction pattern: Standard Names. (line 120)
* msubMN4 instruction pattern: Standard Names. (line 387)
@ -44413,13 +44417,13 @@ Concept Index
* nonimmediate_operand: Machine-Independent Predicates.
(line 101)
* nonlocal goto handler: Edges. (line 171)
* nonlocal_goto instruction pattern: Standard Names. (line 1221)
* nonlocal_goto instruction pattern: Standard Names. (line 1225)
* nonlocal_goto_receiver instruction pattern: Standard Names.
(line 1238)
(line 1242)
* nonmemory_operand: Machine-Independent Predicates.
(line 97)
* nonoffsettable memory reference: Simple Constraints. (line 246)
* nop instruction pattern: Standard Names. (line 1032)
* nop instruction pattern: Standard Names. (line 1036)
* NOP_EXPR: Unary and Binary Expressions.
(line 6)
* normal predicates: Predicates. (line 31)
@ -44614,7 +44618,7 @@ Concept Index
* PREFERRED_STACK_BOUNDARY: Storage Layout. (line 159)
* prefetch: Side Effects. (line 312)
* prefetch and /v: Flags. (line 232)
* prefetch instruction pattern: Standard Names. (line 1360)
* prefetch instruction pattern: Standard Names. (line 1364)
* PREFETCH_SCHEDULE_BARRIER_P: Flags. (line 232)
* PREINCREMENT_EXPR: Unary and Binary Expressions.
(line 6)
@ -44627,7 +44631,7 @@ Concept Index
* PRINT_OPERAND: Instruction Output. (line 81)
* PRINT_OPERAND_ADDRESS: Instruction Output. (line 109)
* PRINT_OPERAND_PUNCT_VALID_P: Instruction Output. (line 102)
* probe_stack instruction pattern: Standard Names. (line 1213)
* probe_stack instruction pattern: Standard Names. (line 1217)
* processor functional units: Processor pipeline description.
(line 6)
* processor pipeline description: Processor pipeline description.
@ -44642,7 +44646,7 @@ Concept Index
* profiling, code generation: Profiling. (line 6)
* program counter: Regs and Memory. (line 362)
* prologue: Function Entry. (line 6)
* prologue instruction pattern: Standard Names. (line 1304)
* prologue instruction pattern: Standard Names. (line 1308)
* PROMOTE_MODE: Storage Layout. (line 100)
* pseudo registers: Regs and Memory. (line 9)
* PSImode: Machine Modes. (line 32)
@ -44804,7 +44808,7 @@ Concept Index
(line 6)
* relative costs: Costs. (line 6)
* RELATIVE_PREFIX_NOT_LINKDIR: Driver. (line 325)
* reload_completed: Standard Names. (line 999)
* reload_completed: Standard Names. (line 1003)
* reload_in instruction pattern: Standard Names. (line 99)
* reload_in_progress: Standard Names. (line 57)
* reload_out instruction pattern: Standard Names. (line 99)
@ -44817,14 +44821,14 @@ Concept Index
(line 6)
* rest_of_decl_compilation: Parsing pass. (line 52)
* rest_of_type_compilation: Parsing pass. (line 52)
* restore_stack_block instruction pattern: Standard Names. (line 1133)
* restore_stack_block instruction pattern: Standard Names. (line 1137)
* restore_stack_function instruction pattern: Standard Names.
(line 1133)
(line 1137)
* restore_stack_nonlocal instruction pattern: Standard Names.
(line 1133)
(line 1137)
* RESULT_DECL: Declarations. (line 6)
* return: Side Effects. (line 72)
* return instruction pattern: Standard Names. (line 986)
* return instruction pattern: Standard Names. (line 990)
* return values in registers: Scalar Return. (line 6)
* RETURN_ADDR_IN_PREVIOUS_FRAME: Frame Layout. (line 135)
* RETURN_ADDR_OFFSET: Exception Handling. (line 60)
@ -44912,15 +44916,15 @@ Concept Index
* same_type_p: Types. (line 88)
* SAmode: Machine Modes. (line 148)
* sat_fract: Conversions. (line 90)
* satfractMN2 instruction pattern: Standard Names. (line 825)
* satfractunsMN2 instruction pattern: Standard Names. (line 838)
* satfractMN2 instruction pattern: Standard Names. (line 829)
* satfractunsMN2 instruction pattern: Standard Names. (line 842)
* satisfies_constraint_: C Constraint Interface.
(line 47)
* SAVE_EXPR: Unary and Binary Expressions.
(line 6)
* save_stack_block instruction pattern: Standard Names. (line 1133)
* save_stack_function instruction pattern: Standard Names. (line 1133)
* save_stack_nonlocal instruction pattern: Standard Names. (line 1133)
* save_stack_block instruction pattern: Standard Names. (line 1137)
* save_stack_function instruction pattern: Standard Names. (line 1137)
* save_stack_nonlocal instruction pattern: Standard Names. (line 1137)
* SBSS_SECTION_ASM_OP: Sections. (line 77)
* Scalar evolutions: Scalar evolutions. (line 6)
* scalars, returned as values: Scalar Return. (line 6)
@ -44977,7 +44981,7 @@ Concept Index
* SHORT_FRACT_TYPE_SIZE: Type Layout. (line 63)
* SHORT_IMMEDIATES_SIGN_EXTEND: Misc. (line 96)
* SHORT_TYPE_SIZE: Type Layout. (line 16)
* sibcall_epilogue instruction pattern: Standard Names. (line 1330)
* sibcall_epilogue instruction pattern: Standard Names. (line 1334)
* sibling call: Edges. (line 122)
* SIBLING_CALL_P: Flags. (line 179)
* SIG_ATOMIC_TYPE: Type Layout. (line 235)
@ -45062,8 +45066,8 @@ Concept Index
* STACK_POINTER_REGNUM and virtual registers: Regs and Memory.
(line 83)
* stack_pointer_rtx: Frame Registers. (line 90)
* stack_protect_set instruction pattern: Standard Names. (line 1501)
* stack_protect_test instruction pattern: Standard Names. (line 1511)
* stack_protect_set instruction pattern: Standard Names. (line 1505)
* stack_protect_test instruction pattern: Standard Names. (line 1515)
* STACK_PUSH_CODE: Frame Layout. (line 17)
* STACK_REG_COVER_CLASS: Stack Registers. (line 23)
* STACK_REGS: Stack Registers. (line 20)
@ -45109,7 +45113,7 @@ Concept Index
* STRING_CST: Constant expressions.
(line 6)
* STRING_POOL_ADDRESS_P: Flags. (line 183)
* strlenM instruction pattern: Standard Names. (line 760)
* strlenM instruction pattern: Standard Names. (line 764)
* structure value address: Aggregate Return. (line 6)
* STRUCTURE_SIZE_BOUNDARY: Storage Layout. (line 302)
* structures, returning: Interface. (line 10)
@ -45168,35 +45172,35 @@ Concept Index
* SYMBOL_REF_USED: Flags. (line 215)
* SYMBOL_REF_WEAK: Flags. (line 220)
* symbolic label: Sharing. (line 20)
* sync_addMODE instruction pattern: Standard Names. (line 1417)
* sync_andMODE instruction pattern: Standard Names. (line 1417)
* sync_addMODE instruction pattern: Standard Names. (line 1421)
* sync_andMODE instruction pattern: Standard Names. (line 1421)
* sync_compare_and_swapMODE instruction pattern: Standard Names.
(line 1387)
* sync_iorMODE instruction pattern: Standard Names. (line 1417)
* sync_lock_releaseMODE instruction pattern: Standard Names. (line 1482)
(line 1391)
* sync_iorMODE instruction pattern: Standard Names. (line 1421)
* sync_lock_releaseMODE instruction pattern: Standard Names. (line 1486)
* sync_lock_test_and_setMODE instruction pattern: Standard Names.
(line 1456)
* sync_nandMODE instruction pattern: Standard Names. (line 1417)
* sync_new_addMODE instruction pattern: Standard Names. (line 1449)
* sync_new_andMODE instruction pattern: Standard Names. (line 1449)
* sync_new_iorMODE instruction pattern: Standard Names. (line 1449)
* sync_new_nandMODE instruction pattern: Standard Names. (line 1449)
* sync_new_subMODE instruction pattern: Standard Names. (line 1449)
* sync_new_xorMODE instruction pattern: Standard Names. (line 1449)
* sync_old_addMODE instruction pattern: Standard Names. (line 1432)
* sync_old_andMODE instruction pattern: Standard Names. (line 1432)
* sync_old_iorMODE instruction pattern: Standard Names. (line 1432)
* sync_old_nandMODE instruction pattern: Standard Names. (line 1432)
* sync_old_subMODE instruction pattern: Standard Names. (line 1432)
* sync_old_xorMODE instruction pattern: Standard Names. (line 1432)
* sync_subMODE instruction pattern: Standard Names. (line 1417)
* sync_xorMODE instruction pattern: Standard Names. (line 1417)
(line 1460)
* sync_nandMODE instruction pattern: Standard Names. (line 1421)
* sync_new_addMODE instruction pattern: Standard Names. (line 1453)
* sync_new_andMODE instruction pattern: Standard Names. (line 1453)
* sync_new_iorMODE instruction pattern: Standard Names. (line 1453)
* sync_new_nandMODE instruction pattern: Standard Names. (line 1453)
* sync_new_subMODE instruction pattern: Standard Names. (line 1453)
* sync_new_xorMODE instruction pattern: Standard Names. (line 1453)
* sync_old_addMODE instruction pattern: Standard Names. (line 1436)
* sync_old_andMODE instruction pattern: Standard Names. (line 1436)
* sync_old_iorMODE instruction pattern: Standard Names. (line 1436)
* sync_old_nandMODE instruction pattern: Standard Names. (line 1436)
* sync_old_subMODE instruction pattern: Standard Names. (line 1436)
* sync_old_xorMODE instruction pattern: Standard Names. (line 1436)
* sync_subMODE instruction pattern: Standard Names. (line 1421)
* sync_xorMODE instruction pattern: Standard Names. (line 1421)
* SYSROOT_HEADERS_SUFFIX_SPEC: Driver. (line 239)
* SYSROOT_SUFFIX_SPEC: Driver. (line 234)
* SYSTEM_INCLUDE_DIR: Driver. (line 408)
* t-TARGET: Target Fragment. (line 6)
* table jump: Basic Blocks. (line 57)
* tablejump instruction pattern: Standard Names. (line 1061)
* tablejump instruction pattern: Standard Names. (line 1065)
* tag: GTY Options. (line 81)
* tagging insns: Tagging Insns. (line 6)
* tail calls: Tail Calls. (line 6)
@ -45571,7 +45575,7 @@ Concept Index
* TRAMPOLINE_SIZE: Trampolines. (line 45)
* trampolines for nested functions: Trampolines. (line 6)
* TRANSFER_FROM_TRAMPOLINE: Trampolines. (line 123)
* trap instruction pattern: Standard Names. (line 1340)
* trap instruction pattern: Standard Names. (line 1344)
* tree <1>: Macros and Functions.
(line 6)
* tree: Tree overview. (line 6)
@ -45628,7 +45632,7 @@ Concept Index
* TRUNC_MOD_EXPR: Unary and Binary Expressions.
(line 6)
* truncate: Conversions. (line 38)
* truncMN2 instruction pattern: Standard Names. (line 803)
* truncMN2 instruction pattern: Standard Names. (line 807)
* TRUTH_AND_EXPR: Unary and Binary Expressions.
(line 6)
* TRUTH_ANDIF_EXPR: Unary and Binary Expressions.
@ -45782,8 +45786,8 @@ Concept Index
* unsigned_sat_fract: Conversions. (line 103)
* unspec: Side Effects. (line 287)
* unspec_volatile: Side Effects. (line 287)
* untyped_call instruction pattern: Standard Names. (line 971)
* untyped_return instruction pattern: Standard Names. (line 1021)
* untyped_call instruction pattern: Standard Names. (line 975)
* untyped_return instruction pattern: Standard Names. (line 1025)
* UPDATE_PATH_HOST_CANONICALIZE (PATH): Filesystem. (line 59)
* update_ssa: SSA. (line 76)
* update_stmt <1>: SSA Operands. (line 6)
@ -45972,7 +45976,7 @@ Concept Index
* XVECLEN: Accessors. (line 44)
* XWINT: Accessors. (line 6)
* zero_extend: Conversions. (line 28)
* zero_extendMN2 instruction pattern: Standard Names. (line 813)
* zero_extendMN2 instruction pattern: Standard Names. (line 817)
* zero_extract: Bit-Fields. (line 30)
* zero_extract, canonicalization of: Insn Canonicalizations.
(line 88)
@ -46192,131 +46196,131 @@ Node: Define Constraints874656
Node: C Constraint Interface881437
Node: Standard Names885078
Ref: shift patterns904006
Ref: prologue instruction pattern943725
Ref: epilogue instruction pattern944218
Node: Pattern Ordering953934
Node: Dependent Patterns955170
Node: Jump Patterns956790
Ref: Jump Patterns-Footnote-1958934
Node: Looping Patterns958980
Node: Insn Canonicalizations963708
Node: Expander Definitions967659
Node: Insn Splitting975777
Node: Including Patterns985379
Node: Peephole Definitions987159
Node: define_peephole988412
Node: define_peephole2994743
Node: Insn Attributes997810
Node: Defining Attributes998916
Node: Expressions1001436
Node: Tagging Insns1008038
Node: Attr Example1012391
Node: Insn Lengths1014765
Node: Constant Attributes1017824
Node: Delay Slots1018993
Node: Processor pipeline description1022217
Ref: Processor pipeline description-Footnote-11039835
Node: Conditional Execution1040157
Node: Constant Definitions1043010
Node: Iterators1044605
Node: Mode Iterators1045052
Node: Defining Mode Iterators1046030
Node: Substitutions1047524
Node: Examples1049765
Node: Code Iterators1051213
Node: Target Macros1053470
Node: Target Structure1056558
Node: Driver1057827
Node: Run-time Target1081508
Node: Per-Function Data1089380
Node: Storage Layout1092143
Node: Type Layout1117729
Node: Registers1132229
Node: Register Basics1133203
Node: Allocation Order1138770
Node: Values in Registers1140791
Node: Leaf Functions1148280
Node: Stack Registers1151138
Node: Register Classes1152410
Node: Old Constraints1180035
Node: Stack and Calling1187187
Node: Frame Layout1187721
Node: Exception Handling1198601
Node: Stack Checking1204979
Node: Frame Registers1209792
Node: Elimination1216685
Node: Stack Arguments1220914
Node: Register Arguments1227723
Node: Scalar Return1243201
Node: Aggregate Return1249293
Node: Caller Saves1252974
Node: Function Entry1254152
Node: Profiling1266780
Node: Tail Calls1268479
Node: Stack Smashing Protection1269845
Node: Varargs1270957
Node: Trampolines1278952
Node: Library Calls1285599
Node: Addressing Modes1290449
Node: Anchored Addresses1307858
Node: Condition Code1310507
Node: CC0 Condition Codes1312636
Node: MODE_CC Condition Codes1315882
Node: Cond. Exec. Macros1322111
Node: Costs1323090
Node: Scheduling1336551
Node: Sections1353818
Node: PIC1368886
Node: Assembler Format1370890
Node: File Framework1372028
Ref: TARGET_HAVE_SWITCHABLE_BSS_SECTIONS1377503
Node: Data Output1380768
Node: Uninitialized Data1388527
Node: Label Output1394091
Node: Initialization1415781
Node: Macros for Initialization1421743
Node: Instruction Output1428195
Node: Dispatch Tables1437866
Node: Exception Region Output1441681
Node: Alignment Output1447423
Node: Debugging Info1451586
Node: All Debuggers1452256
Node: DBX Options1455111
Node: DBX Hooks1460560
Node: File Names and DBX1462486
Node: SDB and DWARF1464598
Node: VMS Debug1468899
Node: Floating Point1469469
Node: Mode Switching1474292
Node: Target Attributes1478218
Node: Emulated TLS1485054
Node: MIPS Coprocessors1488444
Node: PCH Target1490013
Node: C++ ABI1491555
Node: Named Address Spaces1496204
Node: Misc1501306
Ref: TARGET_SHIFT_TRUNCATION_MASK1508734
Node: Host Config1553245
Node: Host Common1554313
Node: Filesystem1556692
Node: Host Misc1560807
Node: Fragments1563256
Node: Target Fragment1564451
Node: Host Fragment1570341
Node: Collect21570581
Node: Header Dirs1573217
Node: Type Information1574640
Node: GTY Options1576931
Node: GGC Roots1587606
Node: Files1588326
Node: Invoking the garbage collector1591072
Node: Plugins1592125
Node: Funding1607947
Node: GNU Project1610434
Node: Copying1611083
Node: GNU Free Documentation License1648614
Node: Contributors1671023
Node: Option Index1707710
Node: Concept Index1708295
Ref: prologue instruction pattern944017
Ref: epilogue instruction pattern944510
Node: Pattern Ordering954226
Node: Dependent Patterns955462
Node: Jump Patterns957082
Ref: Jump Patterns-Footnote-1959226
Node: Looping Patterns959272
Node: Insn Canonicalizations964000
Node: Expander Definitions967951
Node: Insn Splitting976069
Node: Including Patterns985671
Node: Peephole Definitions987451
Node: define_peephole988704
Node: define_peephole2995035
Node: Insn Attributes998102
Node: Defining Attributes999208
Node: Expressions1001728
Node: Tagging Insns1008330
Node: Attr Example1012683
Node: Insn Lengths1015057
Node: Constant Attributes1018116
Node: Delay Slots1019285
Node: Processor pipeline description1022509
Ref: Processor pipeline description-Footnote-11040127
Node: Conditional Execution1040449
Node: Constant Definitions1043302
Node: Iterators1044897
Node: Mode Iterators1045344
Node: Defining Mode Iterators1046322
Node: Substitutions1047816
Node: Examples1050057
Node: Code Iterators1051505
Node: Target Macros1053762
Node: Target Structure1056850
Node: Driver1058119
Node: Run-time Target1081800
Node: Per-Function Data1089672
Node: Storage Layout1092435
Node: Type Layout1118021
Node: Registers1132521
Node: Register Basics1133495
Node: Allocation Order1139062
Node: Values in Registers1141083
Node: Leaf Functions1148572
Node: Stack Registers1151430
Node: Register Classes1152702
Node: Old Constraints1180327
Node: Stack and Calling1187479
Node: Frame Layout1188013
Node: Exception Handling1198893
Node: Stack Checking1205271
Node: Frame Registers1210084
Node: Elimination1216977
Node: Stack Arguments1221206
Node: Register Arguments1228015
Node: Scalar Return1243493
Node: Aggregate Return1249585
Node: Caller Saves1253266
Node: Function Entry1254444
Node: Profiling1267072
Node: Tail Calls1268771
Node: Stack Smashing Protection1270137
Node: Varargs1271249
Node: Trampolines1279244
Node: Library Calls1285891
Node: Addressing Modes1290741
Node: Anchored Addresses1308150
Node: Condition Code1310799
Node: CC0 Condition Codes1312928
Node: MODE_CC Condition Codes1316174
Node: Cond. Exec. Macros1322403
Node: Costs1323382
Node: Scheduling1336843
Node: Sections1354110
Node: PIC1369178
Node: Assembler Format1371182
Node: File Framework1372320
Ref: TARGET_HAVE_SWITCHABLE_BSS_SECTIONS1377795
Node: Data Output1381060
Node: Uninitialized Data1388819
Node: Label Output1394383
Node: Initialization1416073
Node: Macros for Initialization1422035
Node: Instruction Output1428487
Node: Dispatch Tables1438158
Node: Exception Region Output1441973
Node: Alignment Output1447715
Node: Debugging Info1451878
Node: All Debuggers1452548
Node: DBX Options1455403
Node: DBX Hooks1460852
Node: File Names and DBX1462778
Node: SDB and DWARF1464890
Node: VMS Debug1469191
Node: Floating Point1469761
Node: Mode Switching1474584
Node: Target Attributes1478510
Node: Emulated TLS1485346
Node: MIPS Coprocessors1488736
Node: PCH Target1490305
Node: C++ ABI1491847
Node: Named Address Spaces1496496
Node: Misc1501598
Ref: TARGET_SHIFT_TRUNCATION_MASK1509026
Node: Host Config1553537
Node: Host Common1554605
Node: Filesystem1556984
Node: Host Misc1561099
Node: Fragments1563548
Node: Target Fragment1564743
Node: Host Fragment1570633
Node: Collect21570873
Node: Header Dirs1573509
Node: Type Information1574932
Node: GTY Options1577223
Node: GGC Roots1587898
Node: Files1588618
Node: Invoking the garbage collector1591364
Node: Plugins1592417
Node: Funding1608239
Node: GNU Project1610726
Node: Copying1611375
Node: GNU Free Documentation License1648906
Node: Contributors1671315
Node: Option Index1708002
Node: Concept Index1708587

End Tag Table

2
external/gpl3/gcc/dist/gcc/doc/gcj-dbtool.1 vendored
View File

@ -132,7 +132,7 @@
.\" ========================================================================
.\"
.IX Title "GCJ-DBTOOL 1"
.TH GCJ-DBTOOL 1 "2011-04-28" "gcc-4.5.3" "GNU"
.TH GCJ-DBTOOL 1 "2012-07-02" "gcc-4.5.4" "GNU"
.\" For nroff, turn off justification. Always turn off hyphenation; it makes
.\" way too many mistakes in technical documents.
.if n .ad l

2
external/gpl3/gcc/dist/gcc/doc/gcj.1 vendored
View File

@ -132,7 +132,7 @@
.\" ========================================================================
.\"
.IX Title "GCJ 1"
.TH GCJ 1 "2011-04-28" "gcc-4.5.3" "GNU"
.TH GCJ 1 "2012-07-02" "gcc-4.5.4" "GNU"
.\" For nroff, turn off justification. Always turn off hyphenation; it makes
.\" way too many mistakes in technical documents.
.if n .ad l

2
external/gpl3/gcc/dist/gcc/doc/gcj.info vendored
View File

@ -1,5 +1,5 @@
This is doc/gcj.info, produced by makeinfo version 4.12 from
/space/rguenther/gcc-4.5.3/gcc-4.5.3/gcc/java/gcj.texi.
/space/rguenther/gcc-4.5.4/gcc-4.5.4/gcc/java/gcj.texi.
Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 Free
Software Foundation, Inc.

2
external/gpl3/gcc/dist/gcc/doc/gcov.1 vendored
View File

@ -132,7 +132,7 @@
.\" ========================================================================
.\"
.IX Title "GCOV 1"
.TH GCOV 1 "2011-04-28" "gcc-4.5.3" "GNU"
.TH GCOV 1 "2012-07-02" "gcc-4.5.4" "GNU"
.\" For nroff, turn off justification. Always turn off hyphenation; it makes
.\" way too many mistakes in technical documents.
.if n .ad l

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