change NO_REG_W to ICU_NO_REG_W.
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sato
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a96c83ebbb
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@ -1,4 +1,4 @@
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/* $NetBSD: icureg.h,v 1.5 2001/09/27 13:59:37 sato Exp $ */
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/* $NetBSD: icureg.h,v 1.6 2002/02/09 14:54:05 sato Exp $ */
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/*-
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* Copyright (c) 1999 Shin Takemura. All rights reserved.
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@ -47,7 +47,7 @@
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#error currently missconfiguraton.
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#endif
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#define NO_REG_W 0 /* no register */
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#define ICU_NO_REG_W 0xffffffff /* no register */
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/* SYSINT1 & MSYSINT1 */
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@ -100,8 +100,8 @@
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/* AIUINT & MAIUINT */
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#define VR4102_AIUINT_REG_W 0x004 /* Level2 AIU intr reg */
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#define VR4102_MAIUINT_REG_W 0x010 /* Level2 Mask AIU intr reg */
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#define VR4122_AIUINT_REG_W NO_REG_W /* Level2 AIU intr reg */
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#define VR4122_MAIUINT_REG_W NO_REG_W /* Level2 Mask AIU intr reg */
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#define VR4122_AIUINT_REG_W ICU_NO_REG_W /* Level2 AIU intr reg */
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#define VR4122_MAIUINT_REG_W ICU_NO_REG_W /* Level2 Mask AIU intr reg */
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#define VR4181_AIUINT_REG_W 0x004 /* Level2 AIU intr reg */
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#define VR4181_MAIUINT_REG_W 0x010 /* Level2 Mask AIU intr reg */
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#if defined SINGLE_VRIP_BASE
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@ -131,8 +131,8 @@
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/* KIUINT & MKIUINT */
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#define VR4102_KIUINT_REG_W 0x006 /* Level2 KIU intr reg */
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#define VR4102_MKIUINT_REG_W 0x012 /* Level2 Mask KIU intr reg */
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#define VR4122_KIUINT_REG_W NO_REG_W /* Level2 KIU intr reg */
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#define VR4122_MKIUINT_REG_W NO_REG_W /* Level2 Mask KIU intr reg */
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#define VR4122_KIUINT_REG_W ICU_NO_REG_W /* Level2 KIU intr reg */
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#define VR4122_MKIUINT_REG_W ICU_NO_REG_W /* Level2 Mask KIU intr reg */
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#define VR4181_KIUINT_REG_W 0x118 /* Level2 KIU intr reg */
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#define VR4181_MKIUINT_REG_W 0x012 /* Level2 Mask KIU intr reg */
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#if defined SINGLE_VRIP_BASE
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@ -160,8 +160,8 @@
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#define VR4102_MGIUINT_L_REG_W 0x014 /* Level2 Mask GIU intr reg Low */
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#define VR4122_GIUINT_L_REG_W 0x008 /* Level2 GIU intr reg Low */
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#define VR4122_MGIUINT_L_REG_W 0x014 /* Level2 Mask GIU intr reg Low */
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#define VR4181_GIUINT_L_REG_W NO_REG_W /* Level2 GIU intr reg Low */
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#define VR4181_MGIUINT_L_REG_W NO_REG_W /* Level2 Mask GIU intr reg Low */
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#define VR4181_GIUINT_L_REG_W ICU_NO_REG_W /* Level2 GIU intr reg Low */
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#define VR4181_MGIUINT_L_REG_W ICU_NO_REG_W /* Level2 Mask GIU intr reg Low */
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#if defined SINGLE_VRIP_BASE
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#if defined VRGROUP_4102_4121
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#define GIUINT_L_REG_W VR4102_GIUINT_L_REG_W
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@ -200,8 +200,8 @@
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#define VR4102_MDSIUINT_REG_W 0x016 /* Level2 Mask DSIU intr reg */
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#define VR4122_DSIUINT_REG_W 0x00a /* Level2 DSIU intr reg */
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#define VR4122_MDSIUINT_REG_W 0x016 /* Level2 Mask DSIU intr reg */
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#define VR4181_DSIUINT_REG_W NO_REG_W /* Level2 DSIU intr reg */
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#define VR4181_MDSIUINT_REG_W NO_REG_W /* Level2 Mask DSIU intr reg */
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#define VR4181_DSIUINT_REG_W ICU_NO_REG_W /* Level2 DSIU intr reg */
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#define VR4181_MDSIUINT_REG_W ICU_NO_REG_W /* Level2 Mask DSIU intr reg */
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#if defined SINGLE_VRIP_BASE
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#if defined VRGROUP_4102_4121
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#define DSIUINT_REG_W VR4102_DSIUINT_REG_W
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@ -304,8 +304,8 @@
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#define VR4102_MGIUINT_H_REG_W 0x188 /* Level2 Mask GIU intr reg High */
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#define VR4122_GIUINT_H_REG_W 0x022 /* Level2 GIU intr reg High */
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#define VR4122_MGIUINT_H_REG_W 0x028 /* Level2 Mask GIU intr reg High */
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#define VR4181_GIUINT_H_REG_W NO_REG_W /* Level2 GIU intr reg High */
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#define VR4181_MGIUINT_H_REG_W NO_REG_W /* Level2 Mask GIU intr reg High */
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#define VR4181_GIUINT_H_REG_W ICU_NO_REG_W /* Level2 GIU intr reg High */
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#define VR4181_MGIUINT_H_REG_W ICU_NO_REG_W /* Level2 Mask GIU intr reg High */
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#if defined SINGLE_VRIP_BASE
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#if defined VRGROUP_4102_4121
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#define GIUINT_H_REG_W VR4102_GIUINT_H_REG_W
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@ -344,8 +344,8 @@
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#define VR4102_MFIRINT_REG_W 0x18a /* Level2 Mask FIR intr reg */
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#define VR4122_FIRINT_REG_W 0x024 /* Level2 FIR intr reg */
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#define VR4122_MFIRINT_REG_W 0x02a /* Level2 Mask FIR intr reg */
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#define VR4181_FIRINT_REG_W NO_REG_W /* Level2 FIR intr reg */
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#define VR4181_MFIRINT_REG_W NO_REG_W /* Level2 Mask FIR intr reg */
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#define VR4181_FIRINT_REG_W ICU_NO_REG_W /* Level2 FIR intr reg */
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#define VR4181_MFIRINT_REG_W ICU_NO_REG_W /* Level2 Mask FIR intr reg */
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#if defined SINGLE_VRIP_BASE
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#if defined VRGROUP_4102_4121
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#define FIRINT_REG_W VR4102_FIRINT_REG_W
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@ -369,12 +369,12 @@
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/* PCIINT & MPCIINT */
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#define VR4102_PCIINT_REG_W NO_REG_W /* Level2 PCI intr reg */
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#define VR4102_MPCIINT_REG_W NO_REG_W /* Level2 PCI intr mask */
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#define VR4102_PCIINT_REG_W ICU_NO_REG_W /* Level2 PCI intr reg */
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#define VR4102_MPCIINT_REG_W ICU_NO_REG_W /* Level2 PCI intr mask */
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#define VR4122_PCIINT_REG_W 0x2c /* Level2 PCI intr reg */
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#define VR4122_MPCIINT_REG_W 0x32 /* Level2 PCI intr mask */
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#define VR4181_PCIINT_REG_W NO_REG_W /* Level2 PCI intr reg */
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#define VR4181_MPCIINT_REG_W NO_REG_W /* Level2 PCI intr mask */
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#define VR4181_PCIINT_REG_W ICU_NO_REG_W /* Level2 PCI intr reg */
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#define VR4181_MPCIINT_REG_W ICU_NO_REG_W /* Level2 PCI intr mask */
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#if defined SINGLE_VRIP_BASE
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#if defined VRGROUP_4102_4121
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#define PCIINT_REG_W VR4102_PCIINT_REG_W
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@ -394,12 +394,12 @@
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/* SCUINT & MSCUINT */
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#define VR4102_SCUINT_REG_W NO_REG_W /* Level2 SCU intr reg */
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#define VR4102_MSCUINT_REG_W NO_REG_W /* Level2 SCU intr mask */
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#define VR4102_SCUINT_REG_W ICU_NO_REG_W /* Level2 SCU intr reg */
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#define VR4102_MSCUINT_REG_W ICU_NO_REG_W /* Level2 SCU intr mask */
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#define VR4122_SCUINT_REG_W 0x2e /* Level2 SCU intr reg */
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#define VR4122_MSCUINT_REG_W 0x34 /* Level2 SCU intr mask */
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#define VR4181_SCUINT_REG_W NO_REG_W /* Level2 SCU intr reg */
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#define VR4181_MSCUINT_REG_W NO_REG_W /* Level2 SCU intr mask */
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#define VR4181_SCUINT_REG_W ICU_NO_REG_W /* Level2 SCU intr reg */
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#define VR4181_MSCUINT_REG_W ICU_NO_REG_W /* Level2 SCU intr mask */
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#if defined SINGLE_VRIP_BASE
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#if defined VRGROUP_4102_4121
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#define SCUINT_REG_W VR4102_SCUINT_REG_W
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@ -419,12 +419,12 @@
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/* CSIINT & MCSIINT */
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#define VR4102_CSIINT_REG_W NO_REG_W /* Level2 CSI intr reg */
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#define VR4102_MCSIINT_REG_W NO_REG_W /* Level2 CSI intr mask */
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#define VR4102_CSIINT_REG_W ICU_NO_REG_W /* Level2 CSI intr reg */
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#define VR4102_MCSIINT_REG_W ICU_NO_REG_W /* Level2 CSI intr mask */
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#define VR4122_CSIINT_REG_W 0x30 /* Level2 CSI intr reg */
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#define VR4122_MCSIINT_REG_W 0x36 /* Level2 CSI intr mask */
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#define VR4181_CSIINT_REG_W NO_REG_W /* Level2 CSI intr reg */
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#define VR4181_MCSIINT_REG_W NO_REG_W /* Level2 CSI intr mask */
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#define VR4181_CSIINT_REG_W ICU_NO_REG_W /* Level2 CSI intr reg */
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#define VR4181_MCSIINT_REG_W ICU_NO_REG_W /* Level2 CSI intr mask */
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#if defined SINGLE_VRIP_BASE
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#if defined VRGROUP_4102_4121
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#define CSIINT_REG_W VR4102_CSIINT_REG_W
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@ -450,12 +450,12 @@
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/* BCUINT & MBCUINT */
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#define VR4102_BCUINT_REG_W NO_REG_W /* Level2 BCU intr reg */
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#define VR4102_MBCUINT_REG_W NO_REG_W /* Level2 BCU intr mask */
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#define VR4102_BCUINT_REG_W ICU_NO_REG_W /* Level2 BCU intr reg */
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#define VR4102_MBCUINT_REG_W ICU_NO_REG_W /* Level2 BCU intr mask */
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#define VR4122_BCUINT_REG_W 0x38 /* Level2 BCU intr reg */
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#define VR4122_MBCUINT_REG_W 0x3a /* Level2 BCU intr mask */
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#define VR4181_BCUINT_REG_W NO_REG_W /* Level2 BCU intr reg */
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#define VR4181_MBCUINT_REG_W NO_REG_W /* Level2 BCU intr mask */
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#define VR4181_BCUINT_REG_W ICU_NO_REG_W /* Level2 BCU intr reg */
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#define VR4181_MBCUINT_REG_W ICU_NO_REG_W /* Level2 BCU intr mask */
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#if defined SINGLE_VRIP_BASE
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#if defined VRGROUP_4102_4121
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#define BCUINT_REG_W VR4102_BCUINT_REG_W
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