Add a workaround to handle virtual alias which may cause data corruption
on R5000/Rm52xx machines: - Add a new global variable mips_cache_virtual_alias in mips/cache.c, which indicates that VIPT cache on the CPU could cause virtual alias and software support is required to handle it. (i.e. no VCED/VCEI) - Add several cache flush/invalidate ops around KSEG0 access which might cause virtual alias if mips_cache_virtual_alias is true. (note checking mips_sdcache_line_size isn't valid for R5000/Rm52xx because only R4000/R4400 with L2 cache have VCED/VCEI) - Remove a global variable mips_sdcache_forceinv, which is now superseded by new mips_cache_virtual_alias. While here, also change some R4000/R4400 cache ops: - Don't override mips_cache_alias_mask and mips_cache_prefer_mask with values based on MIPS3_MAX_PCACHE_SIZE for R4000/R4400 with L2 cache because it's still worth to reduce VCED/VCEI. - Flush dcache in pmap_zero_page(9) unconditionally on all MIPS_HAS_R4K_MMU CPUs and remove cache flush code from cpu_lwp_fork() in vm_machdep.c. Thanks to Markus W Kilbinger for testing patches on port-cobalt/port-mips. XXX This fix is just a workaround because it doesn't handle all possible XXX virtual aliases. As discussed on port-mips, maybe the real fix XXX for virtual alias is to change MI UVM to adapt it to VIPT cache. XXX (all VA mappings against the same PA must have the same VAC index etc.)
This commit is contained in:
tsutsui
parent
5067941219
commit
a8d2e55834
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@ -1,4 +1,4 @@
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/* $NetBSD: cache.h,v 1.7 2005/03/01 04:23:44 sekiya Exp $ */
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/* $NetBSD: cache.h,v 1.8 2005/03/26 09:51:02 tsutsui Exp $ */
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/*
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* Copyright 2001 Wasabi Systems, Inc.
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@ -185,8 +185,6 @@ extern int mips_sdcache_write_through;
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extern int mips_scache_unified;
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extern u_int mips_sdcache_forceinv; /* force pmap to invalidate for r5ksc */
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/* TERTIARY CACHE VARIABLES */
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extern u_int mips_tcache_size; /* always unified */
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extern u_int mips_tcache_line_size;
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@ -201,6 +199,8 @@ extern u_int mips_dcache_align_mask;
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extern u_int mips_cache_alias_mask;
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extern u_int mips_cache_prefer_mask;
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extern int mips_cache_virtual_alias;
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/*
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* XXX XXX XXX THIS SHOULD NOT EXIST XXX XXX XXX
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*/
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.h,v 1.46 2005/01/17 04:54:14 atatat Exp $ */
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/* $NetBSD: pmap.h,v 1.47 2005/03/26 09:51:02 tsutsui Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -180,8 +180,10 @@ void pmap_prefer(vaddr_t, vaddr_t *, int);
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/*
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* Alternate mapping hooks for pool pages. Avoids thrashing the TLB.
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*/
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#define PMAP_MAP_POOLPAGE(pa) MIPS_PHYS_TO_KSEG0((pa))
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#define PMAP_UNMAP_POOLPAGE(va) MIPS_KSEG0_TO_PHYS((va))
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vaddr_t mips_pmap_map_poolpage(paddr_t);
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paddr_t mips_pmap_unmap_poolpage(vaddr_t);
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#define PMAP_MAP_POOLPAGE(pa) mips_pmap_map_poolpage(pa)
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#define PMAP_UNMAP_POOLPAGE(va) mips_pmap_unmap_poolpage(va)
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/*
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* Other hooks for the pool allocator.
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@ -1,4 +1,4 @@
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/* $NetBSD: cache.c,v 1.26 2005/03/01 04:23:44 sekiya Exp $ */
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/* $NetBSD: cache.c,v 1.27 2005/03/26 09:51:02 tsutsui Exp $ */
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/*
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* Copyright 2001, 2002 Wasabi Systems, Inc.
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@ -68,7 +68,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.26 2005/03/01 04:23:44 sekiya Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.27 2005/03/26 09:51:02 tsutsui Exp $");
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#include "opt_cputype.h"
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#include "opt_mips_cache.h"
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@ -129,8 +129,6 @@ int mips_sdcache_write_through;
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int mips_scache_unified;
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u_int mips_sdcache_forceinv = 0;
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/* TERTIARY CACHE VARIABLES */
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u_int mips_tcache_size; /* always unified */
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u_int mips_tcache_line_size;
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@ -154,6 +152,8 @@ u_int mips_dcache_align_mask;
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u_int mips_cache_alias_mask; /* for virtually-indexed caches */
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u_int mips_cache_prefer_mask;
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int mips_cache_virtual_alias;
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struct mips_cache_ops mips_cache_ops;
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#ifdef MIPS1
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@ -421,6 +421,11 @@ mips_config_cache_prehistoric(void)
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mips3_get_cache_config(csizebase);
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if (mips_picache_size > PAGE_SIZE ||
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mips_pdcache_size > PAGE_SIZE)
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/* no VCE support if there is no L2 cache */
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mips_cache_virtual_alias = 1;
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switch (mips_picache_line_size) {
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case 16:
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mips_cache_ops.mco_icache_sync_all =
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@ -494,6 +499,10 @@ primary_cache_is_2way:
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mips3_get_cache_config(csizebase);
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if (mips_picache_size > PAGE_SIZE ||
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mips_pdcache_size > PAGE_SIZE)
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mips_cache_virtual_alias = 1;
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switch (mips_picache_line_size) {
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case 32:
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mips_cache_ops.mco_icache_sync_all =
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@ -590,6 +599,7 @@ primary_cache_is_2way:
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~(PAGE_SIZE - 1);
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mips_cache_prefer_mask =
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max(mips_pdcache_size, mips_picache_size) - 1;
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mips_cache_virtual_alias = 1;
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/* cache ops */
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mips_cache_ops.mco_icache_sync_all =
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r5900_icache_sync_all_64;
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@ -619,6 +629,8 @@ primary_cache_is_2way:
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mips4_get_cache_config(csizebase);
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/* VCE is handled by hardware */
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mips_cache_ops.mco_icache_sync_all =
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r10k_icache_sync_all;
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mips_cache_ops.mco_icache_sync_range =
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@ -669,14 +681,22 @@ primary_cache_is_2way:
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switch (MIPS_PRID_IMPL(cpu_id)) {
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#if defined(MIPS3) || defined(MIPS4)
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case MIPS_R4000:
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#if 0
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/*
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* R4000/R4400 always detects virtual alias as if
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* primary cache size is 32KB. Actual primary cache size
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* is ignored wrt VCED/VCEI.
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*/
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/*
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* XXX
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* It's still better to avoid virtual alias even with VCE,
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* isn't it?
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*/
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mips_cache_alias_mask =
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(MIPS3_MAX_PCACHE_SIZE - 1) & ~(PAGE_SIZE - 1);
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mips_cache_prefer_mask = MIPS3_MAX_PCACHE_SIZE - 1;
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#endif
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mips_cache_virtual_alias = 0;
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/* FALLTHROUGH */
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case MIPS_R4600:
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#ifdef ENABLE_MIPS_R4700
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@ -1,4 +1,4 @@
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/* $NetBSD: mem.c,v 1.29 2003/08/07 16:28:33 agc Exp $ */
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/* $NetBSD: mem.c,v 1.30 2005/03/26 09:51:02 tsutsui Exp $ */
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/*
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* Copyright (c) 1982, 1986, 1990, 1993
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* Memory special file
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*/
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#include "opt_cputype.h"
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#include "opt_mips_cache.h"
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: mem.c,v 1.29 2003/08/07 16:28:33 agc Exp $");
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__KERNEL_RCSID(0, "$NetBSD: mem.c,v 1.30 2005/03/26 09:51:02 tsutsui Exp $");
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#include <sys/param.h>
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#include <sys/conf.h>
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#include <machine/cpu.h>
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#include <mips/cache.h>
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#include <uvm/uvm_extern.h>
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extern paddr_t avail_end;
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return (EFAULT);
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v += MIPS_KSEG0_START;
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error = uiomove((void *)v, c, uio);
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#if defined(MIPS3_PLUS)
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if (mips_cache_virtual_alias)
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mips_dcache_wbinv_range(v, c);
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#endif
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continue;
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case DEV_KMEM:
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uio->uio_rw == UIO_READ ? B_READ : B_WRITE)))
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return (EFAULT);
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error = uiomove((void *)v, c, uio);
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#if defined(MIPS3_PLUS)
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if (mips_cache_virtual_alias)
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mips_dcache_wbinv_range(v, c);
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#endif
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continue;
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case DEV_NULL:
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.157 2005/03/01 04:23:44 sekiya Exp $ */
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/* $NetBSD: pmap.c,v 1.158 2005/03/26 09:51:02 tsutsui Exp $ */
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/*-
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* Copyright (c) 1998, 2001 The NetBSD Foundation, Inc.
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@ -74,7 +74,7 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.157 2005/03/01 04:23:44 sekiya Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.158 2005/03/26 09:51:02 tsutsui Exp $");
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/*
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* Manages physical address maps.
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@ -641,10 +641,10 @@ pmap_destroy(pmap)
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* were being accessed by KSEG0 (cached) addresses and
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* may cause cache coherency problems when the page
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* is reused with KSEG2 (mapped) addresses. This may
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* cause problems on machines without secondary caches.
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* cause problems on machines without VCED/VCEI.
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*/
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if (MIPS_HAS_R4K_MMU)
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mips_dcache_wbinv_range((vaddr_t) pte,
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if (mips_cache_virtual_alias)
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mips_dcache_inv_range((vaddr_t)pte,
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PAGE_SIZE);
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#endif /* MIPS3_PLUS */
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uvm_pagefree(PHYS_TO_VM_PAGE(MIPS_KSEG0_TO_PHYS(pte)));
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pmap_zero_page(phys)
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paddr_t phys;
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{
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vaddr_t va;
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#if defined(MIPS3_PLUS)
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pv_entry_t pv;
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#endif
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#ifdef DEBUG
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if (pmapdebug & PDB_FOLLOW)
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printf("pmap_zero_page(%lx)\n", (u_long)phys);
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if (! (phys < MIPS_MAX_MEM_ADDR))
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printf("pmap_zero_page(%lx) nonphys\n", (u_long)phys);
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#endif
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va = MIPS_PHYS_TO_KSEG0(phys);
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mips_pagezero((caddr_t)MIPS_PHYS_TO_KSEG0(phys));
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#if defined(MIPS3_PLUS) /* XXX mmu XXX */
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if (mips_cache_virtual_alias) {
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pv = pa_to_pvh(phys);
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if ((pv->pv_flags & PV_UNCACHED) == 0 &&
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mips_cache_indexof(pv->pv_va) != mips_cache_indexof(va))
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mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE);
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}
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#endif
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mips_pagezero((caddr_t)va);
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#if defined(MIPS3_PLUS) /* XXX mmu XXX */
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/*
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@ -1598,9 +1613,8 @@ pmap_zero_page(phys)
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*
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* XXXJRT This is totally disgusting.
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*/
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if (MIPS_HAS_R4K_MMU &&
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( (mips_sdcache_line_size == 0) || (mips_sdcache_forceinv) ) )
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mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(phys), NBPG);
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if (MIPS_HAS_R4K_MMU) /* XXX VCED on kernel stack is not allowed */
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mips_dcache_wbinv_range(va, PAGE_SIZE);
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#endif /* MIPS3_PLUS */
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}
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@ -1636,11 +1650,12 @@ pmap_copy_page(src, dst)
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* It would probably be better to map the destination as a
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* write-through no allocate to reduce cache thrash.
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*/
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if (MIPS_HAS_R4K_MMU &&
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( (mips_sdcache_line_size == 0) || (mips_sdcache_forceinv)) ) {
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if (mips_cache_virtual_alias) {
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/*XXX FIXME Not very sophisticated */
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mips_flushcache_allpvh(src);
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/* mips_flushcache_allpvh(dst); */
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#if 0
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mips_flushcache_allpvh(dst);
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#endif
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}
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#endif /* MIPS3_PLUS */
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@ -1659,10 +1674,9 @@ pmap_copy_page(src, dst)
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*
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* XXXJRT -- This is totally disgusting.
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*/
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if (MIPS_HAS_R4K_MMU &&
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( (mips_sdcache_line_size == 0) || (mips_sdcache_forceinv)) ) {
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mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(src), NBPG);
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mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(dst), NBPG);
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if (mips_cache_virtual_alias) {
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mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(src), PAGE_SIZE);
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mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(dst), PAGE_SIZE);
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}
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#endif /* MIPS3_PLUS */
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}
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@ -1891,7 +1905,7 @@ again:
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pv->pv_next = NULL;
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} else {
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#if defined(MIPS3_PLUS) /* XXX mmu XXX */
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if (MIPS_HAS_R4K_MMU && mips_sdcache_line_size == 0) {
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if (mips_cache_virtual_alias) {
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/*
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* There is at least one other VA mapping this page.
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* Check if they are cache index compatible.
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@ -2103,12 +2117,27 @@ void *
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pmap_pv_page_alloc(struct pool *pp, int flags)
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{
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struct vm_page *pg;
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paddr_t phys;
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#if defined(MIPS3_PLUS)
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pv_entry_t pv;
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#endif
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vaddr_t va;
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pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE);
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if (pg == NULL) {
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return NULL;
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}
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return ((void *)MIPS_PHYS_TO_KSEG0(VM_PAGE_TO_PHYS(pg)));
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phys = VM_PAGE_TO_PHYS(pg);
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va = MIPS_PHYS_TO_KSEG0(phys);
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#if defined(MIPS3_PLUS)
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if (mips_cache_virtual_alias) {
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pv = pa_to_pvh(phys);
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if ((pv->pv_flags & PV_UNCACHED) == 0 &&
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mips_cache_indexof(pv->pv_va) != mips_cache_indexof(va))
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mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE);
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}
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#endif
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return ((void *)va);
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}
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/*
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@ -2119,6 +2148,11 @@ pmap_pv_page_alloc(struct pool *pp, int flags)
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void
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pmap_pv_page_free(struct pool *pp, void *v)
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{
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#ifdef MIPS3_PLUS
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if (mips_cache_virtual_alias)
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mips_dcache_inv_range((vaddr_t)v, PAGE_SIZE);
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#endif
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uvm_pagefree(PHYS_TO_VM_PAGE(MIPS_KSEG0_TO_PHYS((vaddr_t)v)));
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}
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@ -2162,6 +2196,40 @@ pmap_prefer(foff, vap, td)
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}
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#endif /* MIPS3_PLUS */
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vaddr_t
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mips_pmap_map_poolpage(paddr_t pa)
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{
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vaddr_t va;
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#if defined(MIPS3_PLUS)
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pv_entry_t pv;
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#endif
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va = MIPS_PHYS_TO_KSEG0(pa);
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#if defined(MIPS3_PLUS)
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if (mips_cache_virtual_alias) {
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pv = pa_to_pvh(pa);
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if ((pv->pv_flags & PV_UNCACHED) == 0 &&
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mips_cache_indexof(pv->pv_va) != mips_cache_indexof(va))
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mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE);
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}
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#endif
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return va;
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}
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paddr_t
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mips_pmap_unmap_poolpage(vaddr_t va)
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{
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paddr_t pa;
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pa = MIPS_KSEG0_TO_PHYS(va);
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#if defined(MIPS3_PLUS)
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if (mips_cache_virtual_alias) {
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mips_dcache_inv_range(va, PAGE_SIZE);
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}
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#endif
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return pa;
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}
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/******************** page table page management ********************/
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/* TO BE DONE */
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|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: vm_machdep.c,v 1.105 2005/01/01 03:25:46 simonb Exp $ */
|
||||
/* $NetBSD: vm_machdep.c,v 1.106 2005/03/26 09:51:02 tsutsui Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1992, 1993
|
||||
|
|
@ -79,7 +79,7 @@
|
|||
#include "opt_ddb.h"
|
||||
|
||||
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
|
||||
__KERNEL_RCSID(0, "$NetBSD: vm_machdep.c,v 1.105 2005/01/01 03:25:46 simonb Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: vm_machdep.c,v 1.106 2005/03/26 09:51:02 tsutsui Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
|
|
@ -131,18 +131,6 @@ cpu_lwp_fork(struct lwp *l1, struct lwp *l2, void *stack, size_t stacksize,
|
|||
pt_entry_t *pte;
|
||||
int i, x;
|
||||
|
||||
#ifdef MIPS3_PLUS
|
||||
/*
|
||||
* To eliminate virtual aliases created by pmap_zero_page(),
|
||||
* this cache flush operation is necessary.
|
||||
* VCED on kernel stack is not allowed.
|
||||
* XXXJRT Confirm that this is necessry, and/or fix
|
||||
* XXXJRT pmap_zero_page().
|
||||
*/
|
||||
if (CPUISMIPS3 && mips_sdcache_line_size)
|
||||
mips_dcache_wbinv_range((vaddr_t) l2->l_addr, USPACE);
|
||||
#endif
|
||||
|
||||
#ifdef DIAGNOSTIC
|
||||
/*
|
||||
* If l1 != curlwp && l1 == &lwp0, we're creating a kernel thread.
|
||||
|
|
|
|||
Loading…
Reference in New Issue