Add MD DELAY and spl routines to fit Nisimura's change.

sys/arch/newsmips/include/intr.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: intr.h,v 1.1 1998/06/08 20:35:14 tsubai Exp $	*/
+/*	$NetBSD: intr.h,v 1.2 1998/08/26 12:07:21 tsubai Exp $	*/
 
 /*
  * Copyright (c) 1998 Jonathan Stone.  All rights reserved.
@@ -33,8 +33,6 @@
 #ifndef _MACHINE_INTR_H_
 #define _MACHINE_INTR_H_
 
-#include <mips/intr.h>
-
 #define	IPL_NONE	0	/* disable only this interrupt */
 #define	IPL_BIO		1	/* disable block I/O interrupts */
 #define	IPL_NET		2	/* disable network interrupts */
@@ -42,33 +40,57 @@
 #define	IPL_CLOCK	4	/* disable clock interrupts */
 #define	IPL_STATCLOCK	5	/* disable profiling interrupts */
 #define	IPL_SERIAL	6	/* disable serial hardware interrupts */
-#define	IPL_DMA		7	/* disable DMA reload interrupts */
+#define	IPL_HIGH	7	/* disable all interrupts */
-#define	IPL_HIGH	8	/* disable all interrupts */
+
+#ifndef _LOCORE
+
+#define splbio cpu_spl0
+#define splnet cpu_spl1
+#define spltty cpu_spl1
+#define splimp cpu_spl1
+#define splclock cpu_spl2
+#define splstatclock cpu_spl2
+
+extern void setsoftnet __P((void)), clearsoftnet __P((void));
+extern void setsoftclock __P((void)), clearsoftclock __P((void));
+
+extern int splhigh __P((void));
+extern int splclock __P((void));
+extern int splstatclock __P((void));
+extern int splimp __P((void));
+extern int spltty __P((void));
+extern int splnet __P((void));
+extern int splbio __P((void));
+extern int splsoftnet __P((void));
+extern int splsoftclock __P((void));
+extern int spl0 __P((void));
+extern void splx __P((int));
+
 
 /*
  * Index into intrcnt[], which is defined in locore
  */
-typedef enum {
+#define SOFTCLOCK_INTR	0
-	SOFTCLOCK_INTR = 0,
+#define SOFTNET_INTR	1
-	SOFTNET_INTR,
+#define SERIAL0_INTR	2
-	SERIAL0_INTR,
+#define SERIAL1_INTR	3
-	SERIAL1_INTR,
+#define SERIAL2_INTR	4
-	SERIAL2_INTR,
+#define LANCE_INTR	5
-	LANCE_INTR,
+#define SCSI_INTR	6
-	SCSI_INTR,
+#define ERROR_INTR	7
-	ERROR_INTR,
+#define HARDCLOCK_INTR	8
-	HARDCLOCK_INTR,
+#define FPU_INTR	9
-  	FPU_INTR,
+#define SLOT1_INTR	10
-	SLOT1_INTR,
+#define SLOT2_INTR	11
-	SLOT2_INTR,
+#define SLOT3_INTR	12
-	SLOT3_INTR,
+#define FLOPPY_INTR	13
-	FLOPPY_INTR,
+#define STRAY_INTR	14
-	STRAY_INTR
-} newsmips_intr_t;
-
-extern int news3400_intr
-		__P((u_int mask, u_int pc, u_int statusReg, u_int causeReg));
 
 extern u_int intrcnt[];
 
+/* handle i/o device interrupts */
+extern int (*mips_hardware_intr) __P((u_int, u_int, u_int, u_int));
+extern int news3400_intr __P((u_int, u_int, u_int, u_int));
+
+#endif /* !_LOCORE */
 #endif /* _MACHINE_INTR_H_ */

sys/arch/newsmips/include/param.h

@@ -1,4 +1,4 @@
-/*	from $NetBSD: param.h,v 1.3 1998/04/29 23:11:01 thorpej Exp $	*/
+/*	from $NetBSD: param.h,v 1.4 1998/08/26 12:07:21 tsubai Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -98,3 +98,15 @@
 #define	NMBCLUSTERS	1024		/* map size, max cluster allocation */
 #endif
 #endif
+
+#include <machine/intr.h>
+
+#ifdef _KERNEL
+#ifndef _LOCORE
+
+extern void delay __P((int n));
+extern int cpuspeed;
+#define DELAY(n) { register int N = cpuspeed * (n); while (--N > 0); }
+
+#endif	/* !_LOCORE */
+#endif	/* _KERNEL */

sys/arch/newsmips/newsmips/locore_machdep.S

@@ -1,4 +1,4 @@
-/*	$NetBSD: locore_machdep.S,v 1.2 1998/06/08 21:27:10 tsubai Exp $	*/
+/*	$NetBSD: locore_machdep.S,v 1.3 1998/08/26 12:07:21 tsubai Exp $	*/
 
 /*
  * Copyright (c) 1992, 1993
@@ -79,6 +79,262 @@ LEAF(to_monitor)
 	nop
 END(to_monitor)
 
+/*
+ * Set/clear software interrupt routines.
+ */
+
+LEAF(setsoftclock)
+	mfc0	v1, MIPS_COP_0_STATUS_REG	# save status register
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# disable interrupts (2 cycles)
+	nop
+	mfc0	v0, MIPS_COP_0_CAUSE_REG	# read cause register
+	nop
+	or	v0, v0, MIPS_SOFT_INT_MASK_0	# set soft clock interrupt
+	mtc0	v0, MIPS_COP_0_CAUSE_REG	# save it
+	mtc0	v1, MIPS_COP_0_STATUS_REG
+	j	ra
+	nop
+END(setsoftclock)
+
+LEAF(clearsoftclock)
+	mfc0	v1, MIPS_COP_0_STATUS_REG	# save status register
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# disable interrupts (2 cycles)
+	nop
+	nop
+	mfc0	v0, MIPS_COP_0_CAUSE_REG	# read cause register
+	nop
+	and	v0, v0, ~MIPS_SOFT_INT_MASK_0	# clear soft clock interrupt
+	mtc0	v0, MIPS_COP_0_CAUSE_REG	# save it
+	mtc0	v1, MIPS_COP_0_STATUS_REG
+	j	ra
+	nop
+END(clearsoftclock)
+
+LEAF(setsoftnet)
+	mfc0	v1, MIPS_COP_0_STATUS_REG	# save status register
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# disable interrupts (2 cycles)
+	nop
+	nop
+	mfc0	v0, MIPS_COP_0_CAUSE_REG	# read cause register
+	nop
+	or	v0, v0, MIPS_SOFT_INT_MASK_1	# set soft net interrupt
+	mtc0	v0, MIPS_COP_0_CAUSE_REG	# save it
+	mtc0	v1, MIPS_COP_0_STATUS_REG
+	j	ra
+	nop
+END(setsoftnet)
+
+LEAF(clearsoftnet)
+	mfc0	v1, MIPS_COP_0_STATUS_REG	# save status register
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# disable interrupts (2 cycles)
+	nop
+	nop
+	mfc0	v0, MIPS_COP_0_CAUSE_REG	# read cause register
+	nop
+	and	v0, v0, ~MIPS_SOFT_INT_MASK_1	# clear soft net interrupt
+	mtc0	v0, MIPS_COP_0_CAUSE_REG	# save it
+	mtc0	v1, MIPS_COP_0_STATUS_REG
+	j	ra
+	nop
+END(clearsoftnet)
+
+/*
+ * Set/change interrupt priority routines.
+ */
+
+LEAF(spl0)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	nop
+	or	t0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# enable all interrupts
+	j	ra
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+END(spl0)
+
+LEAF(splsoftclock)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~MIPS_SOFT_INT_MASK_0	# disable soft clock
+	and	t0, t0, v0
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
+	nop					# 3 ins to disable on r4x00
+	j	ra
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+END(splsoftclock)
+
+LEAF(splsoftnet)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~(MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
+	and	t0, t0, v0
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
+	j	ra
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+END(splsoftnet)
+
+/*
+ * hardware-level spls for hardware where the device interrupt priorites
+ * are ordered, and map onto mips interrupt pins in increasing priority.
+ * This maps directly onto BSD spl levels.
+ */
+
+/*
+ * Block out int2 (hardware interrupt 0) and lower mips levels.
+ */
+LEAF(cpu_spl0)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~(MIPS_INT_MASK_SPL0)
+	and	t0, t0, v0
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
+	nop					# 3 ins to disable on r4x00
+	j	ra
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+END(cpu_spl0)
+
+/*
+ * Block out Int3 (hardware interrupt 1) and lower mips levels.
+ */
+LEAF(cpu_spl1)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~(MIPS_INT_MASK_SPL1)
+	and	t0, t0, v0
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
+	nop					# 3 ins to disable on r4x00
+	j	ra
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+END(cpu_spl1)
+
+LEAF(cpu_spl2)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~(MIPS_INT_MASK_SPL2)
+	and	t0, t0, v0
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
+	nop					# 3 ins to disable on r4x00
+	j	ra
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+END(cpu_spl2)
+
+LEAF(cpu_spl3)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~(MIPS_INT_MASK_SPL3)
+	and	t0, t0, v0
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
+	nop					# 3 ins to disable on r4x00
+	j	ra
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+END(cpu_spl3)
+
+LEAF(cpu_spl4)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~(MIPS_INT_MASK_SPL4)
+
+	and	t0, t0, v0
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
+	nop					# 3 ins to disable
+	j	ra
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+END(cpu_spl4)
+
+LEAF(cpu_spl5)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~(MIPS_INT_MASK_SPL5)
+	and	t0, t0, v0
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
+	nop					# 3 ins to disable
+	j	ra
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+END(cpu_spl5)
+
+/*
+ * hardware-level spls for hardware where the interrupt priorites
+ * DO NOT map onto levels.  
+ */
+LEAF(Mach_spl0)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~(MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
+	and	t0, t0, v0
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
+	nop					# 3 ins to disable on r4x00
+	j	ra
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+END(Mach_spl0)
+
+LEAF(Mach_spl1)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~(MIPS_INT_MASK_1|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
+	and	t0, t0, v0
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
+	nop					# 3 ins to disable on r4x00
+	j	ra
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+END(Mach_spl1)
+
+LEAF(Mach_spl2)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~(MIPS_INT_MASK_2|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
+	and	t0, t0, v0
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
+	nop					# 3 ins to disable on r4x00
+	j	ra
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+END(Mach_spl2)
+
+LEAF(Mach_spl3)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~(MIPS_INT_MASK_3|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
+	and	t0, t0, v0
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
+	nop					# 3 ins to disable on r4x00
+	j	ra
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+END(Mach_spl3)
+
+LEAF(Mach_spl4)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~(MIPS_INT_MASK_4|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
+	and	t0, t0, v0
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
+	nop					# 3 ins to disable
+	j	ra
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+END(Mach_spl4)
+
+LEAF(Mach_spl5)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~(MIPS_INT_MASK_5|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
+	and	t0, t0, v0
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
+	nop					# 3 ins to disable
+	j	ra
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+END(Mach_spl5)
+
+/*
+ * We define an alternate entry point after mcount is called so it
+ * can be used in mcount without causeing a recursive loop.
+ */
+LEAF(splhigh)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~MIPS_SR_INT_IE	# disable all interrupts
+	and	t0, t0, v0
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
+	nop					# 3 ins to disable on r4x00
+	j	ra
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+END(splhigh)
+
+/*
+ * Restore saved interrupt mask.
+ */
+LEAF(splx)
+	mfc0	v0, MIPS_COP_0_STATUS_REG
+	li	t0, ~(MIPS_INT_MASK | MIPS_SR_INT_IE)
+	and	t0, t0, v0
+	or	t0, t0, a0
+	mtc0	t0, MIPS_COP_0_STATUS_REG
+	nop					# 3 ins to disable
+	j	ra
+	nop
+END(splx)
+
 /*
  * Interrupt counters for vmstat.
  */