Add MD DELAY and spl routines to fit Nisimura's change.
This commit is contained in:
tsubai
parent
1c3e72cd0e
commit
a890d2dd7f
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@ -1,4 +1,4 @@
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/* $NetBSD: intr.h,v 1.1 1998/06/08 20:35:14 tsubai Exp $ */
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/* $NetBSD: intr.h,v 1.2 1998/08/26 12:07:21 tsubai Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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@ -33,8 +33,6 @@
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#ifndef _MACHINE_INTR_H_
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#define _MACHINE_INTR_H_
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#include <mips/intr.h>
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#define IPL_NONE 0 /* disable only this interrupt */
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#define IPL_BIO 1 /* disable block I/O interrupts */
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#define IPL_NET 2 /* disable network interrupts */
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@ -42,33 +40,57 @@
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#define IPL_CLOCK 4 /* disable clock interrupts */
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#define IPL_STATCLOCK 5 /* disable profiling interrupts */
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#define IPL_SERIAL 6 /* disable serial hardware interrupts */
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#define IPL_DMA 7 /* disable DMA reload interrupts */
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#define IPL_HIGH 8 /* disable all interrupts */
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#define IPL_HIGH 7 /* disable all interrupts */
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#ifndef _LOCORE
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#define splbio cpu_spl0
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#define splnet cpu_spl1
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#define spltty cpu_spl1
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#define splimp cpu_spl1
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#define splclock cpu_spl2
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#define splstatclock cpu_spl2
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extern void setsoftnet __P((void)), clearsoftnet __P((void));
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extern void setsoftclock __P((void)), clearsoftclock __P((void));
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extern int splhigh __P((void));
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extern int splclock __P((void));
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extern int splstatclock __P((void));
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extern int splimp __P((void));
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extern int spltty __P((void));
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extern int splnet __P((void));
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extern int splbio __P((void));
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extern int splsoftnet __P((void));
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extern int splsoftclock __P((void));
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extern int spl0 __P((void));
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extern void splx __P((int));
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/*
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* Index into intrcnt[], which is defined in locore
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*/
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typedef enum {
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SOFTCLOCK_INTR = 0,
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SOFTNET_INTR,
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SERIAL0_INTR,
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SERIAL1_INTR,
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SERIAL2_INTR,
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LANCE_INTR,
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SCSI_INTR,
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ERROR_INTR,
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HARDCLOCK_INTR,
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FPU_INTR,
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SLOT1_INTR,
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SLOT2_INTR,
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SLOT3_INTR,
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FLOPPY_INTR,
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STRAY_INTR
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} newsmips_intr_t;
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extern int news3400_intr
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__P((u_int mask, u_int pc, u_int statusReg, u_int causeReg));
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#define SOFTCLOCK_INTR 0
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#define SOFTNET_INTR 1
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#define SERIAL0_INTR 2
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#define SERIAL1_INTR 3
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#define SERIAL2_INTR 4
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#define LANCE_INTR 5
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#define SCSI_INTR 6
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#define ERROR_INTR 7
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#define HARDCLOCK_INTR 8
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#define FPU_INTR 9
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#define SLOT1_INTR 10
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#define SLOT2_INTR 11
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#define SLOT3_INTR 12
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#define FLOPPY_INTR 13
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#define STRAY_INTR 14
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extern u_int intrcnt[];
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/* handle i/o device interrupts */
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extern int (*mips_hardware_intr) __P((u_int, u_int, u_int, u_int));
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extern int news3400_intr __P((u_int, u_int, u_int, u_int));
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#endif /* !_LOCORE */
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#endif /* _MACHINE_INTR_H_ */
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@ -1,4 +1,4 @@
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/* from $NetBSD: param.h,v 1.3 1998/04/29 23:11:01 thorpej Exp $ */
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/* from $NetBSD: param.h,v 1.4 1998/08/26 12:07:21 tsubai Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -98,3 +98,15 @@
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#define NMBCLUSTERS 1024 /* map size, max cluster allocation */
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#endif
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#endif
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#include <machine/intr.h>
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#ifdef _KERNEL
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#ifndef _LOCORE
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extern void delay __P((int n));
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extern int cpuspeed;
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#define DELAY(n) { register int N = cpuspeed * (n); while (--N > 0); }
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#endif /* !_LOCORE */
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#endif /* _KERNEL */
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@ -1,4 +1,4 @@
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/* $NetBSD: locore_machdep.S,v 1.2 1998/06/08 21:27:10 tsubai Exp $ */
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/* $NetBSD: locore_machdep.S,v 1.3 1998/08/26 12:07:21 tsubai Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -79,6 +79,262 @@ LEAF(to_monitor)
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nop
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END(to_monitor)
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/*
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* Set/clear software interrupt routines.
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*/
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LEAF(setsoftclock)
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mfc0 v1, MIPS_COP_0_STATUS_REG # save status register
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mtc0 zero, MIPS_COP_0_STATUS_REG # disable interrupts (2 cycles)
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nop
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mfc0 v0, MIPS_COP_0_CAUSE_REG # read cause register
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nop
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or v0, v0, MIPS_SOFT_INT_MASK_0 # set soft clock interrupt
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mtc0 v0, MIPS_COP_0_CAUSE_REG # save it
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mtc0 v1, MIPS_COP_0_STATUS_REG
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j ra
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nop
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END(setsoftclock)
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LEAF(clearsoftclock)
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mfc0 v1, MIPS_COP_0_STATUS_REG # save status register
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mtc0 zero, MIPS_COP_0_STATUS_REG # disable interrupts (2 cycles)
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nop
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nop
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mfc0 v0, MIPS_COP_0_CAUSE_REG # read cause register
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nop
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and v0, v0, ~MIPS_SOFT_INT_MASK_0 # clear soft clock interrupt
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mtc0 v0, MIPS_COP_0_CAUSE_REG # save it
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mtc0 v1, MIPS_COP_0_STATUS_REG
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j ra
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nop
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END(clearsoftclock)
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LEAF(setsoftnet)
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mfc0 v1, MIPS_COP_0_STATUS_REG # save status register
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mtc0 zero, MIPS_COP_0_STATUS_REG # disable interrupts (2 cycles)
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nop
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nop
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mfc0 v0, MIPS_COP_0_CAUSE_REG # read cause register
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nop
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or v0, v0, MIPS_SOFT_INT_MASK_1 # set soft net interrupt
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mtc0 v0, MIPS_COP_0_CAUSE_REG # save it
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mtc0 v1, MIPS_COP_0_STATUS_REG
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j ra
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nop
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END(setsoftnet)
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LEAF(clearsoftnet)
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mfc0 v1, MIPS_COP_0_STATUS_REG # save status register
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mtc0 zero, MIPS_COP_0_STATUS_REG # disable interrupts (2 cycles)
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nop
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nop
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mfc0 v0, MIPS_COP_0_CAUSE_REG # read cause register
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nop
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and v0, v0, ~MIPS_SOFT_INT_MASK_1 # clear soft net interrupt
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mtc0 v0, MIPS_COP_0_CAUSE_REG # save it
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mtc0 v1, MIPS_COP_0_STATUS_REG
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j ra
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nop
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END(clearsoftnet)
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/*
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* Set/change interrupt priority routines.
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*/
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LEAF(spl0)
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mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
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nop
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or t0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
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mtc0 t0, MIPS_COP_0_STATUS_REG # enable all interrupts
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j ra
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and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
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END(spl0)
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LEAF(splsoftclock)
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mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
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li t0, ~MIPS_SOFT_INT_MASK_0 # disable soft clock
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and t0, t0, v0
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mtc0 t0, MIPS_COP_0_STATUS_REG # save it
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nop # 3 ins to disable on r4x00
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j ra
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and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
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END(splsoftclock)
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LEAF(splsoftnet)
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mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
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li t0, ~(MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
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and t0, t0, v0
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mtc0 t0, MIPS_COP_0_STATUS_REG # save it
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j ra
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and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
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END(splsoftnet)
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/*
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* hardware-level spls for hardware where the device interrupt priorites
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* are ordered, and map onto mips interrupt pins in increasing priority.
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* This maps directly onto BSD spl levels.
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*/
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/*
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* Block out int2 (hardware interrupt 0) and lower mips levels.
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*/
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LEAF(cpu_spl0)
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mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
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li t0, ~(MIPS_INT_MASK_SPL0)
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and t0, t0, v0
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mtc0 t0, MIPS_COP_0_STATUS_REG # save it
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nop # 3 ins to disable on r4x00
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j ra
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and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
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END(cpu_spl0)
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/*
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* Block out Int3 (hardware interrupt 1) and lower mips levels.
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*/
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LEAF(cpu_spl1)
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mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
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li t0, ~(MIPS_INT_MASK_SPL1)
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and t0, t0, v0
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mtc0 t0, MIPS_COP_0_STATUS_REG # save it
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nop # 3 ins to disable on r4x00
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j ra
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and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
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END(cpu_spl1)
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LEAF(cpu_spl2)
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mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
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li t0, ~(MIPS_INT_MASK_SPL2)
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and t0, t0, v0
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mtc0 t0, MIPS_COP_0_STATUS_REG # save it
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nop # 3 ins to disable on r4x00
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j ra
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and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
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END(cpu_spl2)
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LEAF(cpu_spl3)
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mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
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li t0, ~(MIPS_INT_MASK_SPL3)
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and t0, t0, v0
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mtc0 t0, MIPS_COP_0_STATUS_REG # save it
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nop # 3 ins to disable on r4x00
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j ra
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and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
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END(cpu_spl3)
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LEAF(cpu_spl4)
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mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
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li t0, ~(MIPS_INT_MASK_SPL4)
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and t0, t0, v0
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mtc0 t0, MIPS_COP_0_STATUS_REG # save it
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nop # 3 ins to disable
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j ra
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and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
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END(cpu_spl4)
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LEAF(cpu_spl5)
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mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
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li t0, ~(MIPS_INT_MASK_SPL5)
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and t0, t0, v0
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mtc0 t0, MIPS_COP_0_STATUS_REG # save it
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nop # 3 ins to disable
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j ra
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and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
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END(cpu_spl5)
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/*
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* hardware-level spls for hardware where the interrupt priorites
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* DO NOT map onto levels.
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*/
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LEAF(Mach_spl0)
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mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
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li t0, ~(MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
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and t0, t0, v0
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mtc0 t0, MIPS_COP_0_STATUS_REG # save it
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nop # 3 ins to disable on r4x00
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j ra
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and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
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END(Mach_spl0)
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LEAF(Mach_spl1)
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mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
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li t0, ~(MIPS_INT_MASK_1|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
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and t0, t0, v0
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mtc0 t0, MIPS_COP_0_STATUS_REG # save it
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nop # 3 ins to disable on r4x00
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j ra
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and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
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END(Mach_spl1)
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LEAF(Mach_spl2)
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mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
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li t0, ~(MIPS_INT_MASK_2|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
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and t0, t0, v0
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mtc0 t0, MIPS_COP_0_STATUS_REG # save it
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nop # 3 ins to disable on r4x00
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j ra
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and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
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END(Mach_spl2)
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LEAF(Mach_spl3)
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mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
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li t0, ~(MIPS_INT_MASK_3|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
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and t0, t0, v0
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mtc0 t0, MIPS_COP_0_STATUS_REG # save it
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nop # 3 ins to disable on r4x00
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j ra
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and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
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END(Mach_spl3)
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LEAF(Mach_spl4)
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mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
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li t0, ~(MIPS_INT_MASK_4|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
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and t0, t0, v0
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mtc0 t0, MIPS_COP_0_STATUS_REG # save it
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nop # 3 ins to disable
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j ra
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and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
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END(Mach_spl4)
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LEAF(Mach_spl5)
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mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
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li t0, ~(MIPS_INT_MASK_5|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
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and t0, t0, v0
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mtc0 t0, MIPS_COP_0_STATUS_REG # save it
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nop # 3 ins to disable
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j ra
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and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
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END(Mach_spl5)
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/*
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* We define an alternate entry point after mcount is called so it
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* can be used in mcount without causeing a recursive loop.
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*/
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LEAF(splhigh)
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mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
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li t0, ~MIPS_SR_INT_IE # disable all interrupts
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and t0, t0, v0
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mtc0 t0, MIPS_COP_0_STATUS_REG # save it
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nop # 3 ins to disable on r4x00
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j ra
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and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
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END(splhigh)
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/*
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* Restore saved interrupt mask.
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*/
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LEAF(splx)
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mfc0 v0, MIPS_COP_0_STATUS_REG
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li t0, ~(MIPS_INT_MASK | MIPS_SR_INT_IE)
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and t0, t0, v0
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or t0, t0, a0
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mtc0 t0, MIPS_COP_0_STATUS_REG
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nop # 3 ins to disable
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j ra
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nop
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END(splx)
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/*
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* Interrupt counters for vmstat.
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*/
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