Replacement of the NCR driver by the Leo Weppelman NCR driver as
ported by Matthias Pfaller (Thanks to both!) and a RCS id.
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/* $NetBSD: ncr_5380.h,v 1.2 1994/10/26 08:24:13 cgd Exp $ */
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/*
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* Mach Operating System
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* Copyright (c) 1991,1990,1989 Carnegie Mellon University
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
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* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/*
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* File: scsi_5380.h
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* Author: Alessandro Forin, Carnegie Mellon University
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* Date: 5/91
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*
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* Defines for the NCR 5380 (SCSI chip), aka Am5380
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*
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* Modified for the pc532 by Phil Nelson. 1/94
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*/
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/*
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* Register map
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*/
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typedef struct {
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volatile unsigned char sci_data; /* r: Current data */
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#define sci_odata sci_data /* w: Out data */
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volatile unsigned char sci_icmd; /* rw: Initiator command */
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volatile unsigned char sci_mode; /* rw: Mode */
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volatile unsigned char sci_tcmd; /* rw: Target command */
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volatile unsigned char sci_bus_csr; /* r: Bus Status */
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#define sci_sel_enb sci_bus_csr /* w: Select enable */
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volatile unsigned char sci_csr; /* r: Status */
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#define sci_dma_send sci_csr /* w: Start dma send data */
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volatile unsigned char sci_idata; /* r: Input data */
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#define sci_trecv sci_idata /* w: Start dma receive, target */
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volatile unsigned char sci_iack; /* r: Interrupt Acknowledge */
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#define sci_irecv sci_iack /* w: Start dma receive, initiator */
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} sci_regmap_t;
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/*
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* Initiator command register
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*/
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#define SCI_ICMD_DATA 0x01 /* rw: Assert data bus */
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#define SCI_ICMD_ATN 0x02 /* rw: Assert ATN signal */
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#define SCI_ICMD_SEL 0x04 /* rw: Assert SEL signal */
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#define SCI_ICMD_BSY 0x08 /* rw: Assert BSY signal */
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#define SCI_ICMD_ACK 0x10 /* rw: Assert ACK signal */
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#define SCI_ICMD_LST 0x20 /* r: Lost arbitration */
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#define SCI_ICMD_DIFF SCI_ICMD_LST /* w: Differential cable */
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#define SCI_ICMD_AIP 0x40 /* r: Arbitration in progress */
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#define SCI_ICMD_TEST SCI_ICMD_AIP /* w: Test mode */
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#define SCI_ICMD_RST 0x80 /* rw: Assert RST signal */
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/*
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* Mode register
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*/
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#define SCI_MODE_ARB 0x01 /* rw: Start arbitration */
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#define SCI_MODE_DMA 0x02 /* rw: Enable DMA xfers */
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#define SCI_MODE_MONBSY 0x04 /* rw: Monitor BSY signal */
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#define SCI_MODE_DMA_IE 0x08 /* rw: Enable DMA complete interrupt */
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#define SCI_MODE_PERR_IE 0x10 /* rw: Interrupt on parity errors */
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#define SCI_MODE_PAR_CHK 0x20 /* rw: Check parity */
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#define SCI_MODE_TARGET 0x40 /* rw: Target mode (Initiator if 0) */
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#define SCI_MODE_BLOCKDMA 0x80 /* rw: Block-mode DMA handshake (MBZ) */
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/*
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* Target command register
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*/
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#define SCI_TCMD_IO 0x01 /* rw: Assert I/O signal */
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#define SCI_TCMD_CD 0x02 /* rw: Assert C/D signal */
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#define SCI_TCMD_MSG 0x04 /* rw: Assert MSG signal */
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#define SCI_TCMD_PHASE_MASK 0x07 /* r: Mask for current bus phase */
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#define SCI_TCMD_REQ 0x08 /* rw: Assert REQ signal */
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#define SCI_TCMD_LAST_SENT 0x80 /* ro: Last byte was xferred
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* (not on 5380/1) */
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#define SCI_PHASE(x) SCSI_PHASE(x)
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/*
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* Current (SCSI) Bus status
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*/
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#define SCI_BUS_DBP 0x01 /* r: Data Bus parity */
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#define SCI_BUS_SEL 0x02 /* r: SEL signal */
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#define SCI_BUS_IO 0x04 /* r: I/O signal */
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#define SCI_BUS_CD 0x08 /* r: C/D signal */
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#define SCI_BUS_MSG 0x10 /* r: MSG signal */
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#define SCI_BUS_REQ 0x20 /* r: REQ signal */
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#define SCI_BUS_BSY 0x40 /* r: BSY signal */
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#define SCI_BUS_RST 0x80 /* r: RST signal */
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#define SCI_CUR_PHASE(x) SCSI_PHASE((x)>>2)
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/*
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* Bus and Status register
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*/
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#define SCI_CSR_ACK 0x01 /* r: ACK signal */
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#define SCI_CSR_ATN 0x02 /* r: ATN signal */
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#define SCI_CSR_DISC 0x04 /* r: Disconnected (BSY==0) */
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#define SCI_CSR_PHASE_MATCH 0x08 /* r: Bus and SCI_TCMD match */
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#define SCI_CSR_INT 0x10 /* r: Interrupt request */
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#define SCI_CSR_PERR 0x20 /* r: Parity error */
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#define SCI_CSR_DREQ 0x40 /* r: DMA request */
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#define SCI_CSR_DONE 0x80 /* r: DMA count is zero */
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/* icu scsi chip switching */
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#define ICU_ADR 0xfffffe00
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#define ICU_IO (ICU_ADR+20)
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#define ICU_DIR (ICU_ADR+21)
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#define ICU_DATA (ICU_ADR+19)
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#define ICU_SCSI_BIT 0x80
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@ -1,57 +0,0 @@
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/* $NetBSD: ncr_defs.h,v 1.2 1994/10/26 08:24:14 cgd Exp $ */
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/*-
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* Copyright (C) 1993 Allen K. Briggs, Chris P. Caputo,
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* Michael L. Finch, Bradley A. Grantham, and
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* Lawrence A. Kesteloot
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the Alice Group.
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* 4. The names of the Alice Group or any of its members may not be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE ALICE GROUP ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE ALICE GROUP BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SCSI_DEFS_H
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#define _SCSI_DEFS_H
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#define SCSI_PHASE_DATA_OUT 0x0
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#define SCSI_PHASE_DATA_IN 0x1
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#define SCSI_PHASE_CMD 0x2
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#define SCSI_PHASE_STATUS 0x3
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#define SCSI_PHASE_UNSPEC1 0x4
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#define SCSI_PHASE_UNSPEC2 0x5
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#define SCSI_PHASE_MESSAGE_OUT 0x6
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#define SCSI_PHASE_MESSAGE_IN 0x7
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#define SCSI_PHASE(x) ((x)&0x7)
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/* These should be fixed up. */
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#define SCSI_RET_SUCCESS 0
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#define SCSI_RET_RETRY 1
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#define SCSI_RET_DEVICE_DOWN 2
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#define SCSI_RET_COMMAND_FAIL 3
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#endif
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145
sys/arch/pc532/dev/ncrreg.h
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145
sys/arch/pc532/dev/ncrreg.h
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/* $NetBSD: ncrreg.h,v 1.1 1995/06/09 04:36:26 phil Exp $ */
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/*
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* Copyright (c) 1995 Leo Weppelman.
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* PC532-Port by Matthias Pfaller.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Leo Weppelman.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _NCR5380REG_H
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#define _NCR5380REG_H
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#define PDMA_ADDRESS ((volatile u_char *) 0xffe00000)
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#define SCSI_5380 ((volatile struct scsi_5380 *) 0xffd00000)
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struct scsi_5380 {
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volatile u_char scsi_5380[8]; /* use only the odd bytes */
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};
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#define scsi_data scsi_5380[0] /* Data register */
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#define scsi_icom scsi_5380[1] /* Initiator command register */
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#define scsi_mode scsi_5380[2] /* Mode register */
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#define scsi_tcom scsi_5380[3] /* Target command register */
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#define scsi_idstat scsi_5380[4] /* Bus status register */
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#define scsi_dmstat scsi_5380[5] /* DMA status register */
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#define scsi_trcv scsi_5380[6] /* Target receive register */
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#define scsi_ircv scsi_5380[7] /* Initiator receive register */
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/*
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* Definitions for Initiator command register.
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*/
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#define SC_A_RST 0x80 /* RW - Assert RST */
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#define SC_TEST 0x40 /* W - Test mode */
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#define SC_AIP 0x40 /* R - Arbitration in progress */
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#define SC_LA 0x20 /* R - Lost arbitration */
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#define SC_A_ACK 0x10 /* RW - Assert ACK */
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#define SC_A_BSY 0x08 /* RW - Assert BSY */
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#define SC_A_SEL 0x04 /* RW - Assert SEL */
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#define SC_A_ATN 0x02 /* RW - Assert ATN */
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#define SC_ADTB 0x01 /* RW - Assert Data To Bus */
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/*
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* Definitions for mode register
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*/
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#define SC_B_DMA 0x80 /* RW - Block mode DMA (not on TT!) */
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#define SC_T_MODE 0x40 /* RW - Target mode */
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#define SC_E_PAR 0x20 /* RW - Enable parity check */
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#define SC_E_PARI 0x10 /* RW - Enable parity interrupt */
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#define SC_E_EOPI 0x08 /* RW - Enable End Of Process Interrupt */
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#define SC_MON_BSY 0x04 /* RW - Monitor BSY */
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#define SC_M_DMA 0x02 /* RW - Set DMA mode */
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#define SC_ARBIT 0x01 /* RW - Arbitrate */
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/*
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* Definitions for tcom register
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*/
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#define SC_LBS 0x80 /* RW - Last Byte Send (not on TT!) */
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#define SC_A_REQ 0x08 /* RW - Assert REQ */
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#define SC_A_MSG 0x04 /* RW - Assert MSG */
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#define SC_A_CD 0x02 /* RW - Assert C/D */
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#define SC_A_IO 0x01 /* RW - Assert I/O */
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/*
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* Definitions for idstat register
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*/
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#define SC_S_RST 0x80 /* R - RST is set */
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#define SC_S_BSY 0x40 /* R - BSY is set */
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#define SC_S_REQ 0x20 /* R - REQ is set */
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#define SC_S_MSG 0x10 /* R - MSG is set */
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#define SC_S_CD 0x08 /* R - C/D is set */
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#define SC_S_IO 0x04 /* R - I/O is set */
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#define SC_S_SEL 0x02 /* R - SEL is set */
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#define SC_S_PAR 0x01 /* R - Parity bit */
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/*
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* Definitions for dmastat register
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*/
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#define SC_END_DMA 0x80 /* R - End of DMA */
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#define SC_DMA_REQ 0x40 /* R - DMA request */
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#define SC_PAR_ERR 0x20 /* R - Parity error */
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#define SC_IRQ_SET 0x10 /* R - IRQ is active */
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#define SC_PHS_MTCH 0x08 /* R - Phase Match */
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#define SC_BSY_ERR 0x04 /* R - Busy error */
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#define SC_ATN_STAT 0x02 /* R - State of ATN line */
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#define SC_ACK_STAT 0x01 /* R - State of ACK line */
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#define SC_S_SEND 0x00 /* W - Start DMA output */
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#define SC_CLINT { /* Clear interrupts */ \
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int i = SCSI_5380->scsi_ircv; \
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}
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/*
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* Definition of SCSI-bus phases. The values are determined by signals
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* on the SCSI-bus. DO NOT CHANGE!
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* The values must be used to index the pointers in SCSI-PARMS.
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*/
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#define NR_PHASE 8
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#define PH_DATAOUT 0
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#define PH_DATAIN 1
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#define PH_CMD 2
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#define PH_STATUS 3
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#define PH_RES1 4
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#define PH_RES2 5
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#define PH_MSGOUT 6
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#define PH_MSGIN 7
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#define PH_OUT(phase) (!(phase & 1)) /* TRUE if output phase */
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#define PH_IN(phase) (phase & 1) /* TRUE if input phase */
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/*
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* Id of Host-adapter
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*/
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#define SC_HOST_ID 0x80
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/*
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* Base setting for 5380 mode register
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*/
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#define IMODE_BASE SC_E_PAR
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#endif /* _NCR5380REG_H */
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@ -1,4 +1,4 @@
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/* $NetBSD: scn.c,v 1.17 1995/05/16 07:30:38 phil Exp $ */
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/* $NetBSD: scn.c,v 1.18 1995/06/09 04:36:30 phil Exp $ */
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/*-
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* Copyright (c) 1991 The Regents of the University of California.
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