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Adapt SMC 93cx6 library so that it will work with both 8- and 32-bit 

registers.  This is so that I can read an SMC 93cx6 through the
32-bit registers of the ADMtek ADM8211 802.11 wireless MAC.

Adapt aic to choose 8-bit registers.
This commit is contained in:
dyoung 2003-05-02 19:12:19 +00:00
parent 36664b74fa
commit a7d738c524
3 changed files with 50 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
sys/dev/ic/aic7xxx_seeprom.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: aic7xxx_seeprom.c,v 1.7 2003/04/19 19:33:30 fvdl Exp $ */
/* $NetBSD: aic7xxx_seeprom.c,v 1.8 2003/05/02 19:12:19 dyoung Exp $ */
/*
* Product specific probe and attach routines for:
@ -46,13 +46,13 @@
* from the FreeBSD source file aic7xxx_pci.c by Frank van der Linden
* <fvdl@netbsd.org>
*
* $Id: aic7xxx_seeprom.c,v 1.7 2003/04/19 19:33:30 fvdl Exp $
* $Id: aic7xxx_seeprom.c,v 1.8 2003/05/02 19:12:19 dyoung Exp $
*
* $FreeBSD: src/sys/dev/aic7xxx/aic7xxx_pci.c,v 1.22 2003/01/20 20:44:55 gibbs Exp $
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: aic7xxx_seeprom.c,v 1.7 2003/04/19 19:33:30 fvdl Exp $");
__KERNEL_RCSID(0, "$NetBSD: aic7xxx_seeprom.c,v 1.8 2003/05/02 19:12:19 dyoung Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -104,6 +104,7 @@ ahc_check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
sd.sd_tag = ahc->tag;
sd.sd_bsh = ahc->bsh;
sd.sd_regsize = 1;
sd.sd_control_offset = SEECTL;
sd.sd_status_offset = SEECTL;
sd.sd_dataout_offset = SEECTL;

20
sys/dev/ic/smc93cx6.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: smc93cx6.c,v 1.9 2001/11/13 13:14:45 lukem Exp $ */
/* $NetBSD: smc93cx6.c,v 1.10 2003/05/02 19:12:19 dyoung Exp $ */
/*
* Interface for the 93C66/56/46/26/06 serial eeprom parts.
@ -58,7 +58,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: smc93cx6.c,v 1.9 2001/11/13 13:14:45 lukem Exp $");
__KERNEL_RCSID(0, "$NetBSD: smc93cx6.c,v 1.10 2003/05/02 19:12:19 dyoung Exp $");
#ifndef __NetBSD__
#include "opt_aic7xxx.h"
@ -85,16 +85,20 @@ static struct seeprom_cmd {
unsigned char bits[3];
} seeprom_read = {3, {1, 1, 0}};
/*
* Wait for the SEERDY to go high; about 800 ns.
*/
#define CLOCK_PULSE(sd, rdy) { \
#define CLOCK_PULSE(sd, rdy) do { \
/* \
* Wait for the SEERDY to go high; about 800 ns. \
*/ \
int cpi = 1000; \
if (rdy == 0) { \
DELAY(4); /* more than long enough */ \
break; \
} \
while ((SEEPROM_STATUS_INB(sd) & rdy) == 0 && cpi-- > 0) { \
; /* Do nothing */ \
} \
(void)SEEPROM_INB(sd); /* Clear clock */ \
}
} while (0)
/*
* Read the serial EEPROM and returns 1 if successful and 0 if
@ -110,7 +114,7 @@ read_seeprom(sd, buf, start_addr, count)
int i = 0;
u_int k = 0;
u_int16_t v;
u_int8_t temp;
u_int32_t temp;
/*
* Read the requested registers of the seeprom. The loop

46
sys/dev/ic/smc93cx6var.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: smc93cx6var.h,v 1.5 2000/03/15 02:08:31 fvdl Exp $ */
/* $NetBSD: smc93cx6var.h,v 1.6 2003/05/02 19:12:19 dyoung Exp $ */
/*
* Interface to the 93C46 serial EEPROM that is used to store BIOS
@ -48,16 +48,17 @@ typedef enum {
struct seeprom_descriptor {
bus_space_tag_t sd_tag;
bus_space_handle_t sd_bsh;
bus_size_t sd_regsize;
bus_size_t sd_control_offset;
bus_size_t sd_status_offset;
bus_size_t sd_dataout_offset;
seeprom_chip_t sd_chip;
u_int16_t sd_MS;
u_int16_t sd_RDY;
u_int16_t sd_CS;
u_int16_t sd_CK;
u_int16_t sd_DO;
u_int16_t sd_DI;
u_int32_t sd_MS;
u_int32_t sd_RDY;
u_int32_t sd_CS;
u_int32_t sd_CK;
u_int32_t sd_DO;
u_int32_t sd_DI;
};
/*
@ -77,13 +78,34 @@ struct seeprom_descriptor {
*/
#define SEEPROM_INB(sd) \
bus_space_read_1(sd->sd_tag, sd->sd_bsh, sd->sd_control_offset)
#define SEEPROM_OUTB(sd, value) \
bus_space_write_1(sd->sd_tag, sd->sd_bsh, sd->sd_control_offset, value)
(((sd)->sd_regsize == 4) \
? bus_space_read_4((sd)->sd_tag, (sd)->sd_bsh, \
(sd)->sd_control_offset) \
: bus_space_read_1((sd)->sd_tag, (sd)->sd_bsh, \
(sd)->sd_control_offset))
#define SEEPROM_OUTB(sd, value) do { \
if ((sd)->sd_regsize == 4) \
bus_space_write_4((sd)->sd_tag, (sd)->sd_bsh, \
(sd)->sd_control_offset, (value)); \
else \
bus_space_write_1((sd)->sd_tag, (sd)->sd_bsh, \
(sd)->sd_control_offset, (u_int8_t) (value)); \
} while (0)
#define SEEPROM_STATUS_INB(sd) \
bus_space_read_1(sd->sd_tag, sd->sd_bsh, sd->sd_status_offset)
(((sd)->sd_regsize == 4) \
? bus_space_read_4((sd)->sd_tag, (sd)->sd_bsh, \
(sd)->sd_status_offset) \
: bus_space_read_1((sd)->sd_tag, (sd)->sd_bsh, \
(sd)->sd_status_offset))
#define SEEPROM_DATA_INB(sd) \
bus_space_read_1(sd->sd_tag, sd->sd_bsh, sd->sd_dataout_offset)
(((sd)->sd_regsize == 4) \
? bus_space_read_4((sd)->sd_tag, (sd)->sd_bsh, \
(sd)->sd_dataout_offset) \
: bus_space_read_1((sd)->sd_tag, (sd)->sd_bsh, \
(sd)->sd_dataout_offset))
int read_seeprom(struct seeprom_descriptor *sd, u_int16_t *buf,
bus_size_t start_addr, bus_size_t count);