Add tlb routines for pmap_tlb.c
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matt
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27943e59d2
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sys/arch/arm/arm32/arm32_tlb.c
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sys/arch/arm/arm32/arm32_tlb.c
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/*-
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* Copyright (c) 2013 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(1, "$NetBSD: arm32_tlb.c,v 1.1 2014/03/28 21:51:21 matt Exp $");
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#include <sys/param.h>
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#include <sys/types.h>
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#include <uvm/uvm.h>
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#include <arm/locore.h>
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bool arm_has_tlbiasid_p; // CPU supports TLBIASID system coprocessor op
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tlb_asid_t
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tlb_get_asid(void)
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{
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return armreg_contextidr_read() & 0xff;
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}
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void
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tlb_set_asid(tlb_asid_t asid)
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{
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arm_dsb();
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if (asid == 0) {
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armreg_ttbcr_write(armreg_ttbcr_read() | TTBCR_S_PD0);
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}
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armreg_contextidr_write(asid);
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arm_isb();
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}
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void
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tlb_invalidate_all(void)
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{
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arm_dsb();
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armreg_tlbiall_write(0);
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arm_isb();
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}
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void
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tlb_invalidate_globals(void)
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{
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tlb_invalidate_all();
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}
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void
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tlb_invalidate_asids(tlb_asid_t lo, tlb_asid_t hi)
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{
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arm_dsb();
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if (arm_has_tlbiasid_p) {
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armreg_tlbiall_write(0);
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} else {
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for (; lo <= hi; lo++) {
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armreg_tlbiasid_write(lo);
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}
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}
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arm_isb();
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}
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void
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tlb_invalidate_addr(vaddr_t va, tlb_asid_t asid)
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{
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arm_dsb();
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va = trunc_page(va) | asid;
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for (vaddr_t eva = va + PAGE_SIZE; va < eva; va += L2_S_SIZE) {
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armreg_tlbimva_write(va);
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//armreg_tlbiall_write(asid);
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}
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arm_isb();
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}
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bool
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tlb_update_addr(vaddr_t va, tlb_asid_t asid, pt_entry_t pte, bool insert_p)
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{
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tlb_invalidate_addr(va, asid);
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return true;
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}
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#if !defined(MULTIPROCESSOR) && defined(CPU_CORTEXA5)
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static u_int
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tlb_cortex_a5_record_asids(u_long *mapp)
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{
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u_int nasids = 0;
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for (size_t va_index = 0; va_index < 63; va_index++) {
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for (size_t way = 0; way < 2; way++) {
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armreg_tlbdataop_write(
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__SHIFTIN(way, ARM_TLBDATAOP_WAY)
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| __SHIFTIN(va_index, ARM_A5_TLBDATAOP_INDEX));
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arm_isb();
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const uint64_t d = ((uint64_t) armreg_tlbdata1_read())
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| armreg_tlbdata0_read();
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if (!(d & ARM_TLBDATA_VALID)
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|| !(d & ARM_V5_TLBDATA_nG))
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continue;
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const tlb_asid_t asid = __SHIFTOUT(d,
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ARM_V5_TLBDATA_ASID);
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const u_long mask = 1L << (asid & 31);
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const size_t idx = asid >> 5;
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if (mapp[idx] & mask)
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continue;
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mapp[idx] |= mask;
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nasids++;
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}
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}
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return nasids;
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}
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#endif
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#if !defined(MULTIPROCESSOR) && defined(CPU_CORTEXA7)
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static u_int
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tlb_cortex_a7_record_asids(u_long *mapp)
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{
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u_int nasids = 0;
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for (size_t va_index = 0; va_index < 128; va_index++) {
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for (size_t way = 0; way < 2; way++) {
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armreg_tlbdataop_write(
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__SHIFTIN(way, ARM_TLBDATAOP_WAY)
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| __SHIFTIN(va_index, ARM_A7_TLBDATAOP_INDEX));
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arm_isb();
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const uint32_t d0 = armreg_tlbdata0_read();
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const uint32_t d1 = armreg_tlbdata1_read();
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if (!(d0 & ARM_TLBDATA_VALID)
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|| !(d1 & ARM_A7_TLBDATA1_nG))
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continue;
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const uint64_t d01 = ((uint64_t) d1)|d0;
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const tlb_asid_t asid = __SHIFTOUT(d01,
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ARM_A7_TLBDATA01_ASID);
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const u_long mask = 1L << (asid & 31);
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const size_t idx = asid >> 5;
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if (mapp[idx] & mask)
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continue;
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mapp[idx] |= mask;
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nasids++;
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}
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}
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return nasids;
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}
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#endif
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u_int
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tlb_record_asids(u_long *mapp)
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{
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#ifndef MULTIPROCESSOR
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#ifdef CPU_CORTEXA5
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if (CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid))
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return tlb_cortex_a5_record_asids(mapp);
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#endif
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#ifdef CPU_CORTEXA7
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if (CPU_ID_CORTEX_A7_P(curcpu()->ci_arm_cpuid))
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return tlb_cortex_a7_record_asids(mapp);
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#endif
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#endif /* MULTIPROCESSOR */
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#ifdef DIAGNOSTIC
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mapp[0] = 0xfffffffe;
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mapp[1] = 0xffffffff;
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mapp[2] = 0xffffffff;
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mapp[3] = 0xffffffff;
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mapp[4] = 0xffffffff;
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mapp[5] = 0xffffffff;
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mapp[6] = 0xffffffff;
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mapp[7] = 0xffffffff;
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#endif
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return 255;
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}
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void
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tlb_walk(void *ctx, bool (*func)(void *, vaddr_t, tlb_asid_t, pt_entry_t))
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{
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/* no way to view the TLB */
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}
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