Turn PMAP_NOCACHE into MI flag.
Add MI flags PMAP_WRITE_COMBINE, PMAP_WRITE_BACK, PMAP_NOCACHE_OVR. Update pmap(9) manpage. hppa: Remove MD PMAP_NOCACHE flag as it exists as MI flag mips: Rename MD PMAP_NOCACHE to PGC_NOCACHE. x86: Implement new MI flags using Page-Attribute Tables. x86: Implement BUS_SPACE_MAP_PREFETCHABLE. Patch presented on tech-kern@: http://mail-index.netbsd.org/tech-kern/2010/06/30/msg008458.html No comments on this last version.
This commit is contained in:
cegger
parent
d8a0b8cdce
commit
a63798ea7c
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@ -1,4 +1,4 @@
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.\" $NetBSD: pmap.9,v 1.42 2010/03/22 18:58:33 joerg Exp $
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.\" $NetBSD: pmap.9,v 1.43 2010/07/06 20:50:33 cegger Exp $
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.\"
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.\" Copyright (c) 2000, 2001, 2002 The NetBSD Foundation, Inc.
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.\" All rights reserved.
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@ -486,8 +486,23 @@ resources, the
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.Nm
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module must panic.
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.It PMAP_NOCACHE
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The mapping being created is not cached.
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The mapping being created is
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.Em not
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cached.
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Write accesses have a write-through policy.
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No speculative memory accesses.
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.It PMAP_WRITE_COMBINE
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The mapping being created is
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.Em not
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cached.
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Writes are combined and done in one burst.
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Speculative read accesses may be allowed.
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.It PMAP_WRITE_BACK
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All accesses to the created mapping are cached.
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On reads, cachelines become shared or exclusive if allocated on cache miss.
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On writes, cachelines become modified on a cache miss.
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.It PMAP_NOCACHE_OVR
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Same as PMAP_NOCACHE but mapping is overrideable (e.g. on x86 by MTRRs).
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.El
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.Pp
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The access type provided in the
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@ -633,6 +648,19 @@ The mapping being created is
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.Em not
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cached.
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Write accesses have a write-through policy.
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No speculative memory accesses.
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.It PMAP_WRITE_COMBINE
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The mapping being created is
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.Em not
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cached.
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Writes are combined and done in one burst.
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Speculative read accesses may be allowed.
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.It PMAP_WRITE_BACK
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All accesses to the created mapping are cached.
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On reads, cachelines become shared or exclusive if allocated on cache miss.
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On writes, cachelines become modified on a cache miss.
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.It PMAP_NOCACHE_OVR
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Same as PMAP_NOCACHE but mapping is overrideable (e.g. on x86 by MTRRs).
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.El
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.Pp
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Mappings of this type are always
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@ -1,4 +1,4 @@
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/* $NetBSD: pte.h,v 1.6 2010/02/26 19:25:07 jym Exp $ */
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/* $NetBSD: pte.h,v 1.7 2010/07/06 20:50:34 cegger Exp $ */
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/*
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* Copyright (c) 2001 Wasabi Systems, Inc.
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@ -105,18 +105,23 @@ typedef uint64_t pt_entry_t; /* PTE */
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#define PG_RW 0x0000000000000002 /* read-write */
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#define PG_u 0x0000000000000004 /* user accessible */
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#define PG_PROT 0x0000000000000006
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#define PG_N 0x0000000000000018 /* non-cacheable */
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#define PG_WT 0x0000000000000008 /* write-through */
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#define PG_N 0x0000000000000010 /* non-cacheable */
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#define PG_U 0x0000000000000020 /* used */
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#define PG_M 0x0000000000000040 /* modified */
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#define PG_PS 0x0000000000000080 /* 2MB page size */
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#define PG_PAT 0x0000000000000080 /* PAT (on pte) */
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#define PG_PS 0x0000000000000080 /* 2MB page size (on pde) */
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#define PG_G 0x0000000000000100 /* not flushed */
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#define PG_AVAIL1 0x0000000000000200
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#define PG_AVAIL2 0x0000000000000400
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#define PG_AVAIL3 0x0000000000000800
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#define PG_LGPAT 0x0000000000001000 /* PAT on large pages */
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#define PG_FRAME 0x000ffffffffff000
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#define PG_NX 0x8000000000000000
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#define PG_LGFRAME 0x000fffffffe00000 /* large (2M) page frame mask */
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#define PG_2MFRAME 0x000fffffffe00000 /* large (2M) page frame mask */
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#define PG_1GFRAME 0x000fffffc0000000 /* large (1G) page frame mask */
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#define PG_LGFRAME PG_2MFRAME
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/*
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* short forms of protection codes
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@ -125,13 +130,6 @@ typedef uint64_t pt_entry_t; /* PTE */
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#define PG_KR 0x0000000000000000 /* kernel read-only */
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#define PG_KW 0x0000000000000002 /* kernel read-write */
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/*
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* page protection exception bits
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*/
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#define PGEX_P 0x01 /* protection violation (vs. no mapping) */
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#define PGEX_W 0x02 /* exception during a write cycle */
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#define PGEX_U 0x04 /* exception while in user mode (upl) */
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#define PGEX_X 0x10 /* exception during instruction fetch */
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#include <x86/pte.h>
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#endif /* _AMD64_PTE_H_ */
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.h,v 1.27 2010/06/21 14:43:34 skrll Exp $ */
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/* $NetBSD: pmap.h,v 1.28 2010/07/06 20:50:34 cegger Exp $ */
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/* $OpenBSD: pmap.h,v 1.35 2007/12/14 18:32:23 deraadt Exp $ */
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@ -192,11 +192,6 @@ pmap_protect(struct pmap *pmap, vaddr_t sva, vaddr_t eva, vm_prot_t prot)
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((((va) & 0xc0000000) != 0xc0000000) ? \
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(pmap)->pm_space : HPPA_SID_KERNEL)
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/*
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* MD flags that we use for pmap_kenter_pa:
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*/
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#define PMAP_NOCACHE 0x01000000 /* set the non-cacheable bit */
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#endif /* _KERNEL */
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#endif /* _HPPA_PMAP_H_ */
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@ -1,4 +1,4 @@
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/* $NetBSD: pte.h,v 1.23 2010/05/04 23:27:14 jym Exp $ */
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/* $NetBSD: pte.h,v 1.24 2010/07/06 20:50:34 cegger Exp $ */
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/*
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* Copyright (c) 2001 Wasabi Systems, Inc.
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@ -218,7 +218,9 @@ typedef uint32_t pt_entry_t; /* PTE */
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/* macros to get real L2 and L3 index, from our "extended" L2 index */
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#define l2tol3(idx) ((idx) >> (L3_SHIFT - L2_SHIFT))
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#define l2tol2(idx) ((idx) & (L2_REALMASK >> L2_SHIFT))
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#else /* PAE */
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#define L1_SHIFT 12
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#define L2_SHIFT 22
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#define NBPD_L1 (1UL << L1_SHIFT) /* # bytes mapped by L1 ent (4K) */
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@ -245,14 +247,17 @@ typedef uint32_t pt_entry_t; /* PTE */
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#define PG_RW 0x00000002 /* read-write page */
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#define PG_u 0x00000004 /* user accessible page */
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#define PG_PROT 0x00000806 /* all protection bits */
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#define PG_N 0x00000018 /* non-cacheable */
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#define PG_WT 0x00000008 /* write through */
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#define PG_N 0x00000010 /* non-cacheable */
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#define PG_U 0x00000020 /* has been used */
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#define PG_M 0x00000040 /* has been modified */
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#define PG_PAT 0x00000080 /* PAT (on pte) */
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#define PG_PS 0x00000080 /* 4MB page size */
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#define PG_G 0x00000100 /* global, don't TLB flush */
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#define PG_AVAIL1 0x00000200 /* ignored by hardware */
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#define PG_AVAIL2 0x00000400 /* ignored by hardware */
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#define PG_AVAIL3 0x00000800 /* ignored by hardware */
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#define PG_LGPAT 0x00001000 /* PAT on large pages */
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/*
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* various short-hand protection codes
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@ -267,13 +272,6 @@ typedef uint32_t pt_entry_t; /* PTE */
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#define PG_NX 0 /* dummy */
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#endif
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/*
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* page protection exception bits
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*/
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#define PGEX_P 0x01 /* protection violation (vs. no mapping) */
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#define PGEX_W 0x02 /* exception during a write cycle */
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#define PGEX_U 0x04 /* exception while in user mode (upl) */
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#define PGEX_X 0x10 /* exception during instruction fetch */
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#include <x86/pte.h>
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#endif /* _I386_PTE_H_ */
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.h,v 1.57 2009/12/14 00:46:05 matt Exp $ */
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/* $NetBSD: pmap.h,v 1.58 2010/07/06 20:50:34 cegger Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -202,7 +202,7 @@ paddr_t mips_pmap_unmap_poolpage(vaddr_t);
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#define PMAP_CCA_FOR_PA(pa) CCA_UNCACHED /* uncached */
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#if defined(_MIPS_PADDR_T_64BIT) || defined(_LP64)
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#define PMAP_NOCACHE 0x4000000000000000ULL
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#define PGC_NOCACHE 0x4000000000000000ULL
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#endif
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#endif /* _KERNEL */
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.188 2009/12/14 00:46:07 matt Exp $ */
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/* $NetBSD: pmap.c,v 1.189 2010/07/06 20:50:34 cegger Exp $ */
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/*-
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* Copyright (c) 1998, 2001 The NetBSD Foundation, Inc.
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@ -67,7 +67,7 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.188 2009/12/14 00:46:07 matt Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.189 2010/07/06 20:50:34 cegger Exp $");
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/*
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* Manages physical address maps.
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@ -1177,9 +1177,12 @@ pmap_enter(pmap_t pmap, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags)
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#endif
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#if defined(_MIPS_PADDR_T_64BIT) || defined(_LP64)
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if (pa & PMAP_NOCACHE) {
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if (flags & PMAP_NOCACHE) {
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cached = 0;
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pa &= ~PMAP_NOCACHE;
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pa &= ~PGC_NOCACHE;
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} else {
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cached = 1;
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pa |= PGC_NOCACHE;
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}
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#endif
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@ -1,4 +1,4 @@
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/* $NetBSD: bus.c,v 1.59 2009/12/17 03:59:31 macallan Exp $ */
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/* $NetBSD: bus.c,v 1.60 2010/07/06 20:50:35 cegger Exp $ */
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/*
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: bus.c,v 1.59 2009/12/17 03:59:31 macallan Exp $");
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__KERNEL_RCSID(0, "$NetBSD: bus.c,v 1.60 2010/07/06 20:50:35 cegger Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -1116,6 +1116,7 @@ _bus_dmamem_map(bus_dma_tag_t t, bus_dma_segment_t *segs, int nsegs,
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int curseg;
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const uvm_flag_t kmflags =
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(flags & BUS_DMA_NOWAIT) != 0 ? UVM_KMF_NOWAIT : 0;
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u_int pmapflags;
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/*
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* If we're only mapping 1 segment, use KSEG0 or KSEG1, to avoid
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@ -1139,21 +1140,19 @@ _bus_dmamem_map(bus_dma_tag_t t, bus_dma_segment_t *segs, int nsegs,
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*kvap = (void *)va;
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pmapflags = VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED;
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if (flags & BUS_DMA_COHERENT)
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pmapflags |= PMAP_NOCACHE;
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for (curseg = 0; curseg < nsegs; curseg++) {
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for (addr = segs[curseg].ds_addr;
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addr < (segs[curseg].ds_addr + segs[curseg].ds_len);
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addr += PAGE_SIZE, va += PAGE_SIZE, size -= PAGE_SIZE) {
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if (size == 0)
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panic("_bus_dmamem_map: size botch");
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pmap_enter(pmap_kernel(), va,
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#if defined(_MIPS_PADDR_T_64BIT) || defined(_LP64)
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(flags & BUS_DMA_COHERENT) ?
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addr | PMAP_NOCACHE : addr,
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#else
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addr,
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#endif
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pmap_enter(pmap_kernel(), va, addr,
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VM_PROT_READ | VM_PROT_WRITE,
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VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED);
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pmapflags);
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}
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}
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pmap_update(pmap_kernel());
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@ -1,4 +1,4 @@
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/* $NetBSD: cpuvar.h,v 1.32 2010/04/18 23:47:51 jym Exp $ */
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/* $NetBSD: cpuvar.h,v 1.33 2010/07/06 20:50:35 cegger Exp $ */
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/*-
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* Copyright (c) 2000, 2007 The NetBSD Foundation, Inc.
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@ -140,12 +140,13 @@ int p4_get_bus_clock(struct cpu_info *);
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#endif
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void cpu_get_tsc_freq(struct cpu_info *);
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void pat_init(struct cpu_info *);
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extern int cpu_vendor;
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extern bool x86_mp_online;
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extern uint32_t cpu_feature[5];
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#endif
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#endif /* _KERNEL */
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#endif /* !_X86_CPUVAR_H_ */
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.h,v 1.30 2010/05/10 18:46:58 dyoung Exp $ */
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/* $NetBSD: pmap.h,v 1.31 2010/07/06 20:50:35 cegger Exp $ */
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/*
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*
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@ -178,7 +178,6 @@ struct pmap {
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/*
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* MD flags that we use for pmap_enter and pmap_kenter_pa:
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*/
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#define PMAP_NOCACHE 0x01000000 /* set the non-cacheable bit */
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/*
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* global kernel variables
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@ -0,0 +1,50 @@
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/* $NetBSD: pte.h,v 1.1 2010/07/06 20:50:35 cegger Exp $ */
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/*
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* Copyright (c) 2010 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Christoph Egger.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
|
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* notice, this list of conditions and the following disclaimer.
|
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* 2. Redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _X86_PTE_H
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#define _X86_PTE_H
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/* Cacheability bits when we are using PAT */
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#define PGC_WB 0 /* The default */
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#define PGC_WC PG_WT /* WT and CD is WC */
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#define PGC_UCMINUS PG_N /* UC but mtrr can override */
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#define PGC_UC (PG_WT | PG_N) /* hard UC */
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/*
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* page protection exception bits
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*/
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#define PGEX_P 0x01 /* protection violation (vs. no mapping) */
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#define PGEX_W 0x02 /* exception during a write cycle */
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#define PGEX_U 0x04 /* exception while in user mode (upl) */
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#define PGEX_X 0x10 /* exception during instruction fetch */
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#endif /* _X86_PTE_H */
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@ -1,4 +1,4 @@
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/* $NetBSD: specialreg.h,v 1.41 2010/05/04 23:27:14 jym Exp $ */
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/* $NetBSD: specialreg.h,v 1.42 2010/07/06 20:50:35 cegger Exp $ */
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/*-
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* Copyright (c) 1991 The Regents of the University of California.
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@ -343,6 +343,7 @@
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#define MSR_MTRRfix4K_E8000 0x26d
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#define MSR_MTRRfix4K_F0000 0x26e
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#define MSR_MTRRfix4K_F8000 0x26f
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#define MSR_CR_PAT 0x277
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#define MSR_MTRRdefType 0x2ff
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#define MSR_MC0_CTL 0x400
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#define MSR_MC0_STATUS 0x401
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@ -1,4 +1,4 @@
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/* $NetBSD: bus_space.c,v 1.29 2010/05/10 18:46:58 dyoung Exp $ */
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/* $NetBSD: bus_space.c,v 1.30 2010/07/06 20:50:35 cegger Exp $ */
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/*-
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* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
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@ -31,7 +31,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: bus_space.c,v 1.29 2010/05/10 18:46:58 dyoung Exp $");
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__KERNEL_RCSID(0, "$NetBSD: bus_space.c,v 1.30 2010/07/06 20:50:35 cegger Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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|
|
@ -199,8 +199,7 @@ bus_space_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size,
|
|||
* For memory space, map the bus physical address to
|
||||
* a kernel virtual address.
|
||||
*/
|
||||
error = x86_mem_add_mapping(bpa, size,
|
||||
(flags & BUS_SPACE_MAP_CACHEABLE) != 0, bshp);
|
||||
error = x86_mem_add_mapping(bpa, size, flags, bshp);
|
||||
if (error) {
|
||||
if (extent_free(ex, bpa, size, EX_NOWAIT |
|
||||
(ioport_malloc_safe ? EX_MALLOCOK : 0))) {
|
||||
|
|
@ -232,8 +231,7 @@ _x86_memio_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size,
|
|||
* For memory space, map the bus physical address to
|
||||
* a kernel virtual address.
|
||||
*/
|
||||
return (x86_mem_add_mapping(bpa, size,
|
||||
(flags & BUS_SPACE_MAP_CACHEABLE) != 0, bshp));
|
||||
return x86_mem_add_mapping(bpa, size, flags, bshp);
|
||||
}
|
||||
|
||||
int
|
||||
|
|
@ -286,8 +284,7 @@ bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart, bus_addr_t rend,
|
|||
* For memory space, map the bus physical address to
|
||||
* a kernel virtual address.
|
||||
*/
|
||||
error = x86_mem_add_mapping(bpa, size,
|
||||
(flags & BUS_SPACE_MAP_CACHEABLE) != 0, bshp);
|
||||
error = x86_mem_add_mapping(bpa, size, flags, bshp);
|
||||
if (error) {
|
||||
if (extent_free(iomem_ex, bpa, size, EX_NOWAIT |
|
||||
(ioport_malloc_safe ? EX_MALLOCOK : 0))) {
|
||||
|
|
@ -304,17 +301,20 @@ bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart, bus_addr_t rend,
|
|||
|
||||
int
|
||||
x86_mem_add_mapping(bus_addr_t bpa, bus_size_t size,
|
||||
int cacheable, bus_space_handle_t *bshp)
|
||||
int flags, bus_space_handle_t *bshp)
|
||||
{
|
||||
paddr_t pa, endpa;
|
||||
vaddr_t va, sva;
|
||||
u_int pmapflags = 0;
|
||||
u_int pmapflags;
|
||||
|
||||
pa = x86_trunc_page(bpa);
|
||||
endpa = x86_round_page(bpa + size);
|
||||
|
||||
if (!cacheable)
|
||||
pmapflags |= PMAP_NOCACHE;
|
||||
pmapflags = PMAP_NOCACHE;
|
||||
if ((flags & BUS_SPACE_MAP_CACHEABLE) != 0)
|
||||
pmapflags = 0;
|
||||
else if (flags & BUS_SPACE_MAP_PREFETCHABLE)
|
||||
pmapflags = PMAP_WRITE_COMBINE;
|
||||
|
||||
#ifdef DIAGNOSTIC
|
||||
if (endpa != 0 && endpa <= pa)
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: cpu.c,v 1.70 2010/04/18 23:47:51 jym Exp $ */
|
||||
/* $NetBSD: cpu.c,v 1.71 2010/07/06 20:50:35 cegger Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2000, 2006, 2007, 2008 The NetBSD Foundation, Inc.
|
||||
|
|
@ -62,7 +62,7 @@
|
|||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.70 2010/04/18 23:47:51 jym Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.71 2010/07/06 20:50:35 cegger Exp $");
|
||||
|
||||
#include "opt_ddb.h"
|
||||
#include "opt_mpbios.h" /* for MPDEBUG */
|
||||
|
|
@ -424,6 +424,7 @@ cpu_attach(device_t parent, device_t self, void *aux)
|
|||
panic("unknown processor type??\n");
|
||||
}
|
||||
|
||||
pat_init(ci);
|
||||
atomic_or_32(&cpus_attached, ci->ci_cpumask);
|
||||
|
||||
if (!pmf_device_register(self, cpu_suspend, cpu_resume))
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: pmap.c,v 1.109 2010/05/10 18:46:58 dyoung Exp $ */
|
||||
/* $NetBSD: pmap.c,v 1.110 2010/07/06 20:50:35 cegger Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2007 Manuel Bouyer.
|
||||
|
|
@ -149,7 +149,7 @@
|
|||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.109 2010/05/10 18:46:58 dyoung Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.110 2010/07/06 20:50:35 cegger Exp $");
|
||||
|
||||
#include "opt_user_ldt.h"
|
||||
#include "opt_lockdebug.h"
|
||||
|
|
@ -360,6 +360,20 @@ struct evcnt pmap_ldt_evcnt;
|
|||
struct evcnt pmap_tlb_evcnt __aligned(64);
|
||||
struct pmap_mbox pmap_mbox __aligned(64);
|
||||
|
||||
/*
|
||||
* PAT
|
||||
*/
|
||||
#define PATENTRY(n, type) (type << ((n) * 8))
|
||||
#define PAT_UC 0x0ULL
|
||||
#define PAT_WC 0x1ULL
|
||||
#define PAT_WT 0x4ULL
|
||||
#define PAT_WP 0x5ULL
|
||||
#define PAT_WB 0x6ULL
|
||||
#define PAT_UCMINUS 0x7ULL
|
||||
|
||||
static bool cpu_pat_enabled = false;
|
||||
|
||||
|
||||
/*
|
||||
* Per-CPU data. The pmap mailbox is cache intensive so gets its
|
||||
* own line. Note that the mailbox must be the first item.
|
||||
|
|
@ -1004,6 +1018,57 @@ pmap_exec_fixup(struct vm_map *map, struct trapframe *tf, struct pcb *pcb)
|
|||
}
|
||||
#endif /* !defined(__x86_64__) */
|
||||
|
||||
void
|
||||
pat_init(struct cpu_info *ci)
|
||||
{
|
||||
uint64_t pat;
|
||||
|
||||
if (!(ci->ci_feat_val[0] & CPUID_PAT))
|
||||
return;
|
||||
|
||||
/* We change WT to WC. Leave all other entries the default values. */
|
||||
pat = PATENTRY(0, PAT_WB) | PATENTRY(1, PAT_WC) |
|
||||
PATENTRY(2, PAT_UCMINUS) | PATENTRY(3, PAT_UC) |
|
||||
PATENTRY(4, PAT_WB) | PATENTRY(5, PAT_WC) |
|
||||
PATENTRY(6, PAT_UCMINUS) | PATENTRY(7, PAT_UC);
|
||||
|
||||
wrmsr(MSR_CR_PAT, pat);
|
||||
cpu_pat_enabled = true;
|
||||
aprint_debug_dev(ci->ci_dev, "PAT enabled\n");
|
||||
}
|
||||
|
||||
static pt_entry_t
|
||||
pmap_pat_flags(u_int flags)
|
||||
{
|
||||
u_int cacheflags = (flags & PMAP_CACHE_MASK);
|
||||
|
||||
if (!cpu_pat_enabled) {
|
||||
switch (cacheflags) {
|
||||
case PMAP_NOCACHE:
|
||||
case PMAP_NOCACHE_OVR:
|
||||
/* results in PGC_UCMINUS on cpus which have
|
||||
* the cpuid PAT but PAT "disabled"
|
||||
*/
|
||||
return PG_N;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
switch (cacheflags) {
|
||||
case PMAP_NOCACHE:
|
||||
return PGC_UC;
|
||||
case PMAP_WRITE_COMBINE:
|
||||
return PGC_WC;
|
||||
case PMAP_WRITE_BACK:
|
||||
return PGC_WB;
|
||||
case PMAP_NOCACHE_OVR:
|
||||
return PGC_UCMINUS;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* p m a p k e n t e r f u n c t i o n s
|
||||
*
|
||||
|
|
@ -1041,8 +1106,7 @@ pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags)
|
|||
#endif /* DOM0OPS */
|
||||
npte = pmap_pa2pte(pa);
|
||||
npte |= protection_codes[prot] | PG_k | PG_V | pmap_pg_g;
|
||||
if (flags & PMAP_NOCACHE)
|
||||
npte |= PG_N;
|
||||
npte |= pmap_pat_flags(flags);
|
||||
opte = pmap_pte_testset(pte, npte); /* zap! */
|
||||
#if defined(DIAGNOSTIC)
|
||||
/* XXX For now... */
|
||||
|
|
@ -3961,10 +4025,9 @@ pmap_enter_ma(struct pmap *pmap, vaddr_t va, paddr_t ma, paddr_t pa,
|
|||
#endif /* XEN */
|
||||
|
||||
npte = ma | protection_codes[prot] | PG_V;
|
||||
npte |= pmap_pat_flags(flags);
|
||||
if (wired)
|
||||
npte |= PG_W;
|
||||
if (flags & PMAP_NOCACHE)
|
||||
npte |= PG_N;
|
||||
if (va < VM_MAXUSER_ADDRESS)
|
||||
npte |= PG_u;
|
||||
else if (va < VM_MAX_ADDRESS)
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: cpu.c,v 1.45 2010/06/28 00:47:53 rmind Exp $ */
|
||||
/* $NetBSD: cpu.c,v 1.46 2010/07/06 20:50:35 cegger Exp $ */
|
||||
/* NetBSD: cpu.c,v 1.18 2004/02/20 17:35:01 yamt Exp */
|
||||
|
||||
/*-
|
||||
|
|
@ -66,7 +66,7 @@
|
|||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.45 2010/06/28 00:47:53 rmind Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.46 2010/07/06 20:50:35 cegger Exp $");
|
||||
|
||||
#include "opt_ddb.h"
|
||||
#include "opt_multiprocessor.h"
|
||||
|
|
@ -517,6 +517,7 @@ cpu_attach_common(device_t parent, device_t self, void *aux)
|
|||
panic("unknown processor type??\n");
|
||||
}
|
||||
|
||||
pat_init(ci);
|
||||
atomic_or_32(&cpus_attached, ci->ci_cpumask);
|
||||
|
||||
#if 0
|
||||
|
|
|
|||
Loading…
Reference in New Issue