Import i386/gcscide(4). A driver for the IDE Controller of the
AMD CS5535 Companion device found in the decTOP. gcscide0 at pci0 dev 15 function 2 gcscide0: National Semiconductor/AMD CS5535 IDE Controller (rev. 0x00) Supports Ultra DMA mode 4, Pio Mode 4 and MDMA mode 2. "Go for it" jmcneill@.
This commit is contained in:
xtraeme
parent
dbbafa7889
commit
a5ac7ff5aa
@ -1,4 +1,4 @@
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LIST OF CHANGES FROM LAST RELEASE: <$Revision: 1.881 $>
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LIST OF CHANGES FROM LAST RELEASE: <$Revision: 1.882 $>
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[Note: This file does not mention every change made to the NetBSD source tree.
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@ -144,3 +144,6 @@ Changes from NetBSD 4.0 to NetBSD 5.0:
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tcpdrop(8): Ported by anon ymous (from FreeBSD/OpenBSD)
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[christos 20070625]
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fast_ipsec(4): Add support for IPsec NAT-T [degroote 20070627]
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i386: Imported gcscide(4), a driver for the AMD CS5535 Companion
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IDE Controller for systems with an AMD Geode GX2 CPU
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(for example the decTOP). [xtraeme 20070627]
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@ -1,10 +1,10 @@
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# $NetBSD: Makefile,v 1.66 2007/06/15 23:04:21 jmcneill Exp $
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# $NetBSD: Makefile,v 1.67 2007/06/27 23:02:53 xtraeme Exp $
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# from: @(#)Makefile 8.1 (Berkeley) 6/5/93
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MAN= apm.4 autoconf.4 \
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cmos.4 console.4 \
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elansc.4 fdc.4 \
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geodewdog.4 geodecntr.4 glxsb.4 gscpcib.4 \
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gcscide.4 geodewdog.4 geodecntr.4 glxsb.4 gscpcib.4 \
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intro.4 io.4 lms.4 lpt.4 mem.4 mms.4 npx.4 ndis.4 \
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pcibios.4 pnpbios.4 sony.4 spic.4 vald.4 \
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vesafb.4
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59
share/man/man4/man4.i386/gcscide.4
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59
share/man/man4/man4.i386/gcscide.4
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.\" $NetBSD: gcscide.4,v 1.1 2007/06/27 23:02:53 xtraeme Exp $
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.\"
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.\" Copyright (c) 2003 Manuel Bouyer.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\" 3. All advertising materials mentioning features or use of this software
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.\" must display the following acknowledgement:
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.\" This product includes software developed by Manuel Bouyer.
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.\" 4. The name of the author may not be used to endorse or promote products
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.\" derived from this software without specific prior written permission.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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.\" INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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.\"
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.Dd June 28, 2007
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.Dt GCSCIDE 4
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.Os
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.Sh NAME
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.Nm gcscide
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.Nd AMD CS5535 Companion IDE controller driver
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.Sh SYNOPSIS
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.Cd "gcscide* at pci? dev ? function ? flags 0x0000"
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.Sh DESCRIPTION
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The
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.Nm
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driver supports the AMD CS5535 Companion IDE controller, and provides the
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interface with the hardware for the
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.Xr ata 4
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driver.
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.Pp
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The 0x0002 flag forces the
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.Nm
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driver to disable DMA on chipsets for which DMA would normally be
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enabled.
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This can be used as a debugging aid, or to work around
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problems where the IDE controller is wired up to the system incorrectly.
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.Sh SEE ALSO
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.Xr ata 4 ,
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.Xr atapi 4 ,
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.Xr intro 4 ,
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.Xr pci 4 ,
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.Xr pciide 4 ,
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.Xr wd 4 ,
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.Xr wdc 4
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@ -1,4 +1,4 @@
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# $NetBSD: files.i386,v 1.309 2007/06/15 23:02:20 jmcneill Exp $
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# $NetBSD: files.i386,v 1.310 2007/06/27 23:02:52 xtraeme Exp $
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#
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# new style config file for i386 architecture
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#
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@ -189,6 +189,11 @@ device elansc: sysmon_wdog, gpiobus
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attach elansc at pci
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file arch/i386/pci/elan520.c elansc
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# AMD Geode CS5535 Companion IDE controller
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device gcscide: ata, ata_dma, ata_udma, pciide_common, wdc_common
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attach gcscide at pci
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file arch/i386/pci/gcscide.c gcscide
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# AMD Geode SC1100 GCB area
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device geodegcb {}
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attach geodegcb at pci
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244
sys/arch/i386/pci/gcscide.c
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244
sys/arch/i386/pci/gcscide.c
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/* $NetBSD: gcscide.c,v 1.1 2007/06/27 23:02:53 xtraeme Exp $ */
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/*
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* Copyright (c) 2007 The NetBSD Foundation.
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* All rights reserved.
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*
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* This code is derived from software contributed to the NetBSD Foundation
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* by Juan Romero Pardines.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Juan Romero Pardines
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* for the NetBSD Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Driver for the National Semiconductor/AMD CS5535 Companion Controller.
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* Usually this comes with an AMD Geode GX CPU.
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*
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* Datasheet at:
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*
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* http://www.amd.com/files/connectivitysolutions/geode/geode_gx/31506_cs5535_databook.pdf
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: gcscide.c,v 1.1 2007/06/27 23:02:53 xtraeme Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciidereg.h>
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#include <dev/pci/pciidevar.h>
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#include <machine/cpufunc.h>
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#define GCSCIDE_MSR_ATAC_BASE 0x51300000
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#define GCSCIDE_ATAC_GLD_MSR_CAP (GCSCIDE_MSR_ATAC_BASE + 0)
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#define GCSCIDE_ATAC_GLD_MSR_CONFIG (GCSCIDE_MSR_ATAC_BASE + 0x01)
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#define GCSCIDE_ATAC_GLD_MSR_SMI (GCSCIDE_MSR_ATAC_BASE + 0x02)
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#define GCSCIDE_ATAC_GLD_MSR_ERROR (GCSCIDE_MSR_ATAC_BASE + 0x03)
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#define GCSCIDE_ATAC_GLD_MSR_PM (GCSCIDE_MSR_ATAC_BASE + 0x04)
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#define GCSCIDE_ATAC_GLD_MSR_DIAG (GCSCIDE_MSR_ATAC_BASE + 0x05)
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#define GCSCIDE_ATAC_IO_BAR (GCSCIDE_MSR_ATAC_BASE + 0x08)
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#define GCSCIDE_ATAC_RESET (GCSCIDE_MSR_ATAC_BASE + 0x10)
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#define GCSCIDE_ATAC_CH0D0_PIO (GCSCIDE_MSR_ATAC_BASE + 0x20)
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#define GCSCIDE_ATAC_CH0D0_DMA (GCSCIDE_MSR_ATAC_BASE + 0x21)
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#define GCSCIDE_ATAC_CH0D1_PIO (GCSCIDE_MSR_ATAC_BASE + 0x22)
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#define GCSCIDE_ATAC_CH0D1_DMA (GCSCIDE_MSR_ATAC_BASE + 0x23)
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#define GCSCIDE_ATAC_PCI_ABRTERR (GCSCIDE_MSR_ATAC_BASE + 0x24)
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#define GCSCIDE_ATAC_BM0_CMD_PRIM 0x00
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#define GCSCIDE_ATAC_BM0_STS_PRIM 0x02
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#define GCSCIDE_ATAC_BM0_PRD 0x04
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#define GCSCIDE_PIO_FORMAT 0x80000000UL
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static int gcscide_match(struct device *, struct cfdata *, void *);
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static void gcscide_attach(struct device *, struct device *, void *);
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static void gcscide_chip_map(struct pciide_softc *, struct pci_attach_args *);
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static void gcscide_setup_channel(struct ata_channel *);
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/* PIO Format 1 timings */
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static const uint32_t gcscide_pio_timings[] = {
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0xf7f4f7f4, /* PIO Mode 0 */
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0x53f3f173, /* PIO Mode 1 */
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0x13f18141, /* PIO Mode 2 */
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0x51315131, /* PIO Mode 3 */
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0x11311131 /* PIO Mode 4 */
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};
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static const uint32_t gcscide_mdma_timings[] = {
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0x7f0ffff3, /* MDMA Mode 0 */
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0x7f035352, /* MDMA Mode 1 */
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0x7f024241 /* MDMA Mode 2 */
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};
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static const uint32_t gcscide_udma_timings[] = {
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0x7f7436a1, /* Ultra DMA Mode 0 */
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0x7f733481, /* Ultra DMA Mode 1 */
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0x7f723261, /* Ultra DMA Mode 2 */
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0x7f713161, /* Ultra DMA Mode 3 */
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0x7f703061 /* Ultra DMA Mode 4 */
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};
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CFATTACH_DECL(gcscide, sizeof(struct pciide_softc),
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gcscide_match, gcscide_attach, NULL, NULL);
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static const struct pciide_product_desc pciide_gcscide_products[] = {
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{
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PCI_PRODUCT_NS_CS5535_IDE,
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0,
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"National Semiconductor/AMD CS5535 IDE Controller",
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gcscide_chip_map
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},
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{ 0, 0, NULL, NULL }
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};
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static int
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gcscide_match(struct device *parent, struct cfdata *cfdata, void *aux)
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{
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struct pci_attach_args *pa = (struct pci_attach_args *)aux;
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS &&
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PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
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PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE &&
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pciide_lookup_product(pa->pa_id, pciide_gcscide_products))
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return 2;
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return 0;
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}
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static void
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gcscide_attach(struct device *parent, struct device *self, void *aux)
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{
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struct pci_attach_args *pa = aux;
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struct pciide_softc *sc = (struct pciide_softc *)self;
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pciide_common_attach(sc, pa,
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pciide_lookup_product(pa->pa_id, pciide_gcscide_products));
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}
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static void
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gcscide_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
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{
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pcireg_t interface;
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bus_size_t cmdsize, ctlsize;
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if (pciide_chipen(sc, pa) == 0)
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return;
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aprint_verbose("%s: bus-master DMA support present",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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pciide_mapreg_dma(sc, pa);
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aprint_verbose("\n");
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sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
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if (sc->sc_dma_ok) {
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
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sc->sc_wdcdev.irqack = pciide_irqack;
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}
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sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
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sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
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sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
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sc->sc_wdcdev.sc_atac.atac_set_modes = gcscide_setup_channel;
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sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
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sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
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interface = PCI_INTERFACE(pa->pa_class);
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wdc_allocate_regs(&sc->sc_wdcdev);
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if (pciide_chansetup(sc, 0, interface) == 0)
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return;
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pciide_mapchan(pa, &sc->pciide_channels[0], interface,
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&cmdsize, &ctlsize, pciide_pci_intr);
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}
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static void
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gcscide_setup_channel(struct ata_channel *chp)
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{
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struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
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struct ata_drive_datas *drvp;
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uint64_t reg = 0;
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int drive, s;
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pciide_channel_dma_setup(cp);
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for (drive = 0; drive < 2; drive++) {
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drvp = &chp->ch_drive[drive];
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if ((drvp->drive_flags & DRIVE) == 0)
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continue;
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if ((drvp->drive_flags & DRIVE_UDMA) ||
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(drvp->drive_flags & DRIVE_DMA)) {
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reg = rdmsr(drive ? GCSCIDE_ATAC_CH0D1_DMA :
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GCSCIDE_ATAC_CH0D0_DMA);
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/* high 32 bits */
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reg = (reg << 32);
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/* Preserve PIO Format bit */
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reg &= GCSCIDE_PIO_FORMAT;
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}
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if (drvp->drive_flags & DRIVE_UDMA) {
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s = splbio();
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drvp->drive_flags &= ~DRIVE_DMA;
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splx(s);
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/* Set UDMA and MDMA timings */
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reg |= gcscide_udma_timings[drvp->UDMA_mode];
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reg |= gcscide_mdma_timings[drvp->DMA_mode];
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wrmsr(drive ? GCSCIDE_ATAC_CH0D1_DMA :
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GCSCIDE_ATAC_CH0D0_DMA, reg);
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} else if (drvp->drive_flags & DRIVE_DMA) {
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/*
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* Disable Ultra DMA and set a MDMA mode.
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*/
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if (reg & gcscide_udma_timings[drvp->UDMA_mode])
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reg &= ~gcscide_udma_timings[drvp->UDMA_mode];
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reg |= gcscide_mdma_timings[drvp->DMA_mode];
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wrmsr(drive ? GCSCIDE_ATAC_CH0D1_DMA :
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GCSCIDE_ATAC_CH0D0_DMA, reg);
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} else {
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/*
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* Set PIO Format 1 timings.
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*/
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reg = rdmsr(drive ? GCSCIDE_ATAC_CH0D1_DMA :
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GCSCIDE_ATAC_CH0D0_DMA);
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reg = (reg << 32);
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wrmsr(drive ? GCSCIDE_ATAC_CH0D1_DMA :
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GCSCIDE_ATAC_CH0D0_DMA, reg | GCSCIDE_PIO_FORMAT);
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}
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/* Set PIO mode and timing */
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wrmsr(drive ? GCSCIDE_ATAC_CH0D1_PIO : GCSCIDE_ATAC_CH0D1_PIO,
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gcscide_pio_timings[drvp->PIO_mode]);
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}
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}
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