u_intNN_t -> uintNN_t
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cae22e3811
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a5abba7c76
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@ -1,4 +1,4 @@
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/* $NetBSD: smc83c170.c,v 1.62 2006/04/16 00:35:10 tsutsui Exp $ */
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/* $NetBSD: smc83c170.c,v 1.63 2006/04/16 00:38:59 tsutsui Exp $ */
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/*-
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/*-
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* Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
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* Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
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@ -43,7 +43,7 @@
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*/
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*/
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#include <sys/cdefs.h>
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: smc83c170.c,v 1.62 2006/04/16 00:35:10 tsutsui Exp $");
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__KERNEL_RCSID(0, "$NetBSD: smc83c170.c,v 1.63 2006/04/16 00:38:59 tsutsui Exp $");
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#include "bpfilter.h"
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#include "bpfilter.h"
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@ -89,12 +89,12 @@ void epic_shutdown(void *);
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void epic_reset(struct epic_softc *);
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void epic_reset(struct epic_softc *);
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void epic_rxdrain(struct epic_softc *);
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void epic_rxdrain(struct epic_softc *);
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int epic_add_rxbuf(struct epic_softc *, int);
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int epic_add_rxbuf(struct epic_softc *, int);
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void epic_read_eeprom(struct epic_softc *, int, int, u_int16_t *);
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void epic_read_eeprom(struct epic_softc *, int, int, uint16_t *);
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void epic_set_mchash(struct epic_softc *);
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void epic_set_mchash(struct epic_softc *);
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void epic_fixup_clock_source(struct epic_softc *);
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void epic_fixup_clock_source(struct epic_softc *);
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int epic_mii_read(struct device *, int, int);
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int epic_mii_read(struct device *, int, int);
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void epic_mii_write(struct device *, int, int, int);
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void epic_mii_write(struct device *, int, int, int);
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int epic_mii_wait(struct epic_softc *, u_int32_t);
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int epic_mii_wait(struct epic_softc *, uint32_t);
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void epic_tick(void *);
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void epic_tick(void *);
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void epic_statchg(struct device *);
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void epic_statchg(struct device *);
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@ -121,8 +121,8 @@ epic_attach(sc)
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int rseg, error, miiflags;
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int rseg, error, miiflags;
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u_int i;
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u_int i;
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bus_dma_segment_t seg;
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bus_dma_segment_t seg;
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u_int8_t enaddr[ETHER_ADDR_LEN], devname[12 + 1];
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uint8_t enaddr[ETHER_ADDR_LEN], devname[12 + 1];
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u_int16_t myea[ETHER_ADDR_LEN / 2], mydevname[6];
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uint16_t myea[ETHER_ADDR_LEN / 2], mydevname[6];
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char *nullbuf;
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char *nullbuf;
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callout_init(&sc->sc_mii_callout);
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callout_init(&sc->sc_mii_callout);
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@ -615,7 +615,7 @@ epic_intr(arg)
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struct epic_txdesc *txd;
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struct epic_txdesc *txd;
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struct epic_descsoft *ds;
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struct epic_descsoft *ds;
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struct mbuf *m;
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struct mbuf *m;
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u_int32_t intstat, rxstatus, txstatus;
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uint32_t intstat, rxstatus, txstatus;
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int i, claimed = 0;
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int i, claimed = 0;
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u_int len;
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u_int len;
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@ -929,10 +929,10 @@ epic_init(ifp)
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struct epic_softc *sc = ifp->if_softc;
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struct epic_softc *sc = ifp->if_softc;
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bus_space_tag_t st = sc->sc_st;
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bus_space_tag_t st = sc->sc_st;
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bus_space_handle_t sh = sc->sc_sh;
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bus_space_handle_t sh = sc->sc_sh;
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u_int8_t *enaddr = LLADDR(ifp->if_sadl);
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uint8_t *enaddr = LLADDR(ifp->if_sadl);
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struct epic_txdesc *txd;
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struct epic_txdesc *txd;
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struct epic_descsoft *ds;
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struct epic_descsoft *ds;
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u_int32_t genctl, reg0;
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uint32_t genctl, reg0;
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int i, error = 0;
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int i, error = 0;
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/*
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/*
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@ -1113,7 +1113,7 @@ epic_stop(ifp, disable)
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bus_space_tag_t st = sc->sc_st;
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bus_space_tag_t st = sc->sc_st;
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bus_space_handle_t sh = sc->sc_sh;
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bus_space_handle_t sh = sc->sc_sh;
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struct epic_descsoft *ds;
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struct epic_descsoft *ds;
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u_int32_t reg;
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uint32_t reg;
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int i;
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int i;
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/*
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/*
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@ -1169,11 +1169,11 @@ void
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epic_read_eeprom(sc, word, wordcnt, data)
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epic_read_eeprom(sc, word, wordcnt, data)
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struct epic_softc *sc;
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struct epic_softc *sc;
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int word, wordcnt;
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int word, wordcnt;
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u_int16_t *data;
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uint16_t *data;
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{
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{
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bus_space_tag_t st = sc->sc_st;
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bus_space_tag_t st = sc->sc_st;
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bus_space_handle_t sh = sc->sc_sh;
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bus_space_handle_t sh = sc->sc_sh;
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u_int16_t reg;
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uint16_t reg;
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int i, x;
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int i, x;
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#define EEPROM_WAIT_READY(st, sh) \
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#define EEPROM_WAIT_READY(st, sh) \
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@ -1299,7 +1299,7 @@ epic_set_mchash(sc)
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struct ifnet *ifp = &sc->sc_ethercom.ec_if;
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struct ifnet *ifp = &sc->sc_ethercom.ec_if;
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struct ether_multi *enm;
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struct ether_multi *enm;
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struct ether_multistep step;
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struct ether_multistep step;
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u_int32_t hash, mchash[4];
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uint32_t hash, mchash[4];
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/*
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/*
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* Set up the multicast address filter by passing all multicast
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* Set up the multicast address filter by passing all multicast
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int
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int
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epic_mii_wait(sc, rw)
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epic_mii_wait(sc, rw)
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struct epic_softc *sc;
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struct epic_softc *sc;
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u_int32_t rw;
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uint32_t rw;
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{
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{
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int i;
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int i;
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@ -1430,7 +1430,7 @@ epic_statchg(self)
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struct device *self;
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struct device *self;
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{
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{
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struct epic_softc *sc = (struct epic_softc *)self;
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struct epic_softc *sc = (struct epic_softc *)self;
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u_int32_t txcon, miicfg;
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uint32_t txcon, miicfg;
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/*
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/*
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* Update loopback bits in TXCON to reflect duplex mode.
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* Update loopback bits in TXCON to reflect duplex mode.
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@ -1485,7 +1485,7 @@ epic_mediachange(ifp)
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struct mii_data *mii = &sc->sc_mii;
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struct mii_data *mii = &sc->sc_mii;
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struct ifmedia *ifm = &mii->mii_media;
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struct ifmedia *ifm = &mii->mii_media;
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int media = ifm->ifm_cur->ifm_media;
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int media = ifm->ifm_cur->ifm_media;
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u_int32_t miicfg;
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uint32_t miicfg;
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struct mii_softc *miisc;
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struct mii_softc *miisc;
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int cfg;
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int cfg;
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/* $NetBSD: smc83c170reg.h,v 1.10 2005/12/11 12:21:28 christos Exp $ */
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/* $NetBSD: smc83c170reg.h,v 1.11 2006/04/16 00:38:59 tsutsui Exp $ */
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/*-
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* EPIC transmit descriptor. Must be 4-byte aligned.
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* EPIC transmit descriptor. Must be 4-byte aligned.
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*/
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*/
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struct epic_txdesc {
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struct epic_txdesc {
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u_int32_t et_txstatus; /* transmit status; see below */
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uint32_t et_txstatus; /* transmit status; see below */
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u_int32_t et_bufaddr; /* buffer address */
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uint32_t et_bufaddr; /* buffer address */
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u_int32_t et_control; /* control word; see below */
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uint32_t et_control; /* control word; see below */
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u_int32_t et_nextdesc; /* next descriptor pointer */
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uint32_t et_nextdesc; /* next descriptor pointer */
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};
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};
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/* et_txstatus */
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/* et_txstatus */
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* EPIC receive descriptor. Must be 4-byte aligned.
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* EPIC receive descriptor. Must be 4-byte aligned.
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*/
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*/
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struct epic_rxdesc {
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struct epic_rxdesc {
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u_int32_t er_rxstatus; /* receive status; see below */
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uint32_t er_rxstatus; /* receive status; see below */
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u_int32_t er_bufaddr; /* buffer address */
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uint32_t er_bufaddr; /* buffer address */
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u_int32_t er_control; /* control word; see below */
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uint32_t er_control; /* control word; see below */
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u_int32_t er_nextdesc; /* next descriptor pointer */
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uint32_t er_nextdesc; /* next descriptor pointer */
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};
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};
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/* er_rxstatus */
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/* er_rxstatus */
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* EPIC fraglist descriptor.
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* EPIC fraglist descriptor.
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*/
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*/
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struct epic_fraglist {
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struct epic_fraglist {
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u_int32_t ef_nfrags; /* number of frags in list */
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uint32_t ef_nfrags; /* number of frags in list */
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struct {
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struct {
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u_int32_t ef_addr; /* address of frag */
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uint32_t ef_addr; /* address of frag */
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u_int32_t ef_length; /* length of frag */
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uint32_t ef_length; /* length of frag */
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} ef_frags[EPIC_NFRAGS];
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} ef_frags[EPIC_NFRAGS];
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};
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};
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