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interupt -> interrupt

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This commit is contained in:
christos 2020-12-16 19:49:04 +00:00
parent ab208996b3
commit a5a15771d1
10 changed files with 31 additions and 31 deletions
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8
sys/arch/arm/broadcom/bcm2835_intr.c
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@ -1,4 +1,4 @@
/* $NetBSD: bcm2835_intr.c,v 1.32 2020/02/15 08:16:11 skrll Exp $ */
/* $NetBSD: bcm2835_intr.c,v 1.33 2020/12/16 19:49:04 christos Exp $ */
/*-
* Copyright (c) 2012, 2015, 2019 The NetBSD Foundation, Inc.
@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: bcm2835_intr.c,v 1.32 2020/02/15 08:16:11 skrll Exp $");
__KERNEL_RCSID(0, "$NetBSD: bcm2835_intr.c,v 1.33 2020/12/16 19:49:04 christos Exp $");
#define _INTR_PRIVATE
@ -891,8 +891,8 @@ bcm2836mp_icu_fdt_establish(device_t dev, u_int *specifier, int ipl, int flags,
bip->bi_arg = arg;
/*
* If we're not cold and the BPs have been started then we can register the
* interupt for all CPUs now, e.g. PMU
* If we're not cold and the BPs have been started then we can
* register the interrupt for all CPUs now, e.g. PMU
*/
if (!cold) {
for (cpuid_t cpuid = 0; cpuid < BCM2836_NCPUS; cpuid++) {

6
sys/arch/riscv/include/sysreg.h
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@ -1,4 +1,4 @@
/* $NetBSD: sysreg.h,v 1.10 2020/11/04 20:05:47 skrll Exp $ */
/* $NetBSD: sysreg.h,v 1.11 2020/12/16 19:49:04 christos Exp $ */
/*
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@ -141,7 +141,7 @@ riscvreg_fcsr_write_frm(uint32_t __new)
#define SR_UIE __BIT(0)
/* Supervisor interrupt registers */
/* ... interupt pending register (sip) */
/* ... interrupt pending register (sip) */
/* Bit (XLEN-1)-10 is WIRI */
#define SIP_SEIP __BIT(9)
#define SIP_UEIP __BIT(8)
@ -152,7 +152,7 @@ riscvreg_fcsr_write_frm(uint32_t __new)
#define SIP_SSIP __BIT(1)
#define SIP_USIP __BIT(0)
/* ... interupt-enable register (sie) */
/* ... interrupt-enable register (sie) */
/* Bit (XLEN-1) - 10 is WIRI */
#define SIE_SEIE __BIT(9)
#define SIE_UEIE __BIT(8)

6
sys/dev/i2c/tcakp.c
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@ -1,4 +1,4 @@
/* $NetBSD: tcakp.c,v 1.11 2019/12/23 20:38:08 thorpej Exp $ */
/* $NetBSD: tcakp.c,v 1.12 2020/12/16 19:49:04 christos Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
@ -29,7 +29,7 @@
#include "opt_fdt.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: tcakp.c,v 1.11 2019/12/23 20:38:08 thorpej Exp $");
__KERNEL_RCSID(0, "$NetBSD: tcakp.c,v 1.12 2020/12/16 19:49:04 christos Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -400,7 +400,7 @@ tcakp_attach(device_t parent, device_t self, void *aux)
sc->sc_sih = softint_establish(SOFTINT_SERIAL, tcakp_softintr, sc);
if (sc->sc_sih == NULL) {
aprint_error_dev(sc->sc_dev,
"unable to establish soft interupt\n");
"unable to establish soft interrupt\n");
return;
}

8
sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_uvd_v4_2.c vendored
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@ -1,4 +1,4 @@
/* $NetBSD: amdgpu_uvd_v4_2.c,v 1.3 2020/02/14 14:34:58 maya Exp $ */
/* $NetBSD: amdgpu_uvd_v4_2.c,v 1.4 2020/12/16 19:49:05 christos Exp $ */
/*
* Copyright 2013 Advanced Micro Devices, Inc.
@ -25,7 +25,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: amdgpu_uvd_v4_2.c,v 1.3 2020/02/14 14:34:58 maya Exp $");
__KERNEL_RCSID(0, "$NetBSD: amdgpu_uvd_v4_2.c,v 1.4 2020/12/16 19:49:05 christos Exp $");
#include <linux/firmware.h>
#include <drm/drmP.h>
@ -278,7 +278,7 @@ static int uvd_v4_2_start(struct amdgpu_device *adev)
/* disable clock gating */
WREG32(mmUVD_CGC_GATE, 0);
/* disable interupt */
/* disable interrupt */
WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
/* Stall UMC and register bus before resetting VCPU */
@ -356,7 +356,7 @@ static int uvd_v4_2_start(struct amdgpu_device *adev)
return r;
}
/* enable interupt */
/* enable interrupt */
WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1));
/* force RBC into idle state */

6
sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_uvd_v5_0.c vendored
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@ -1,4 +1,4 @@
/* $NetBSD: amdgpu_uvd_v5_0.c,v 1.2 2020/02/14 14:34:58 maya Exp $ */
/* $NetBSD: amdgpu_uvd_v5_0.c,v 1.3 2020/12/16 19:49:05 christos Exp $ */
/*
* Copyright 2014 Advanced Micro Devices, Inc.
@ -25,7 +25,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: amdgpu_uvd_v5_0.c,v 1.2 2020/02/14 14:34:58 maya Exp $");
__KERNEL_RCSID(0, "$NetBSD: amdgpu_uvd_v5_0.c,v 1.3 2020/12/16 19:49:05 christos Exp $");
#include <linux/firmware.h>
#include <drm/drmP.h>
@ -313,7 +313,7 @@ static int uvd_v5_0_start(struct amdgpu_device *adev)
/* disable clock gating */
WREG32(mmUVD_CGC_GATE, 0);
/* disable interupt */
/* disable interrupt */
WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
/* stall UMC and register bus before resetting VCPU */

6
sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_uvd_v6_0.c vendored
View File

@ -1,4 +1,4 @@
/* $NetBSD: amdgpu_uvd_v6_0.c,v 1.2 2020/02/14 14:34:58 maya Exp $ */
/* $NetBSD: amdgpu_uvd_v6_0.c,v 1.3 2020/12/16 19:49:05 christos Exp $ */
/*
* Copyright 2014 Advanced Micro Devices, Inc.
@ -25,7 +25,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: amdgpu_uvd_v6_0.c,v 1.2 2020/02/14 14:34:58 maya Exp $");
__KERNEL_RCSID(0, "$NetBSD: amdgpu_uvd_v6_0.c,v 1.3 2020/12/16 19:49:05 christos Exp $");
#include <linux/firmware.h>
#include <drm/drmP.h>
@ -311,7 +311,7 @@ static int uvd_v6_0_start(struct amdgpu_device *adev)
/* disable clock gating */
WREG32(mmUVD_CGC_GATE, 0);
/* disable interupt */
/* disable interrupt */
WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
/* stall UMC and register bus before resetting VCPU */

6
sys/external/bsd/drm2/dist/drm/i915/intel_pm.c vendored
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@ -1,4 +1,4 @@
/* $NetBSD: intel_pm.c,v 1.24 2020/02/14 14:34:58 maya Exp $ */
/* $NetBSD: intel_pm.c,v 1.25 2020/12/16 19:49:05 christos Exp $ */
/*
* Copyright © 2012 Intel Corporation
@ -28,7 +28,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: intel_pm.c,v 1.24 2020/02/14 14:34:58 maya Exp $");
__KERNEL_RCSID(0, "$NetBSD: intel_pm.c,v 1.25 2020/12/16 19:49:05 christos Exp $");
#include <linux/cpufreq.h>
#include "i915_drv.h"
@ -4433,7 +4433,7 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
{
u32 mask = 0;
/* We use UP_EI_EXPIRED interupts for both up/down in manual mode */
/* We use UP_EI_EXPIRED interrupts for both up/down in manual mode */
if (val > dev_priv->rps.min_freq_softlimit)
mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
if (val < dev_priv->rps.max_freq_softlimit)

8
sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v1_0.c vendored
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@ -1,4 +1,4 @@
/* $NetBSD: radeon_uvd_v1_0.c,v 1.3 2019/08/17 15:50:05 msaitoh Exp $ */
/* $NetBSD: radeon_uvd_v1_0.c,v 1.4 2020/12/16 19:49:05 christos Exp $ */
/*
* Copyright 2013 Advanced Micro Devices, Inc.
@ -25,7 +25,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: radeon_uvd_v1_0.c,v 1.3 2019/08/17 15:50:05 msaitoh Exp $");
__KERNEL_RCSID(0, "$NetBSD: radeon_uvd_v1_0.c,v 1.4 2020/12/16 19:49:05 christos Exp $");
#include <linux/firmware.h>
#include <drm/drmP.h>
@ -277,7 +277,7 @@ int uvd_v1_0_start(struct radeon_device *rdev)
/* disable clock gating */
WREG32(UVD_CGC_GATE, 0);
/* disable interupt */
/* disable interrupt */
WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1));
/* Stall UMC and register bus before resetting VCPU */
@ -355,7 +355,7 @@ int uvd_v1_0_start(struct radeon_device *rdev)
return r;
}
/* enable interupt */
/* enable interrupt */
WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1));
/* force RBC into idle state */

4
sys/external/bsd/drm2/dist/drm/vmwgfx/vmwgfx_drv.h vendored
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@ -1,4 +1,4 @@
/* $NetBSD: vmwgfx_drv.h,v 1.2 2018/08/27 04:58:37 riastradh Exp $ */
/* $NetBSD: vmwgfx_drv.h,v 1.3 2020/12/16 19:49:05 christos Exp $ */
/**************************************************************************
*
@ -623,7 +623,7 @@ extern void vmw_dmabuf_bo_free(struct ttm_buffer_object *bo);
extern int vmw_dmabuf_init(struct vmw_private *dev_priv,
struct vmw_dma_buffer *vmw_bo,
size_t size, struct ttm_placement *placement,
bool interuptable,
bool interruptible,
void (*bo_free) (struct ttm_buffer_object *bo));
extern int vmw_user_dmabuf_verify_access(struct ttm_buffer_object *bo,
struct ttm_object_file *tfile);

4
sys/external/isc/atheros_hal/dist/ah.h vendored
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@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ah.h,v 1.4 2011/03/07 11:25:42 cegger Exp $
* $Id: ah.h,v 1.5 2020/12/16 19:49:05 christos Exp $
*/
#ifndef _ATH_AH_H_
@ -109,7 +109,7 @@ typedef enum {
HAL_CAP_RXTSTAMP_PREC = 34, /* rx desc tstamp precision (bits) */
HAL_CAP_BB_HANG = 35, /* can baseband hang */
HAL_CAP_MAC_HANG = 36, /* can MAC hang */
HAL_CAP_INTRMASK = 37, /* bitmask of supported interupts */
HAL_CAP_INTRMASK = 37, /* bitmask of supported interrupts */
HAL_CAP_BSSIDMATCH = 38, /* hardware has disable bssid match */
} HAL_CAPABILITY_TYPE;