Fix multiple problems with ldrh/strh/ldrsb/ldrsh disassembly:
* The offset format was wrong. * There is no post-increment or index register update. * It wasn't even matching because the mask was wrong. Also touch up ldr/str disassembly slightly.
This commit is contained in:
mycroft
parent
266f8437dd
commit
a589baf905
@ -1,4 +1,4 @@
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/* $NetBSD: disassem.c,v 1.12 2002/03/10 15:47:43 bjh21 Exp $ */
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/* $NetBSD: disassem.c,v 1.13 2003/03/27 16:42:40 mycroft Exp $ */
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/*
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* Copyright (c) 1996 Mark Brinicombe.
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@ -49,7 +49,7 @@
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#include <sys/param.h>
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__KERNEL_RCSID(0, "$NetBSD: disassem.c,v 1.12 2002/03/10 15:47:43 bjh21 Exp $");
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__KERNEL_RCSID(0, "$NetBSD: disassem.c,v 1.13 2003/03/27 16:42:40 mycroft Exp $");
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#include <sys/systm.h>
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#include <arch/arm/arm/disassem.h>
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@ -85,11 +85,9 @@ __KERNEL_RCSID(0, "$NetBSD: disassem.c,v 1.12 2002/03/10 15:47:43 bjh21 Exp $");
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* c - comment field bits(0-23)
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* p - saved or current status register
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* F - PSR transfer fields
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* B - byte transfer flag
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* D - destination-is-r15 (P) flag on TST, TEQ, CMP, CMN
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* L - co-processor transfer size
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* S - set status flag
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* T - user mode transfer
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* P - fp precision
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* Q - fp precision (for ldf/stf)
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* R - fp rounding
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@ -121,21 +119,28 @@ static const struct arm32_insn arm32_i[] = {
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{ 0x0fe000f0, 0x00c00090, "smull", "Sdnms" },
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{ 0x0fe000f0, 0x00a00090, "umlal", "Sdnms" },
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{ 0x0fe000f0, 0x00e00090, "smlal", "Sdnms" },
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{ 0x0e100000, 0x04000000, "str", "BTdaW" },
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{ 0x0e100000, 0x04100000, "ldr", "BTdaW" },
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{ 0x0c100010, 0x04000000, "str", "BTdaW" },
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{ 0x0c100010, 0x04100000, "ldr", "BTdaW" },
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{ 0x0d700010, 0x04200000, "strt", "daW" },
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{ 0x0d700010, 0x04300000, "ldrt", "daW" },
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{ 0x0d700010, 0x04600000, "strbt", "daW" },
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{ 0x0d700010, 0x04700000, "ldrbt", "daW" },
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{ 0x0c500010, 0x04000000, "str", "daW" },
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{ 0x0c500010, 0x04100000, "ldr", "daW" },
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{ 0x0c500010, 0x04400000, "strb", "daW" },
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{ 0x0c500010, 0x04500000, "ldrb", "daW" },
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{ 0x0e1f0000, 0x080d0000, "stm", "YnWl" },/* separate out r13 base */
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{ 0x0e1f0000, 0x081d0000, "ldm", "YnWl" },/* separate out r13 base */
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{ 0x0e100000, 0x08000000, "stm", "XnWl" },
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{ 0x0e100000, 0x08100000, "ldm", "XnWl" },
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{ 0x0e500ff0, 0x001000b0, "ldrh", "daW" },
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{ 0x0e500ff0, 0x000000b0, "strh", "daW" },
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{ 0x0e500ff0, 0x001000d0, "ldrsb", "daW" },
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{ 0x0e500ff0, 0x001000f0, "ldrsh", "daW" },
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{ 0x0e1000f0, 0x00100090, "ldrb", "de" },
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{ 0x0e1000f0, 0x00000090, "strb", "de" },
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{ 0x0e1000f0, 0x001000d0, "ldrsb", "de" },
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{ 0x0e1000f0, 0x001000b0, "ldrh", "de" },
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{ 0x0e1000f0, 0x000000b0, "strh", "de" },
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{ 0x0e1000f0, 0x001000f0, "ldrsh", "de" },
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{ 0x0f200090, 0x00200090, "und", "x" }, /* Before data processing */
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{ 0x0e1000d0, 0x000000d0, "und", "x" }, /* Before data processing */
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{ 0x0fb00ff0, 0x01000090, "swp", "Bdmo" },
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{ 0x0ff00ff0, 0x01000090, "swp", "dmo" },
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{ 0x0ff00ff0, 0x01400090, "swpb", "dmo" },
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{ 0x0fbf0fff, 0x010f0000, "mrs", "dp" }, /* Before data processing */
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{ 0x0fb0fff0, 0x0120f000, "msr", "pFm" },/* Before data processing */
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{ 0x0fb0f000, 0x0320f000, "msr", "pF2" },/* Before data processing */
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@ -259,6 +264,8 @@ static void disasm_register_shift(const disasm_interface_t *di, u_int insn);
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static void disasm_print_reglist(const disasm_interface_t *di, u_int insn);
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static void disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn,
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u_int loc);
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static void disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn,
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u_int loc);
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static void disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn,
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u_int loc);
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static u_int disassemble_readword(u_int address);
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@ -352,6 +359,10 @@ disasm(const disasm_interface_t *di, vaddr_t loc, int altfmt)
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case 'a':
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disasm_insn_ldrstr(di, insn, loc);
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break;
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/* e - address operand of ldrh/strh instruction */
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case 'e':
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disasm_insn_ldrhstrh(di, insn, loc);
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break;
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/* l - register list for ldm/stm instruction */
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case 'l':
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disasm_print_reglist(di, insn);
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@ -437,13 +448,8 @@ disasm(const disasm_interface_t *di, vaddr_t loc, int altfmt)
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if (insn & 0x00100000)
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di->di_printf("s");
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break;
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/* T - user mode transfer */
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case 'T':
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if ((insn & 0x01200000) == 0x00200000)
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di->di_printf("t");
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break;
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case 'P':
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/* P - fp precision */
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case 'P':
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di->di_printf("%s", insn_fpaprec(insn));
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break;
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/* Q - fp precision (for ldf/stf) */
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@ -567,28 +573,60 @@ disasm_print_reglist(const disasm_interface_t *di, u_int insn)
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static void
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disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn, u_int loc)
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{
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if ((((insn >> 16) & 0x0f) == 15) && ((insn & (1 << 21)) == 0)
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&& ((insn & (1 << 24)) != 0) && ((insn & (1 << 25)) == 0)) {
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int offset;
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offset = insn & 0xfff;
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if ((insn & 0x032f0000) == 0x010f0000) {
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/* rA = pc, immediate index */
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if (insn & 0x00800000)
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loc += (insn & 0xfff);
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loc += offset;
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else
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loc -= (insn & 0xfff);
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loc -= offset;
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di->di_printaddr(loc + 8);
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} else {
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di->di_printf("[r%d", (insn >> 16) & 0x0f);
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di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]");
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if (!(insn & 0x00800000))
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di->di_printf("-");
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if (insn & (1 << 25))
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disasm_register_shift(di, insn);
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else
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di->di_printf("#0x%04x", insn & 0xfff);
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if ((insn & 0x03000fff) != 0x01000000) {
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di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]");
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if (!(insn & 0x00800000))
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di->di_printf("-");
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if (insn & (1 << 25))
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disasm_register_shift(di, insn);
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else
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di->di_printf("#0x%03x", offset);
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}
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if (insn & (1 << 24))
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di->di_printf("]");
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}
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}
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static void
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disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn, u_int loc)
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{
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int offset;
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offset = ((insn & 0xf00) >> 4) | (insn & 0xf);
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if ((insn & 0x004f0000) == 0x004f0000) {
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/* rA = pc, immediate index */
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if (insn & 0x00800000)
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loc += offset;
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else
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loc -= offset;
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di->di_printaddr(loc + 8);
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} else {
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di->di_printf("[r%d", (insn >> 16) & 0x0f);
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if ((insn & 0x01400f0f) != 0x01400000) {
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di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]");
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if (!(insn & 0x00800000))
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di->di_printf("-");
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if (insn & (1 << 22))
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di->di_printf("#0x%02x", offset);
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else
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di->di_printf("r%d", (insn & 0x0f));
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}
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if (insn & (1 << 24))
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di->di_printf("]");
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}
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}
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static void
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disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn, u_int loc)
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