OMAP4/OMAP5 changes.
This commit is contained in:
matt
parent
d101c0e239
commit
a579e160ac
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@ -1,4 +1,4 @@
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/* $NetBSD: omap2_reg.h,v 1.23 2013/06/20 05:27:31 matt Exp $ */
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/* $NetBSD: omap2_reg.h,v 1.24 2014/03/29 23:32:41 matt Exp $ */
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/*
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* Copyright (c) 2007 Microsoft
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@ -363,6 +363,47 @@
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#define TI_AM335X_CM_DIV_M2_DPLL_MPU_DPLL_CLKOUT_DIVCHACK __BIT(5)
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#define TI_AM335X_CM_DIV_M2_DPLL_MPU_DPLL_CLKOUT_DIV __BITS(4,0)
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#define OMAP4_CM_L3INIT_CORE 0x5300 /* OMAP2_CM_BASE */
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#define OMAP5_CM_L3INIT_CORE 0x5600 /* OMAP2_CM_BASE */
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#define OMAP4_CM_L3INIT_HSMMC1_CLKCTRL 0x0008
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#define OMAP4_CM_L3INIT_HSMMC2_CLKCTRL 0x0030
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#define OMAP5_CM_L3INIT_HSMMC_CLKCTRL_CLKSEL_DIV2 __BIT(25)
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#define OMAP4_CM_L3INIT_HSMMC_CLKCTRL_CLKSEL __BIT(24)
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#define OMAP5_CM_L3INIT_HSMMC_CLKCTRL_OPTFCLKEN_32KHZ_CLK __BIT(8)
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#define OMAP4_CM_L3INIT_HSMMC_CLKCTRL_MODELMODE __BITS(1,0)
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#define OMAP4_CM_L3INIT_HSMMC_CLKCTRL_MODELMODE_HW 2
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#define OMAP4_CM_L3INIT_HSI_CLKCTRL 0x0038
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#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL 0x0058
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#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_CLKSEL_UTMI_P2 __BIT(25)
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#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_CLKSEL_UTMI_P1 __BIT(24)
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#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_FUNC48M_CLK __BIT(15)
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#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC480M_P2_CLK __BIT(14)
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#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC480M_P1_CLK __BIT(13)
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#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC60M_P2_CLK __BIT(12)
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#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC60M_P1_CLK __BIT(11)
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#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_UTMI_P3_CLK __BIT(10)
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#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_UTMI_P2_CLK __BIT(9)
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#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_UTMI_P1_CLK __BIT(8)
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#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC480M_P3_CLK __BIT(7)
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#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC60M_P3_CLK __BIT(6)
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#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_MODULEMODE __BITS(1,0)
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#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_MODULEMODE_HW 2
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#define OMAP4_CM_L3INIT_USB_OTG_HS_CLKCTRL 0x0060
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#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_CLKSEL_60M __BIT(24)
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#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_OPTFCLKEN_XCLK __BIT(8)
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#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_MODULEMODE __BITS(1,0)
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#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_MODULEMODE_HW 1
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#define OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL 0x0068
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#define OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL_USB_CH2_CLK __BIT(10)
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#define OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL_USB_CH1_CLK __BIT(9)
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#define OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL_USB_CH0_CLK __BIT(8)
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#define OMAP5_CM_L3INIT_SATA_CLKCTRL 0x0088
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#define OMAP5_CM_L3INIT_SATA_CLKCTRL_OPTFCLKEN_REF_CLK __BIT(8)
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#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL 0x00F0
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#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_OPTFCLKEN_REFCLK960M __BIT(8)
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#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_MODULEMODE __BITS(1,0)
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#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_MODULEMODE_HW 1
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/*
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* Power Management registers base, offsets, and size
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*/
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@ -763,8 +804,8 @@
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#define OHCI1_BASE_OMAP3 0x48064400
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#define EHCI1_BASE_OMAP3 0x48064800
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#define OHCI1_BASE_OMAP4 0x4A064800
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#define EHCI1_BASE_OMAP4 0x4A064C00
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#define OHCI1_BASE_OMAP4 0x4A064800 /* also OMAP5 */
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#define EHCI1_BASE_OMAP4 0x4A064C00 /* also OMAP5 */
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/*
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* SDRC
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@ -781,6 +822,7 @@
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/*
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* PL310 L2CC (44xx)
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*/
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#define OMAP4_SCU_BASE 0x48240000
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#define OMAP4_L2CC_BASE 0x48242000
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#define OMAP4_L2CC_SIZE 0x00001000 /* 4KB */
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@ -788,6 +830,13 @@
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#define AHCI1_BASE_OMAP5 0x4a140000
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/* These also apply to OMAP5 */
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#define OMAP4_WUGEN_BASE 0x48281000
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#define OMAP4_WKG_CONTROL_0 0x00000000
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#define OMAP4_WKG_CONTROL_1 0x00000400
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#define OMAP4_AUX_CORE_BOOT0 0x00000800
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#define OMAP4_AUX_CORE_BOOT1 0x00000804
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#define OMAP5_PRM_FRAC_INCREMENTER_NUMERATOR 0x48243210
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#define PRM_FRAC_INCR_NUM_ABE_LP_MODE __BITS(27,16)
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#define PRM_FRAC_INCR_NUM_SYS_MODE __BITS(11,0)
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@ -1,4 +1,4 @@
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/* $NetBSD: omap3_ehci.c,v 1.9 2013/06/18 15:23:18 matt Exp $ */
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/* $NetBSD: omap3_ehci.c,v 1.10 2014/03/29 23:32:41 matt Exp $ */
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/*-
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* Copyright (c) 2010-2012 Jared D. McNeill <jmcneill@invisible.ca>
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@ -26,7 +26,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: omap3_ehci.c,v 1.9 2013/06/18 15:23:18 matt Exp $");
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__KERNEL_RCSID(0, "$NetBSD: omap3_ehci.c,v 1.10 2014/03/29 23:32:41 matt Exp $");
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#include "locators.h"
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@ -110,7 +110,7 @@ __KERNEL_RCSID(0, "$NetBSD: omap3_ehci.c,v 1.9 2013/06/18 15:23:18 matt Exp $");
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/* USBTLL module */
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#ifdef OMAP_3XXX
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#define USBTLL_BASE 0x48062000
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#elif defined(OMAP4)
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#elif defined(OMAP4) || defined(OMAP5)
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#define USBTLL_BASE 0x4a062000
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#endif
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#define USBTLL_SIZE 0x1000
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@ -118,7 +118,7 @@ __KERNEL_RCSID(0, "$NetBSD: omap3_ehci.c,v 1.9 2013/06/18 15:23:18 matt Exp $");
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/* HS USB HOST module */
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#ifdef OMAP_3XXX
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#define UHH_BASE 0x48064000
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#elif defined(OMAP4)
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#elif defined(OMAP4) || defined(OMAP5)
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#define UHH_BASE 0x4a064000
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#endif
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#define UHH_SIZE 0x1000
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@ -127,6 +127,57 @@ enum omap3_ehci_port_mode {
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OMAP3_EHCI_PORT_MODE_NONE,
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OMAP3_EHCI_PORT_MODE_PHY,
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OMAP3_EHCI_PORT_MODE_TLL,
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OMAP3_EHCI_PORT_MODE_HSIC,
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};
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static const uint32_t uhh_map[3][4] = {
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#if defined(OMAP4) || defined(OMAP5)
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{
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[OMAP3_EHCI_PORT_MODE_NONE] =
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__SHIFTIN(UHH_HOSTCONFIG_PMODE_UTMI, UHH_HOSTCONFIG_P1_MODE),
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[OMAP3_EHCI_PORT_MODE_PHY] =
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__SHIFTIN(UHH_HOSTCONFIG_PMODE_ULPI_PHY, UHH_HOSTCONFIG_P1_MODE),
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[OMAP3_EHCI_PORT_MODE_TLL] =
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__SHIFTIN(UHH_HOSTCONFIG_PMODE_UTMI, UHH_HOSTCONFIG_P1_MODE),
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[OMAP3_EHCI_PORT_MODE_HSIC] =
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__SHIFTIN(UHH_HOSTCONFIG_PMODE_HSIC, UHH_HOSTCONFIG_P1_MODE),
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}, {
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[OMAP3_EHCI_PORT_MODE_NONE] =
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__SHIFTIN(UHH_HOSTCONFIG_PMODE_UTMI, UHH_HOSTCONFIG_P2_MODE),
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[OMAP3_EHCI_PORT_MODE_PHY] =
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__SHIFTIN(UHH_HOSTCONFIG_PMODE_ULPI_PHY, UHH_HOSTCONFIG_P2_MODE),
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[OMAP3_EHCI_PORT_MODE_TLL] =
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__SHIFTIN(UHH_HOSTCONFIG_PMODE_UTMI, UHH_HOSTCONFIG_P2_MODE),
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[OMAP3_EHCI_PORT_MODE_HSIC] =
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__SHIFTIN(UHH_HOSTCONFIG_PMODE_HSIC, UHH_HOSTCONFIG_P2_MODE),
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}, {
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[OMAP3_EHCI_PORT_MODE_NONE] =
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__SHIFTIN(UHH_HOSTCONFIG_PMODE_UTMI, UHH_HOSTCONFIG_P3_MODE),
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[OMAP3_EHCI_PORT_MODE_PHY] =
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__SHIFTIN(UHH_HOSTCONFIG_PMODE_ULPI_PHY, UHH_HOSTCONFIG_P3_MODE),
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[OMAP3_EHCI_PORT_MODE_TLL] =
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__SHIFTIN(UHH_HOSTCONFIG_PMODE_UTMI, UHH_HOSTCONFIG_P3_MODE),
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[OMAP3_EHCI_PORT_MODE_HSIC] =
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__SHIFTIN(UHH_HOSTCONFIG_PMODE_HSIC, UHH_HOSTCONFIG_P3_MODE),
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}
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#else
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{
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[OMAP3_EHCI_PORT_MODE_NONE] = UHH_HOSTCONFIG_P1_ULPI_BYPASS,
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[OMAP3_EHCI_PORT_MODE_PHY] = 0,
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[OMAP3_EHCI_PORT_MODE_TLL] = UHH_HOSTCONFIG_P1_ULPI_BYPASS,
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[OMAP3_EHCI_PORT_MODE_HSIC] = UHH_HOSTCONFIG_P1_ULPI_BYPASS,
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}, {
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[OMAP3_EHCI_PORT_MODE_NONE] = UHH_HOSTCONFIG_P2_ULPI_BYPASS,
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[OMAP3_EHCI_PORT_MODE_PHY] = 0,
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[OMAP3_EHCI_PORT_MODE_TLL] = UHH_HOSTCONFIG_P2_ULPI_BYPASS,
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[OMAP3_EHCI_PORT_MODE_HSIC] = UHH_HOSTCONFIG_P2_ULPI_BYPASS,
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}, {
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[OMAP3_EHCI_PORT_MODE_NONE] = UHH_HOSTCONFIG_P3_ULPI_BYPASS,
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[OMAP3_EHCI_PORT_MODE_PHY] = 0,
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[OMAP3_EHCI_PORT_MODE_TLL] = UHH_HOSTCONFIG_P3_ULPI_BYPASS,
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[OMAP3_EHCI_PORT_MODE_HSIC] = UHH_HOSTCONFIG_P3_ULPI_BYPASS,
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},
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#endif
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};
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struct omap3_ehci_softc {
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@ -155,6 +206,9 @@ struct omap3_ehci_softc {
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static void omap3_dpll5_init(struct omap3_ehci_softc *);
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static void omap3_usbhost_init(struct omap3_ehci_softc *, int);
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#endif
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#if defined(OMAP4) || defined(OMAP5)
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static void omap4_usbhost_init(struct omap3_ehci_softc *, int);
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#endif
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static void usbtll_reset(struct omap3_ehci_softc *);
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static void usbtll_power(struct omap3_ehci_softc *, bool);
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static void usbtll_init(struct omap3_ehci_softc *, int);
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@ -297,7 +351,7 @@ omap3_ehci_match(device_t parent, cfdata_t match, void *opaque)
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if (obio->obio_addr == EHCI1_BASE_OMAP3)
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return 1;
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#endif
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#ifdef OMAP4
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#if defined(OMAP4) || defined(OMAP5)
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if (obio->obio_addr == EHCI1_BASE_OMAP4)
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return 1;
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#endif
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@ -318,6 +372,14 @@ omap3_ehci_get_port_mode(prop_dictionary_t prop, const char *key)
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} else if (strcmp(s, "tll") == 0) {
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mode = OMAP3_EHCI_PORT_MODE_TLL;
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#endif
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#if defined(OMAP4) || defined(OMAP5)
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} else if (strcmp(s, "hsic") == 0) {
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mode = OMAP3_EHCI_PORT_MODE_HSIC;
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#endif
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} else if (strcmp(s, "none") == 0) {
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mode = OMAP3_EHCI_PORT_MODE_NONE;
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} else {
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panic("%s: unknown port mode %s", __func__, s);
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}
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}
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@ -415,6 +477,9 @@ omap3_ehci_attach(device_t parent, device_t self, void *opaque)
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omap3_usbhost_init(sc, 1);
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#endif /* OMAP_3XXX */
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#if defined(OMAP4) || defined(OMAP5)
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omap4_usbhost_init(sc, 1);
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#endif
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sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH);
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@ -587,6 +652,40 @@ omap3_usbhost_init(struct omap3_ehci_softc *sc, int enable)
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}
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#endif /* OMAP_3XXX */
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#if defined(OMAP4) || defined(OMAP5)
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static void
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omap4_usbhost_init(struct omap3_ehci_softc *sc, int enable)
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{
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bus_space_tag_t iot = sc->sc.iot;
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bus_space_handle_t ioh;
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uint32_t val;
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int err __diagused;
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#ifdef OMAP5
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bus_size_t off = OMAP5_CM_L3INIT_CORE;
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#elif defined(OMAP4)
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bus_size_t off = OMAP4_CM_L3INIT_CORE;
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#endif
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err = bus_space_map(iot, OMAP2_CM_BASE + off, 0x100, 0, &ioh);
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KASSERT(err == 0);
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val = bus_space_read_4(iot, ioh, OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL);
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val |= OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC60M_P3_CLK
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| OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC60M_P2_CLK
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| OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC480M_P3_CLK
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| OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC480M_P2_CLK
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| OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_UTMI_P3_CLK
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| OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_UTMI_P2_CLK;
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bus_space_write_4(iot, ioh, OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL, val);
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val = bus_space_read_4(iot, ioh, OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL);
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val |= OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL_USB_CH2_CLK
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| OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL_USB_CH1_CLK;
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bus_space_write_4(iot, ioh, OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL, val);
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bus_space_unmap(iot, ioh, 0x100);
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}
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#endif /* OMAP4 || OMAP5 */
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static void
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usbtll_reset(struct omap3_ehci_softc *sc)
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{
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@ -648,28 +747,48 @@ usbtll_init(struct omap3_ehci_softc *sc, int chmask)
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static void
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uhh_power(struct omap3_ehci_softc *sc, bool on)
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{
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uint32_t v;
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int retry = 5000;
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uint32_t v;
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v = UHH_READ4(sc, UHH_REVISION);
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const int vers = UHH_REVISION_MAJOR(v);
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if (on) {
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v = UHH_READ4(sc, UHH_SYSCONFIG);
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v &= ~(UHH_SYSCONFIG_SIDLEMODE_MASK|UHH_SYSCONFIG_MIDLEMODE_MASK);
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v |= UHH_SYSCONFIG_MIDLEMODE_SMARTSTANDBY;
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v |= UHH_SYSCONFIG_CLOCKACTIVITY;
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v |= UHH_SYSCONFIG_SIDLEMODE_SMARTIDLE;
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v |= UHH_SYSCONFIG_ENAWAKEUP;
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v &= ~UHH_SYSCONFIG_AUTOIDLE;
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if (vers >= UHH_REVISION_VERS2) {
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v &= ~UHH4_SYSCONFIG_STANDBYMODE;
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v |= UHH4_SYSCONFIG_STANDBYMODE_SMARTSTANDBY;
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v &= ~UHH4_SYSCONFIG_SIDLEMODE;
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v |= UHH4_SYSCONFIG_SIDLEMODE_SMARTIDLE;
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} else {
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v &= ~UHH3_SYSCONFIG_MIDLEMODE_MASK;
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v |= UHH3_SYSCONFIG_MIDLEMODE_SMARTSTANDBY;
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v &= ~UHH3_SYSCONFIG_SIDLEMODE_MASK;
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v |= UHH3_SYSCONFIG_SIDLEMODE_SMARTIDLE;
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v |= UHH3_SYSCONFIG_CLOCKACTIVITY;
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v |= UHH3_SYSCONFIG_ENAWAKEUP;
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v &= ~UHH3_SYSCONFIG_AUTOIDLE;
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}
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UHH_WRITE4(sc, UHH_SYSCONFIG, v);
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v = UHH_READ4(sc, UHH_SYSCONFIG);
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} else {
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v = UHH_READ4(sc, UHH_SYSCONFIG);
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v |= UHH_SYSCONFIG_SOFTRESET;
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if (vers >= UHH_REVISION_VERS2) {
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v |= UHH4_SYSCONFIG_SOFTRESET;
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} else {
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v |= UHH3_SYSCONFIG_SOFTRESET;
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}
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UHH_WRITE4(sc, UHH_SYSCONFIG, v);
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do {
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v = UHH_READ4(sc, UHH_SYSSTATUS);
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if (v & UHH_SYSSTATUS_RESETDONE_ALL)
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break;
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if (vers >= UHH_REVISION_VERS2) {
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if ((v & UHH4_SYSSTATUS_RESETDONE_ALL) == 0)
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break;
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} else {
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if (v & UHH3_SYSSTATUS_RESETDONE_ALL)
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break;
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}
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delay(10);
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} while (retry-- > 0);
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if (retry == 0)
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|
|
@ -699,18 +818,18 @@ uhh_portconfig(struct omap3_ehci_softc *sc)
|
|||
&& sc->sc_portconfig[2].mode == OMAP3_EHCI_PORT_MODE_NONE)
|
||||
v &= ~UHH_HOSTCONFIG_P3_CONNECT_STATUS;
|
||||
|
||||
v &= ~(UHH_HOSTCONFIG_P1_ULPI_BYPASS |UHH_HOSTCONFIG_P2_ULPI_BYPASS
|
||||
|UHH_HOSTCONFIG_P2_ULPI_BYPASS);
|
||||
if (sc->sc_portconfig[0].mode != OMAP3_EHCI_PORT_MODE_PHY)
|
||||
v |= UHH_HOSTCONFIG_P1_ULPI_BYPASS;
|
||||
v &= ~(UHH_HOSTCONFIG_P1_ULPI_BYPASS|UHH_HOSTCONFIG_P2_ULPI_BYPASS
|
||||
|UHH_HOSTCONFIG_P3_ULPI_BYPASS);
|
||||
v &= ~(UHH_HOSTCONFIG_P1_MODE|UHH_HOSTCONFIG_P2_MODE
|
||||
|UHH_HOSTCONFIG_P3_MODE);
|
||||
|
||||
if (sc->sc_nports > 1
|
||||
&& sc->sc_portconfig[1].mode != OMAP3_EHCI_PORT_MODE_PHY)
|
||||
v |= UHH_HOSTCONFIG_P2_ULPI_BYPASS;
|
||||
|
||||
if (sc->sc_nports > 2
|
||||
&& sc->sc_portconfig[2].mode == OMAP3_EHCI_PORT_MODE_PHY)
|
||||
v |= UHH_HOSTCONFIG_P3_ULPI_BYPASS;
|
||||
v |= uhh_map[0][sc->sc_portconfig[0].mode];
|
||||
if (sc->sc_nports > 1) {
|
||||
v |= uhh_map[1][sc->sc_portconfig[1].mode];
|
||||
if (sc->sc_nports > 2) {
|
||||
v |= uhh_map[2][sc->sc_portconfig[2].mode];
|
||||
}
|
||||
}
|
||||
|
||||
UHH_WRITE4(sc, UHH_HOSTCONFIG, v);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: omap3_sdhc.c,v 1.13 2013/08/05 21:55:47 jmcneill Exp $ */
|
||||
/* $NetBSD: omap3_sdhc.c,v 1.14 2014/03/29 23:32:41 matt Exp $ */
|
||||
/*-
|
||||
* Copyright (c) 2011 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
|
|
@ -29,7 +29,7 @@
|
|||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: omap3_sdhc.c,v 1.13 2013/08/05 21:55:47 jmcneill Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: omap3_sdhc.c,v 1.14 2014/03/29 23:32:41 matt Exp $");
|
||||
|
||||
#include "opt_omap.h"
|
||||
|
||||
|
|
@ -119,7 +119,7 @@ obiosdhc_match(device_t parent, cfdata_t cf, void *aux)
|
|||
|| oa->obio_addr == SDMMC2_BASE_3530
|
||||
|| oa->obio_addr == SDMMC3_BASE_3530)
|
||||
return 1;
|
||||
#elif defined(OMAP4)
|
||||
#elif defined(OMAP4) || defined(OMAP5)
|
||||
if (oa->obio_addr == SDMMC1_BASE_4430
|
||||
|| oa->obio_addr == SDMMC2_BASE_4430
|
||||
|| oa->obio_addr == SDMMC3_BASE_4430
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: omap3_uhhreg.h,v 1.2 2013/06/18 15:01:49 matt Exp $ */
|
||||
/* $NetBSD: omap3_uhhreg.h,v 1.3 2014/03/29 23:32:41 matt Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2010 Jared D. McNeill <jmcneill@invisible.ca>
|
||||
|
|
@ -29,33 +29,51 @@
|
|||
#define _OMAP3_UHHREG_H
|
||||
|
||||
/* 32-bit */
|
||||
#define UHH_REVISION 0x00
|
||||
#define UHH_REVISION_MAJOR(x) (((x) >> 4) & 0xf)
|
||||
#define UHH_REVISION_MINOR(x) ((x) & 0xf)
|
||||
#define UHH_REVISION 0x00
|
||||
#define UHH_REVISION_MAJOR(x) (((x) >> 4) & 0xf)
|
||||
#define UHH_REVISION_MINOR(x) ((x) & 0xf)
|
||||
#define UHH_REVISION_VERS2 2
|
||||
|
||||
#define UHH_SYSCONFIG 0x10
|
||||
#define UHH_SYSCONFIG_MIDLEMODE_MASK 0x00003000
|
||||
#define UHH_SYSCONFIG_MIDLEMODE_SMARTSTANDBY 0x00002000
|
||||
#define UHH_SYSCONFIG_CLOCKACTIVITY 0x00000100
|
||||
#define UHH_SYSCONFIG_SIDLEMODE_MASK 0x00000018
|
||||
#define UHH_SYSCONFIG_SIDLEMODE_SMARTIDLE 0x00000008
|
||||
#define UHH_SYSCONFIG_ENAWAKEUP 0x00000004
|
||||
#define UHH_SYSCONFIG_SOFTRESET 0x00000002
|
||||
#define UHH_SYSCONFIG_AUTOIDLE 0x00000001
|
||||
#define UHH_HWINFO 0x04
|
||||
#define UHH_HWINFO_SAR_CNTX_SIZE __BITS(9,0)
|
||||
|
||||
#define UHH_SYSSTATUS 0x14
|
||||
#define UHH_SYSSTATUS_EHCI_RESETDONE 0x00000004
|
||||
#define UHH_SYSSTATUS_OHCI_RESETDONE 0x00000002
|
||||
#define UHH_SYSSTATUS_RESETDONE 0x00000001
|
||||
#define UHH_SYSSTATUS_RESETDONE_ALL \
|
||||
#define UHH_SYSCONFIG 0x10
|
||||
#define UHH3_SYSCONFIG_MIDLEMODE_MASK 0x00003000
|
||||
#define UHH3_SYSCONFIG_MIDLEMODE_SMARTSTANDBY 0x00002000
|
||||
#define UHH3_SYSCONFIG_CLOCKACTIVITY 0x00000100
|
||||
#define UHH3_SYSCONFIG_SIDLEMODE_MASK 0x00000018
|
||||
#define UHH3_SYSCONFIG_SIDLEMODE_SMARTIDLE 0x00000008
|
||||
#define UHH3_SYSCONFIG_ENAWAKEUP 0x00000004
|
||||
#define UHH3_SYSCONFIG_SOFTRESET 0x00000002
|
||||
#define UHH3_SYSCONFIG_AUTOIDLE 0x00000001
|
||||
|
||||
#define UHH4_SYSCONFIG_STANDBYMODE __BITS(5,4)
|
||||
#define UHH4_SYSCONFIG_STANDBYMODE_SMARTSTANDBY __SHIFTIN(2,UHH4_SYSCONFIG_STANDBYMODE)
|
||||
#define UHH4_SYSCONFIG_SIDLEMODE __BITS(3,2)
|
||||
#define UHH4_SYSCONFIG_SIDLEMODE_SMARTIDLE __SHIFTIN(2,UHH4_SYSCONFIG_SIDLEMODE)
|
||||
#define UHH4_SYSCONFIG_SOFTRESET __BIT(0)
|
||||
|
||||
#define UHH_SYSSTATUS 0x14
|
||||
#define UHH_SYSSTATUS_EHCI_RESETDONE 0x00000004
|
||||
#define UHH_SYSSTATUS_OHCI_RESETDONE 0x00000002
|
||||
#define UHH3_SYSSTATUS_RESETDONE 0x00000001
|
||||
#define UHH3_SYSSTATUS_RESETDONE_ALL \
|
||||
(UHH_SYSSTATUS_EHCI_RESETDONE | \
|
||||
UHH_SYSSTATUS_OHCI_RESETDONE | \
|
||||
UHH_SYSSTATUS_RESETDONE)
|
||||
UHH3_SYSSTATUS_RESETDONE)
|
||||
#define UHH4_SYSSTATUS_RESETDONE_ALL \
|
||||
(UHH_SYSSTATUS_EHCI_RESETDONE | \
|
||||
UHH_SYSSTATUS_OHCI_RESETDONE)
|
||||
|
||||
#define UHH_HOSTCONFIG 0x40
|
||||
#define UHH_HOSTCONFIG 0x40
|
||||
#define UHH_HOSTCONFIG_APP_START_CLK __BIT(31)
|
||||
#define UHH_HOSTCONFIG_P3_MODE __BITS(21,20)
|
||||
#define UHH_HOSTCONFIG_P2_MODE __BITS(19,18)
|
||||
#define UHH_HOSTCONFIG_P1_MODE __BITS(17,16)
|
||||
#define UHH_HOSTCONFIG_PMODE_ULPI_PHY 0
|
||||
#define UHH_HOSTCONFIG_PMODE_UTMI 1
|
||||
#define UHH_HOSTCONFIG_PMODE__RSVD2 2
|
||||
#define UHH_HOSTCONFIG_PMODE_HSIC 3
|
||||
#define UHH_HOSTCONFIG_P3_ULPI_BYPASS __BIT(12)
|
||||
#define UHH_HOSTCONFIG_P2_ULPI_BYPASS __BIT(11)
|
||||
#define UHH_HOSTCONFIG_P3_CONNECT_STATUS __BIT(10)
|
||||
|
|
@ -77,4 +95,6 @@
|
|||
#define UHH_DEBUG_CSR_EHCI_SIMULATION_MODE 0x00000040
|
||||
#define UHH_DEBUG_CSR_EHCI_FLADJ 0x0000003f
|
||||
|
||||
#define UHH_SAR_CNTX_BASE 0x100
|
||||
|
||||
#endif /* !_OMAP3_UHHREG_H */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: omap3_usbtllreg.h,v 1.1 2012/12/12 00:33:45 matt Exp $ */
|
||||
/* $NetBSD: omap3_usbtllreg.h,v 1.2 2014/03/29 23:32:41 matt Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2010 Jared D. McNeill <jmcneill@invisible.ca>
|
||||
|
|
@ -33,6 +33,9 @@
|
|||
#define USBTLL_REVISION_MAJOR(x) (((x) >> 4) & 0xf)
|
||||
#define USBTLL_REVISION_MINOR(x) ((x) & 0xf)
|
||||
|
||||
#define USBTLL_HWINFO 0x04
|
||||
#define USBTLL_HWINFO_SAR_CNTX_SIZE __BITS(7,0)
|
||||
|
||||
#define USBTLL_SYSCONFIG 0x10
|
||||
#define USBTLL_SYSCONFIG_CLOCKACTIVITY 0x00000100
|
||||
#define USBTLL_SYSCONFIG_SIDLEMODE 0x00000018
|
||||
|
|
@ -81,6 +84,8 @@
|
|||
#define USBTLL_CHANNEL_CONF_CHANMODE 0x00000006
|
||||
#define USBTLL_CHANNEL_CONF_CHANEN 0x00000001
|
||||
|
||||
#define USBTLL_SAR_CNTX(i) (0x400 + (0x04 * (i)))
|
||||
|
||||
/* 8-bit */
|
||||
#define ULPI_VENDOR_ID_LO(i) (0x100 * (i) + 0)
|
||||
#define ULPI_VENDOR_ID_HI(i) (0x100 * (i) + 1)
|
||||
|
|
|
|||
Loading…
Reference in New Issue