New version (from Theo (from 4.4)) - supports multicast.
This commit is contained in:
gwr
parent
0819c2c23a
commit
a4aa1b4b57
File diff suppressed because it is too large
Load Diff
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@ -1,19 +1,34 @@
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/*
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* Ethernet software status per interface.
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*
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*/
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/* Per interface statistics */
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struct lestats {
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long lexints; /* transmitter interrupts */
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long lerints; /* receiver interrupts */
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long lerbufs; /* total buffers received during interrupts */
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long lerhits; /* times current rbuf was full */
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long lerscans; /* rbufs scanned before finding first full */
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};
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/*
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* Each interface is referenced by a network interface structure,
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* le_if, which the routing code uses to locate the interface.
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* This structure contains the output queue for the interface, its address, ...
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* This structure contains the output queue for the interface,
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* its address, ...
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*/
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struct le_softc {
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struct device sc_dev;
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struct arpcom sc_ac; /* common Ethernet structures */
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#define sc_if sc_ac.ac_if /* network-visible interface */
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#define sc_addr sc_ac.ac_enaddr /* hardware Ethernet address */
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char *sc_machdep; /* machine dependent pointer */
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struct lereg1 *sc_r1; /* LANCE registers */
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struct lereg2 *sc_r2; /* dual-port RAM */
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int sc_rmd; /* predicted next rmd to process */
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struct device sc_dev; /* base device */
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void *sc_machdep; /* machine dependent pointer */
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struct evcnt sc_intrcnt; /* # of interrupts, per le */
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struct evcnt sc_errcnt; /* # of errors, per le */
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struct arpcom sc_ac; /* common Ethernet structures */
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#define sc_if sc_ac.ac_if /* network-visible interface */
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#define sc_addr sc_ac.ac_enaddr /* hardware Ethernet address */
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volatile struct lereg1 *sc_r1; /* LANCE registers */
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volatile struct lereg2 *sc_r2; /* dual-port RAM */
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int sc_rmd; /* predicted next rmd to process */
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int sc_runt;
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int sc_jab;
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int sc_merr;
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@ -28,7 +43,5 @@ struct le_softc {
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int sc_txoff;
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int sc_busy;
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short sc_iflags;
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#if NBPFILTER > 0
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caddr_t sc_bpf;
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#endif
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struct lestats sc_lestats; /* per interface statistics */
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};
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@ -28,7 +28,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Header: /cvsroot/src/sys/arch/sun3/dev/Attic/if_le_subr.c,v 1.4 1994/03/16 04:35:36 glass Exp $
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* $Header: /cvsroot/src/sys/arch/sun3/dev/Attic/if_le_subr.c,v 1.5 1994/05/28 15:45:53 gwr Exp $
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* gwr: uncomment obio_probe_byte
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*/
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@ -50,7 +50,6 @@
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#include <machine/autoconf.h>
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#include <machine/cpu.h>
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#include <machine/isr.h>
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#include <machine/mtpr.h>
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#include <machine/obio.h>
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#include <machine/idprom.h>
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@ -59,6 +58,19 @@
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#include "if_lereg.h"
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#include "if_le.h"
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int
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le_md_match(parent, cf, args)
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struct device *parent;
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struct cfdata *cf;
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void *args;
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{
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caddr_t le_addr;
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struct obio_cf_loc *obio_loc = (struct obio_cf_loc *) CFDATA_LOC(cf);
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le_addr = OBIO_DEFAULT_PARAM(caddr_t, obio_loc->obio_addr, OBIO_AMD_ETHER);
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return !obio_probe_byte(le_addr);
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}
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/*
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* things to do:
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* allocate dvma area memory for dual access
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@ -69,48 +81,31 @@
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*
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*/
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int le_machdep_attach(parent, self, args)
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struct device *parent;
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struct device *self;
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void *args;
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void
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le_md_attach(parent, self, args)
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struct device *parent;
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struct device *self;
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void *args;
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{
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caddr_t dvma_malloc(), le_addr;
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int level, leintr(), unit = DEVICE_UNIT(self);
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struct le_softc *le = (struct le_softc *) self;
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struct obio_cf_loc *obio_loc = OBIO_LOC(self);
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/* allocate "shared" memory */
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le->sc_r2 =
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(struct lereg2 *) dvma_malloc(sizeof(struct lereg2));
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if (!le->sc_r2) {
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printf(": not enough dvma space\n");
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return 1;
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}
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idprom_etheraddr(le->sc_addr); /* ethernet addr */
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le_addr = OBIO_DEFAULT_PARAM(caddr_t, obio_loc->obio_addr, OBIO_AMD_ETHER);
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caddr_t dvma_malloc(), le_addr;
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int level, leintr();
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struct le_softc *le = (struct le_softc *) self;
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struct obio_cf_loc *obio_loc = OBIO_LOC(self);
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/* allocate "shared" memory */
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le->sc_r2 = (struct lereg2 *) dvma_malloc(sizeof(struct lereg2));
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if (!le->sc_r2)
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panic(": not enough dvma space");
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idprom_etheraddr(le->sc_addr); /* ethernet addr */
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le_addr = OBIO_DEFAULT_PARAM(caddr_t, obio_loc->obio_addr, OBIO_AMD_ETHER);
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/* register access */
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le->sc_r1 = (struct lereg1 *)
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obio_alloc(le_addr, OBIO_AMD_ETHER_SIZE, OBIO_WRITE);
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if (!le->sc_r1) {
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printf(": not enough obio space\n");
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return 1;
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}
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level = OBIO_DEFAULT_PARAM(int, obio_loc->obio_level, 3);
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obio_print(le_addr, level);
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le->sc_machdep = NULL;
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isr_add(level, leintr, unit);
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return 0;
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}
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int le_machdep_match(parent, cf, args)
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struct device *parent;
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struct cfdata *cf;
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void *args;
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{
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caddr_t le_addr;
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struct obio_cf_loc *obio_loc = (struct obio_cf_loc *) CFDATA_LOC(cf);
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le_addr = OBIO_DEFAULT_PARAM(caddr_t, obio_loc->obio_addr, OBIO_AMD_ETHER);
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return !obio_probe_byte(le_addr);
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/* register access */
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le->sc_r1 = (struct lereg1 *)
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obio_alloc(le_addr, OBIO_AMD_ETHER_SIZE, OBIO_WRITE);
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if (!le->sc_r1)
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panic(": not enough obio space\n");
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level = OBIO_DEFAULT_PARAM(int, obio_loc->obio_level, 3);
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obio_print(le_addr, level);
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le->sc_machdep = NULL;
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isr_add(level, leintr, (int)le);
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}
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@ -1,7 +1,4 @@
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/* access LANCE registers */
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#define LERDWR(cntl, src, dst) (dst) = (src)
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/* One might also set: LE_C3_ACON | LE_C3_BCON */
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#define LE_C3_CONFIG LE_C3_BSWP
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#define LANCE_ADDR(lance) ((unsigned int) lance & 0x00FFFFFF)
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#define le_machdep_intrcheck(le, unit)
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 1982, 1990 The Regents of the University of California.
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* All rights reserved.
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/*-
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* Copyright (c) 1982, 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -30,12 +30,11 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)if_lereg.h 7.1 (Berkeley) 5/8/90
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* if_lereg.h,v 1.2 1993/05/22 07:56:25 cgd Exp
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* from: Header: if_lereg.h,v 1.7 93/10/31 04:41:00 leres Locked
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* from: @(#)if_lereg.h 8.2 (Berkeley) 10/30/93
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* $Id: if_lereg.h,v 1.4 1994/05/28 15:45:55 gwr Exp $
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*/
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#define LEID 21
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#define LEMTU 1518
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#define LEMINSIZE 60 /* should be 64 if mode DTCR is set */
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#define LERBUF 8
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#define LETBUF 1
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#define LETBUFLOG2 0
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#define LE_TLEN (LETBUFLOG2 << 13)
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#define LE_ADDR_LOW_MASK 0xFFFF
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#define vu_char volatile u_char
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/*
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* LANCE registers.
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*/
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/* Local Area Network Controller for Ethernet (LANCE) registers */
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struct lereg1 {
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u_short ler1_rdp; /* data port */
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u_short ler1_rap; /* register select port */
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u_short ler1_rdp; /* register data port */
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u_short ler1_rap; /* register address port */
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};
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/* register addresses */
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#define LE_CSR0 0 /* Control and status register */
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#define LE_CSR1 1 /* low address of init block */
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#define LE_CSR2 2 /* high address of init block */
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#define LE_CSR3 3 /* Bus master and control */
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/* Control and status register 0 (csr0) */
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#define LE_C0_ERR 0x8000 /* error summary */
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#define LE_C0_BABL 0x4000 /* transmitter timeout error */
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#define LE_C0_CERR 0x2000 /* collision */
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#define LE_C0_MISS 0x1000 /* missed a packet */
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#define LE_C0_MERR 0x0800 /* memory error */
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#define LE_C0_RINT 0x0400 /* receiver interrupt */
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#define LE_C0_TINT 0x0200 /* transmitter interrupt */
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#define LE_C0_IDON 0x0100 /* initalization done */
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#define LE_C0_INTR 0x0080 /* interrupt condition */
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#define LE_C0_INEA 0x0040 /* interrupt enable */
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#define LE_C0_RXON 0x0020 /* receiver on */
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#define LE_C0_TXON 0x0010 /* transmitter on */
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#define LE_C0_TDMD 0x0008 /* transmit demand */
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#define LE_C0_STOP 0x0004 /* disable all external activity */
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#define LE_C0_STRT 0x0002 /* enable external activity */
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#define LE_C0_INIT 0x0001 /* begin initalization */
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#define LE_C0_BITS \
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"\20\20ERR\17BABL\16CERR\15MISS\14MERR\13RINT\
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\12TINT\11IDON\10INTR\07INEA\06RXON\05TXON\04TDMD\03STOP\02STRT\01INIT"
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/* Control and status register 3 (csr3) */
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#define LE_C3_BSWP 0x4 /* byte swap */
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#define LE_C3_ACON 0x2 /* ALE control, eh? */
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#define LE_C3_BCON 0x1 /* byte control */
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/*
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* Overlayed on 16K dual-port RAM.
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* Current size is 13,758 bytes with 8 x 1518 receive buffers and
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* 1 x 1518 transmit buffer.
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*/
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struct lereg2 {
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/* init block */
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u_short ler2_mode; /* +0x0000 */
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u_char ler2_padr[6]; /* +0x0002 */
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u_long ler2_ladrf0; /* +0x0008 */
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u_long ler2_ladrf1; /* +0x000C */
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u_short ler2_rdra; /* +0x0010 */
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u_short ler2_rlen; /* +0x0012 */
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u_short ler2_tdra; /* +0x0014 */
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u_short ler2_tlen; /* +0x0016 */
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/* receive message descriptors */
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struct lermd { /* +0x0018 */
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u_short rmd0;
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u_char rmd1_bits;
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u_char rmd1_hadr;
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short rmd2;
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u_short rmd3;
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/* initialization block */
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u_short ler2_mode; /* mode */
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u_char ler2_padr[6]; /* physical address */
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u_short ler2_ladrf[4]; /* logical address filter */
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u_short ler2_rdra; /* receive descriptor addr */
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u_short ler2_rlen; /* rda high and ring size */
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u_short ler2_tdra; /* transmit descriptor addr */
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u_short ler2_tlen; /* tda high and ring size */
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/* receive message descriptors. bits/hadr are byte order dependent. */
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struct lermd {
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u_short rmd0; /* low address of packet */
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u_char rmd1_bits; /* descriptor bits */
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u_char rmd1_hadr; /* high address of packet */
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short rmd2; /* buffer byte count */
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u_short rmd3; /* message byte count */
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} ler2_rmd[LERBUF];
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/* transmit message descriptors */
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struct letmd { /* +0x0058 */
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u_short tmd0;
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u_char tmd1_bits;
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u_char tmd1_hadr;
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short tmd2;
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u_short tmd3;
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struct letmd {
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u_short tmd0; /* low address of packet */
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u_char tmd1_bits; /* descriptor bits */
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u_char tmd1_hadr; /* high address of packet */
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short tmd2; /* buffer byte count */
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u_short tmd3; /* transmit error bits */
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} ler2_tmd[LETBUF];
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char ler2_rbuf[LERBUF][LEMTU]; /* +0x0060 */
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char ler2_tbuf[LETBUF][LEMTU]; /* +0x2FD0 */
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char ler2_rbuf[LERBUF][LEMTU];
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char ler2_tbuf[LETBUF][LEMTU];
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};
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/*
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* Control and status bits -- lereg0
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*/
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#define LE_IE 0x80 /* interrupt enable */
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#define LE_IR 0x40 /* interrupt requested */
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#define LE_LOCK 0x08 /* lock status register */
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#define LE_ACK 0x04 /* ack of lock */
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#define LE_JAB 0x02 /* loss of tx clock (???) */
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#define LE_IPL(x) ((((x) >> 4) & 0x3) + 3)
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/*
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* Control and status bits -- lereg1
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*/
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#define LE_CSR0 0
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#define LE_CSR1 1
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#define LE_CSR2 2
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#define LE_CSR3 3
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#define LE_SERR 0x8000
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#define LE_BABL 0x4000
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#define LE_CERR 0x2000
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#define LE_MISS 0x1000
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#define LE_MERR 0x0800
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#define LE_RINT 0x0400
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#define LE_TINT 0x0200
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#define LE_IDON 0x0100
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#define LE_INTR 0x0080
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#define LE_INEA 0x0040
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#define LE_RXON 0x0020
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#define LE_TXON 0x0010
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#define LE_TDMD 0x0008
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#define LE_STOP 0x0004
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#define LE_STRT 0x0002
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#define LE_INIT 0x0001
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#define LE_STATUS_BITS "\20\20ERR\17BABL\16CERR\15MISS\14MERR\13RINT\12TINT\11IDON\10INTR\07INEA\06RXON\05TXON\04TDMD\03STOP\02STRT\01INIT"
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/* Initialzation block (mode) */
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#define LE_MODE_PROM 0x8000 /* promiscuous mode */
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/* 0x7f80 reserved, must be zero */
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#define LE_MODE_INTL 0x0040 /* internal loopback */
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#define LE_MODE_DRTY 0x0020 /* disable retry */
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#define LE_MODE_COLL 0x0010 /* force a collision */
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#define LE_MODE_DTCR 0x0008 /* disable transmit CRC */
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#define LE_MODE_LOOP 0x0004 /* loopback mode */
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#define LE_MODE_DTX 0x0002 /* disable transmitter */
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#define LE_MODE_DRX 0x0001 /* disable receiver */
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#define LE_MODE_NORMAL 0 /* none of the above */
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#define LE_BSWP 0x4
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#define LE_MODE 0x0
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/* Receive message descriptor 1 (rmd1_bits) */
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#define LE_R1_OWN 0x80 /* LANCE owns the packet */
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#define LE_R1_ERR 0x40 /* error summary */
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#define LE_R1_FRAM 0x20 /* framing error */
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#define LE_R1_OFLO 0x10 /* overflow error */
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#define LE_R1_CRC 0x08 /* CRC error */
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#define LE_R1_BUFF 0x04 /* buffer error */
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#define LE_R1_STP 0x02 /* start of packet */
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#define LE_R1_ENP 0x01 /* end of packet */
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/*
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* Control and status bits -- lereg2
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*/
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#define LE_OWN 0x80
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#define LE_ERR 0x40
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#define LE_STP 0x02
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#define LE_ENP 0x01
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#define LE_R1_BITS \
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"\20\10OWN\7ERR\6FRAM\5OFLO\4CRC\3BUFF\2STP\1ENP"
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#define LE_FRAM 0x20
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#define LE_OFLO 0x10
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#define LE_CRC 0x08
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#define LE_RBUFF 0x04
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#define LE_MORE 0x10
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#define LE_ONE 0x08
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#define LE_DEF 0x04
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#define LE_TBUFF 0x8000
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#define LE_UFLO 0x4000
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#define LE_LCOL 0x1000
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#define LE_LCAR 0x0800
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#define LE_RTRY 0x0400
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/* Transmit message descriptor 1 (tmd1_bits) */
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#define LE_T1_OWN 0x80 /* LANCE owns the packet */
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#define LE_T1_ERR 0x40 /* error summary */
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#define LE_T1_MORE 0x10 /* multiple collisions */
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#define LE_T1_ONE 0x08 /* single collision */
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#define LE_T1_DEF 0x04 /* defferred transmit */
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#define LE_T1_STP 0x02 /* start of packet */
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#define LE_T1_ENP 0x01 /* end of packet */
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#define LE_T1_BITS \
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"\20\10OWN\7ERR\6RES\5MORE\4ONE\3DEF\2STP\1ENP"
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/* Transmit message descriptor 3 (tmd3) */
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#define LE_T3_BUFF 0x8000 /* buffer error */
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#define LE_T3_UFLO 0x4000 /* underflow error */
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#define LE_T3_LCOL 0x1000 /* late collision */
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||||
#define LE_T3_LCAR 0x0800 /* loss of carrier */
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||||
#define LE_T3_RTRY 0x0400 /* retry error */
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#define LE_T3_TDR_MASK 0x03ff /* time domain reflectometry counter */
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||||
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||||
#define LE_T3_BITS \
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"\20\20BUFF\17UFLO\16RES\15LCOL\14LCAR\13RTRY"
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||||
|
|
|
|||
Loading…
Reference in New Issue