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add support i.MX6 and NITROGEN6X evaluation board

This commit is contained in:
ryo 2014-09-25 05:05:28 +00:00
parent 19e7c9be20
commit a4103ccd60
41 changed files with 8160 additions and 148 deletions
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123
sys/arch/arm/imx/files.imx6
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# $NetBSD: files.imx6,v 1.1 2012/09/01 00:07:32 matt Exp $
# $NetBSD: files.imx6,v 1.2 2014/09/25 05:05:28 ryo Exp $
#
# Configuration info for the Freescale i.MX6
#
include "arch/arm/pic/files.pic"
include "arch/arm/cortex/files.cortex"
defparam opt_imx.h MEMSIZE
defflag opt_imx.h IMX6
file arch/arm/arm32/arm32_boot.c
file arch/arm/arm32/arm32_kvminit.c
file arch/arm/arm32/arm32_reboot.c
file arch/arm/arm32/irq_dispatch.S
define bus_dma_generic
file arch/arm/imx/imx_space.c
file arch/arm/imx/imx_dma.c bus_dma_generic needs-flag
file arch/arm/imx/imx_dma.c bus_dma_generic needs-flag
file arch/arm/imx/imx6_board.c
# iMX6 AXI/AHB bus interface and SoC domains
device axi { [addr=-1], [size=0], [irq=-1], [irqbase=-1]} : bus_space_generic
attach axi at mainbus
file arch/arm/imx/imx6_axi.c axi
file arch/arm/imx/imx6_axi.c axi
# iMX6 Clock Control Module
device imxccm
attach imxccm at axi
file arch/arm/imx/imx6_ccm.c imxccm needs-flag
defflag opt_imx6clk.h IMXCCMDEBUG
# iMX6 Enhanced Periodic Interrupt Timer
device imxclock
attach imxclock at axi
file arch/arm/imx/imxclock.c
file arch/arm/imx/imx6_clock.c
file arch/arm/imx/imxclock.c imxclock
file arch/arm/imx/imx6_clock.c imxclock
# Clock Control Module
device imxccm
attach imxccm at axi
file arch/arm/imx/imx6_ccm.c imxccm needs-flag
# iMX6 On-Chip OTP Controller
device imxocotp
attach imxocotp at axi
file arch/arm/imx/imx6_ocotp.c imxocotp needs-flag
# frequency of external low frequency clock
# typically 32000, 32768, or 38400.
defparam opt_imx6clk.h IMX6_CKIL_FREQ
# frequency of on-chip oscillator. typically 24000000.
defparam opt_imx6clk.h IMX6_OSC_FREQ
# following parameters are used when imxccm is not configured in the kernel.
defparam opt_imx6clk.h IMX6_AHBCLK_FREQ
defparam opt_imx6clk.h IMX6_IPGCLK_FREQ
# Watchdog
device imxwdog: sysmon_wdog
attach imxwdog at axi
file arch/arm/imx/imx6_wdog.c imxwdog
file arch/arm/imx/imxwdog.c imxwdog
# iMX GPIO
#device imxgpio: gpiobus
device imxgpio: gpiobus
attach imxgpio at axi
#file arch/arm/imx/imxgpio.c imxgpio needs-flag
#file arch/arm/imx/imx6_gpio.c imxgpio
file arch/arm/imx/imxgpio.c imxgpio needs-flag
file arch/arm/imx/imx6_gpio.c imxgpio
defflag opt_imxgpio.h IMX_GPIO_INTR_SPLIT
# iMX IOMUX
#device imxiomux : bus_space_generic
#attach imxiomux at axi
#file arch/arm/imx/imx6_iomux.c imxiomux
# IPU v3 controller
#device ipu : bus_dma_generic, wsemuldisplaydev, rasops16, rasops8, rasops4, rasops_rotation, vcons
#file arch/arm/imx/imx6_ipuv3.c ipu needs-flag
#defflag opt_imx6_ipuv3.h IMXIPUCONSOLE
#defparam opt_imx6_ipuv3.h IPUV3_DEBUG
# iMX M3IF - Multi Master Memory Interface
# iMX ESDCTL/MDDRC - Enhanced SDRAM/LPDDR memory controller
# iMX PCMCIA - PCMCIA memory controller
# iMX NANDFC - NAND Flash memory controller
# iMX WEIM - Wireless External Interface Module
# iMX6 IOMUX
device imxiomux
attach imxiomux at axi
file arch/arm/imx/imx6_iomux.c imxiomux
# iMX UART
device imxuart
attach imxuart at axi
file arch/arm/imx/imxuart.c imxuart needs-flag
file arch/arm/imx/imx6_uart.c imxuart
defflag opt_imxuart.h IMXUARTCONSOLE
defflag opt_imxuart.h IMXUARTCONSOLE
# USB controller
# iMX6 10/100/1000-Mbps Ethernet MAC(ENET)
device enet: ether, ifnet, arp, mii, bus_dma_generic
attach enet at axi
file arch/arm/imx/if_enet.c enet
# USB Controller
# attach of this driver need to be specified in paltform configuration
device imxusbc { unit, irq } : bus_dma_generic
file arch/arm/imx/imx6_usb.c imxusbc
device imxusbc { unit, irq } : bus_dma_generic
file arch/arm/imx/imx6_usb.c imxusbc
attach ehci at imxusbc with imxehci
file arch/arm/imx/imxusb.c imxehci
attach ehci at imxusbc with imxehci
file arch/arm/imx/imxusb.c imxehci
# attach wdc at ahb with wdc_ahb : bus_dma_generic
# file arch/arm/imx/wdc_axi.c wdc_axi
# SD host controller for SD/MMC
# uSDHC
attach sdhc at axi with sdhc_axi
file arch/arm/imx/imx6_esdhc.c sdhc_axi
file arch/arm/imx/imx6_usdhc.c sdhc_axi
# iic Controler
# device imxi2c: i2cbus
# file arch/arm/imx/imx6_i2c.c imxi2c
# attach imxi2c at aips with imxi2c_aips
# file arch/arm/imx/imxi2c_aips.c imxi2c_aips
# spi bus controlloer
# device imxspi: spibus
# file arch/arm/imx/imx6_spi.c imxspi
# Smart Direct Memory Access Controller
# device imxsdma: dmover_service, bus_dma_generic
# attach imxsdma at ahb
# file arch/arm/imx/imxsdma.c imxsdma
# file arch/arm/imx/imxsdmaprog.c imxsdma
# iis sound Controller (SSI module)
# device imxi2s {} : bus_dma_generic
# file arch/arm/imx/imx6_i2s.c imxi2s needs-flag
# iMX6 SATA Controllers (AHCI)
attach ahcisata at axi with imx6_ahcisata
file arch/arm/imx/imx6_ahcisata.c imx6_ahcisata

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sys/arch/arm/imx/if_enet.c Normal file
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sys/arch/arm/imx/if_enetreg.h Normal file
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/* $NetBSD: if_enetreg.h,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*-
* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* i.MX6 10/100/1000-Mbps ethernet MAC (ENET)
*/
#ifndef _ARM_IMX_IF_ENETREG_H_
#define _ARM_IMX_IF_ENETREG_H_
#include <sys/cdefs.h>
#define ENET_EIR 0x00000004
# define ENET_EIR_BABR __BIT(30)
# define ENET_EIR_BABT __BIT(29)
# define ENET_EIR_GRA __BIT(28)
# define ENET_EIR_TXF __BIT(27)
# define ENET_EIR_TXB __BIT(26)
# define ENET_EIR_RXF __BIT(25)
# define ENET_EIR_RXB __BIT(24)
# define ENET_EIR_MII __BIT(23)
# define ENET_EIR_EBERR __BIT(22)
# define ENET_EIR_LC __BIT(21)
# define ENET_EIR_RL __BIT(20)
# define ENET_EIR_UN __BIT(19)
# define ENET_EIR_PLR __BIT(18)
# define ENET_EIR_WAKEUP __BIT(17)
# define ENET_EIR_TS_AVAIL __BIT(16)
# define ENET_EIR_TS_TIMER __BIT(15)
#define ENET_EIMR 0x00000008
#define ENET_RDAR 0x00000010
# define ENET_RDAR_ACTIVE __BIT(24)
#define ENET_TDAR 0x00000014
# define ENET_TDAR_ACTIVE __BIT(24)
#define ENET_ECR 0x00000024
# define ENET_ECR_DBSWP __BIT(8)
# define ENET_ECR_STOPEN __BIT(7)
# define ENET_ECR_DBGEN __BIT(6)
# define ENET_ECR_SPEED __BIT(5)
# define ENET_ECR_EN1588 __BIT(4)
# define ENET_ECR_SLEEP __BIT(3)
# define ENET_ECR_MAGICEN __BIT(2)
# define ENET_ECR_ETHEREN __BIT(1)
# define ENET_ECR_RESET __BIT(0)
#define ENET_MMFR 0x00000040
# define ENET_MMFR_ST 0x40000000
# define ENET_MMFR_OP_FORCEWRITE 0x00000000
# define ENET_MMFR_OP_WRITE 0x10000000
# define ENET_MMFR_OP_READ 0x20000000
# define ENET_MMFR_OP_FORCEREAD 0x30000000
# define ENET_MMFR_TA 0x00020000
# define ENET_MMFR_PHY_ADDR(phy) __SHIFTIN(phy, __BITS(27, 23))
# define ENET_MMFR_PHY_REG(reg) __SHIFTIN(reg, __BITS(22, 18))
# define ENET_MMFR_DATAMASK 0x0000ffff
#define ENET_MSCR 0x00000044
# define ENET_MSCR_HOLDTIME_1CLK 0x00000000
# define ENET_MSCR_HOLDTIME_2CLK 0x00000100
# define ENET_MSCR_HOLDTIME_3CLK 0x00000200
# define ENET_MSCR_HOLDTIME_8CLK 0x00000700
# define ENET_MSCR_DIS_PRE __BIT(7)
# define ENET_MSCR_MII_SPEED_25MHZ __SHIFTIN(4, __BITS(6, 1))
# define ENET_MSCR_MII_SPEED_33MHZ __SHIFTIN(6, __BITS(6, 1))
# define ENET_MSCR_MII_SPEED_40MHZ __SHIFTIN(7, __BITS(6, 1))
# define ENET_MSCR_MII_SPEED_50MHZ __SHIFTIN(9, __BITS(6, 1))
# define ENET_MSCR_MII_SPEED_66MHZ __SHIFTIN(13, __BITS(6, 1))
#define ENET_MIBC 0x00000064
# define ENET_MIBC_MIB_DIS __BIT(31)
# define ENET_MIBC_MIB_IDLE __BIT(30)
# define ENET_MIBC_MIB_CLEAR __BIT(29)
#define ENET_RCR 0x00000084
# define ENET_RCR_GRS __BIT(31)
# define ENET_RCR_NLC __BIT(30)
# define ENET_RCR_MAX_FL(n) __SHIFTIN(n, __BITS(29, 16))
# define ENET_RCR_CFEN __BIT(15)
# define ENET_RCR_CRCFWD __BIT(14)
# define ENET_RCR_PAUFWD __BIT(13)
# define ENET_RCR_PADEN __BIT(12)
# define ENET_RCR_RMII_10T __BIT(9)
# define ENET_RCR_RGMII_EN __BIT(6)
# define ENET_RCR_FCE __BIT(5)
# define ENET_RCR_PROM __BIT(3)
# define ENET_RCR_DRT __BIT(1)
#define ENET_TCR 0x000000c4
# define ENET_TCR_FDEN __BIT(2)
#define ENET_PALR 0x000000e4
#define ENET_PAUR 0x000000e8
#define ENET_OPD 0x000000ec
#define ENET_IAUR 0x00000118
#define ENET_IALR 0x0000011c
#define ENET_GAUR 0x00000120
#define ENET_GALR 0x00000124
#define ENET_TFWR 0x00000144
# define ENET_TFWR_STRFWD __BIT(8)
# define ENET_TFWR_FIFO(n) __SHIFTIN(((n) / 64), __BITS(5, 0))
#define ENET_RDSR 0x00000180
#define ENET_TDSR 0x00000184
#define ENET_MRBR 0x00000188
#define ENET_RSFL 0x00000190
#define ENET_RSEM 0x00000194
#define ENET_RAEM 0x00000198
#define ENET_RAFL 0x0000019c
#define ENET_TSEM 0x000001a0
#define ENET_TAEM 0x000001a4
#define ENET_TAFL 0x000001a8
#define ENET_TIPG 0x000001ac
#define ENET_FTRL 0x000001b0
#define ENET_TACC 0x000001c0
# define ENET_TACC_PROCHK __BIT(4)
# define ENET_TACC_IPCHK __BIT(3)
# define ENET_TACC_SHIFT16 __BIT(0)
#define ENET_RACC 0x000001c4
# define ENET_RACC_SHIFT16 __BIT(7)
# define ENET_RACC_LINEDIS __BIT(6)
# define ENET_RACC_PRODIS __BIT(2)
# define ENET_RACC_IPDIS __BIT(1)
# define ENET_RACC_PADREM __BIT(0)
/* Statistics counters */
#define ENET_RMON_T_DROP 0x00000200
#define ENET_RMON_T_PACKETS 0x00000204
#define ENET_RMON_T_BC_PKT 0x00000208
#define ENET_RMON_T_MC_PKT 0x0000020c
#define ENET_RMON_T_CRC_ALIGN 0x00000210
#define ENET_RMON_T_UNDERSIZE 0x00000214
#define ENET_RMON_T_OVERSIZE 0x00000218
#define ENET_RMON_T_FRAG 0x0000021c
#define ENET_RMON_T_JAB 0x00000220
#define ENET_RMON_T_COL 0x00000224
#define ENET_RMON_T_P64 0x00000228
#define ENET_RMON_T_P65TO127N 0x0000022c
#define ENET_RMON_T_P128TO255N 0x00000230
#define ENET_RMON_T_P256TO511 0x00000234
#define ENET_RMON_T_P512TO1023 0x00000238
#define ENET_RMON_T_P1024TO2047 0x0000023c
#define ENET_RMON_T_P_GTE2048 0x00000240
#define ENET_RMON_T_OCTETS 0x00000244
#define ENET_IEEE_T_DROP 0x00000248
#define ENET_IEEE_T_FRAME_OK 0x0000024c
#define ENET_IEEE_T_1COL 0x00000250
#define ENET_IEEE_T_MCOL 0x00000254
#define ENET_IEEE_T_DEF 0x00000258
#define ENET_IEEE_T_LCOL 0x0000025c
#define ENET_IEEE_T_EXCOL 0x00000260
#define ENET_IEEE_T_MACERR 0x00000264
#define ENET_IEEE_T_CSERR 0x00000268
#define ENET_IEEE_T_SQE 0x0000026c
#define ENET_IEEE_T_FDXFC 0x00000270
#define ENET_IEEE_T_OCTETS_OK 0x00000274
#define ENET_RMON_R_PACKETS 0x00000284
#define ENET_RMON_R_BC_PKT 0x00000288
#define ENET_RMON_R_MC_PKT 0x0000028c
#define ENET_RMON_R_CRC_ALIGN 0x00000290
#define ENET_RMON_R_UNDERSIZE 0x00000294
#define ENET_RMON_R_OVERSIZE 0x00000298
#define ENET_RMON_R_FRAG 0x0000029c
#define ENET_RMON_R_JAB 0x000002a0
#define ENET_RMON_R_RESVD_0 0x000002a4
#define ENET_RMON_R_P64 0x000002a8
#define ENET_RMON_R_P65TO127 0x000002ac
#define ENET_RMON_R_P128TO255 0x000002b0
#define ENET_RMON_R_P256TO511 0x000002b4
#define ENET_RMON_R_P512TO1023 0x000002b8
#define ENET_RMON_R_P1024TO2047 0x000002bc
#define ENET_RMON_R_P_GTE2048 0x000002c0
#define ENET_RMON_R_OCTETS 0x000002c4
#define ENET_IEEE_R_DROP 0x000002c8
#define ENET_IEEE_R_FRAME_OK 0x000002cc
#define ENET_IEEE_R_CRC 0x000002d0
#define ENET_IEEE_R_ALIGN 0x000002d4
#define ENET_IEEE_R_MACERR 0x000002d8
#define ENET_IEEE_R_FDXFC 0x000002dc
#define ENET_IEEE_R_OCTETS_OK 0x000002e0
/* IEEE1588 control */
#define ENET_ATCR 0x00000400
#define ENET_ATVR 0x00000404
#define ENET_ATOFF 0x00000408
#define ENET_ATPER 0x0000040c
#define ENET_ATCOR 0x00000410
#define ENET_ATINC 0x00000414
#define ENET_ATSTMP 0x00000418
/* Capture/compare block */
#define ENET_TGSR 0x00000604
#define ENET_TCSR0 0x00000608
#define ENET_TCCR0 0x0000060c
#define ENET_TCSR1 0x00000610
#define ENET_TCCR1 0x00000614
#define ENET_TCSR2 0x00000618
#define ENET_TCCR2 0x0000061c
#define ENET_TCSR3 0x00000620
#define ENET_TCCR3 0x00000624
/* enhanced transmit buffer descriptor */
struct enet_txdesc {
uint32_t tx_flags1_len;
#define TXFLAGS1_R __BIT(31) /* Ready */
#define TXFLAGS1_T1 __BIT(30) /* TX software owner1 */
#define TXFLAGS1_W __BIT(29) /* Wrap */
#define TXFLAGS1_T2 __BIT(28) /* TX software owner2 */
#define TXFLAGS1_L __BIT(27) /* Last in frame */
#define TXFLAGS1_TC __BIT(26) /* Transmit CRC */
#define TXFLAGS1_ABC __BIT(25) /* Append bad CRC */
#define TXFLAGS1_LEN(n) ((n) & 0xffff)
uint32_t tx_databuf;
uint32_t tx_flags2;
#define TXFLAGS2_INT __BIT(30) /* Interrupt */
#define TXFLAGS2_TS __BIT(29) /* Timestamp */
#define TXFLAGS2_PINS __BIT(28) /* Insert Proto csum */
#define TXFLAGS2_IINS __BIT(27) /* Insert IP csum */
#define TXFLAGS2_TXE __BIT(15) /* Transmit error */
#define TXFLAGS2_UE __BIT(13) /* Underflow error */
#define TXFLAGS2_EE __BIT(12) /* Excess colls Err */
#define TXFLAGS2_FE __BIT(11) /* Frame Error */
#define TXFLAGS2_LCE __BIT(10) /* Late collision Err */
#define TXFLAGS2_OE __BIT(9) /* Overfow Error */
#define TXFLAGS2_TSE __BIT(8) /* Timestamp Error */
uint32_t tx__reserved1;
uint32_t tx_flags3;
#define TXFLAGS3_BDU __BIT(31)
uint32_t tx_1588timestamp;
uint32_t tx__reserved2;
uint32_t tx__reserved3;
} __packed;
/* enhanced receive buffer descriptor */
struct enet_rxdesc {
uint32_t rx_flags1_len;
#define RXFLAGS1_E __BIT(31) /* Empty */
#define RXFLAGS1_R1 __BIT(30) /* RX software owner1 */
#define RXFLAGS1_W __BIT(29) /* Wrap */
#define RXFLAGS1_R2 __BIT(28) /* RX software owner2 */
#define RXFLAGS1_L __BIT(27) /* Last in frame */
#define RXFLAGS1_M __BIT(24) /* Miss */
#define RXFLAGS1_BC __BIT(23) /* Broadcast */
#define RXFLAGS1_MC __BIT(22) /* Multicast */
#define RXFLAGS1_LG __BIT(21) /* Length Violation */
#define RXFLAGS1_NO __BIT(20) /* Non-Octet aligned */
#define RXFLAGS1_CR __BIT(18) /* CRC or frame error */
#define RXFLAGS1_OV __BIT(17) /* Overrun */
#define RXFLAGS1_TR __BIT(16) /* Truncated */
#define RXFLAGS1_LEN(n) ((n) & 0xffff)
uint32_t rx_databuf;
uint32_t rx_flags2;
#define RXFLAGS2_ME __BIT(31) /* MAC error */
#define RXFLAGS2_PE __BIT(26) /* PHY error */
#define RXFLAGS2_CE __BIT(25) /* Collision */
#define RXFLAGS2_UC __BIT(24) /* Unicast */
#define RXFLAGS2_INT __BIT(23) /* RXB/RXF interrupt */
#define RXFLAGS2_ICE __BIT(5) /* IP csum error */
#define RXFLAGS2_PCR __BIT(4) /* Proto csum error */
#define RXFLAGS2_VLAN __BIT(2) /* VLAN */
#define RXFLAGS2_IPV6 __BIT(1) /* IPv6 frame */
#define RXFLAGS2_FRAG __BIT(0) /* IPv4 fragment */
#if _BYTE_ORDER == _LITTLE_ENDIAN
uint16_t rx_cksum;
uint8_t rx_proto;
uint8_t rx_hl;
#else
uint8_t rx_hl;
uint8_t rx_proto;
uint16_t rx_cksum;
#endif
uint32_t rx_flags3;
#define RXFLAGS3_BDU __BIT(31)
uint32_t rx_1588timestamp;
uint32_t rx__reserved2;
uint32_t rx__reserved3;
} __packed;
#endif /* _ARM_IMX_IF_ENETREG_H_ */

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/* $NetBSD: imx6_ahcisata.c,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: imx6_ahcisata.c,v 1.1 2014/09/25 05:05:28 ryo Exp $");
#include "locators.h"
#include "opt_imx.h"
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/device.h>
#include <arm/imx/imx6_reg.h>
#include <arm/imx/imx6var.h>
#include <arm/imx/imx6_ahcisatareg.h>
#include <arm/imx/imx6_iomuxreg.h>
#include <arm/imx/imx6_ccmreg.h>
#include <arm/imx/imx6_ccmvar.h>
#include <dev/ata/atavar.h>
#include <dev/ic/ahcisatavar.h>
struct imx_ahci_softc {
device_t sc_dev;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_ioh;
void *sc_ih;
struct ahci_softc sc_ahcisc;
};
static int imx6_ahcisata_match(device_t, cfdata_t, void *);
static void imx6_ahcisata_attach(device_t, device_t, void *);
static int imx6_ahcisata_detach(device_t, int);
static int ixm6_ahcisata_init(struct imx_ahci_softc *);
static int imx6_ahcisata_phy_ctrl(struct imx_ahci_softc *, uint32_t, int);
static int imx6_ahcisata_phy_addr(struct imx_ahci_softc *, uint32_t);
static int imx6_ahcisata_phy_write(struct imx_ahci_softc *, uint32_t, uint16_t);
static int imx6_ahcisata_phy_read(struct imx_ahci_softc *, uint32_t);
CFATTACH_DECL_NEW(imx6_ahcisata, sizeof(struct imx_ahci_softc),
imx6_ahcisata_match, imx6_ahcisata_attach, imx6_ahcisata_detach, NULL);
static int
imx6_ahcisata_match(device_t parent, cfdata_t match, void *aux)
{
struct axi_attach_args * const aa = aux;
if (aa->aa_addr == IMX6_SATA_BASE)
return 1;
return 0;
}
static void
imx6_ahcisata_attach(device_t parent, device_t self, void *aux)
{
struct imx_ahci_softc *sc;
struct ahci_softc *ahci_sc;
struct axi_attach_args *aa;
aa = aux;
sc = device_private(self);
sc->sc_dev = self;
sc->sc_iot = aa->aa_iot;
if (aa->aa_size == AXICF_SIZE_DEFAULT)
aa->aa_size = IMX6_SATA_SIZE;
aprint_naive("\n");
aprint_normal(": AHCI Controller\n");
if (bus_space_map(aa->aa_iot, aa->aa_addr, aa->aa_size, 0,
&sc->sc_ioh)) {
aprint_error_dev(self, "cannot map registers\n");
return;
}
if (ixm6_ahcisata_init(sc) != 0) {
aprint_error_dev(self, "couldn't init ahci\n");
return;
}
ahci_sc = &sc->sc_ahcisc;
ahci_sc->sc_atac.atac_dev = sc->sc_dev;
ahci_sc->sc_ahci_ports = 1;
ahci_sc->sc_dmat = aa->aa_dmat;
ahci_sc->sc_ahcis = aa->aa_size;
ahci_sc->sc_ahcit = sc->sc_iot;
ahci_sc->sc_ahcih = sc->sc_ioh;
sc->sc_ih = intr_establish(aa->aa_irq, IPL_BIO, IST_LEVEL,
ahci_intr, ahci_sc);
if (sc->sc_ih == NULL) {
aprint_error_dev(self, "unable to establish interrupt\n");
return;
}
ahci_attach(ahci_sc);
}
static int
imx6_ahcisata_detach(device_t self, int flags)
{
struct imx_ahci_softc *sc;
struct ahci_softc *ahci_sc;
int rv;
sc = device_private(self);
ahci_sc = &sc->sc_ahcisc;
rv = ahci_detach(ahci_sc, flags);
if (rv)
return rv;
if (sc->sc_ih) {
intr_disestablish(sc->sc_ih);
sc->sc_ih = NULL;
}
if (ahci_sc->sc_ahcis) {
bus_space_unmap(ahci_sc->sc_ahcit, ahci_sc->sc_ahcih,
ahci_sc->sc_ahcis);
ahci_sc->sc_ahcis = 0;
ahci_sc->sc_ahcit = 0;
ahci_sc->sc_ahcih = 0;
}
return 0;
}
static int
imx6_ahcisata_phy_ctrl(struct imx_ahci_softc *sc, uint32_t bitmask, int on)
{
uint32_t v;
int timeout;
v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SATA_P0PHYCR);
if (on)
v |= bitmask;
else
v &= ~bitmask;
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SATA_P0PHYCR, v);
for (timeout = 5000; timeout > 0; --timeout) {
v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SATA_P0PHYSR);
if (!!(v & SATA_P0PHYSR_CR_ACK) == !!on)
break;
delay(100);
}
if (timeout > 0)
return 0;
return -1;
}
static int
imx6_ahcisata_phy_addr(struct imx_ahci_softc *sc, uint32_t addr)
{
delay(100);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SATA_P0PHYCR, addr);
if (imx6_ahcisata_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_ADDR, 1) != 0)
return -1;
if (imx6_ahcisata_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_ADDR, 0) != 0)
return -1;
return 0;
}
static int
imx6_ahcisata_phy_write(struct imx_ahci_softc *sc, uint32_t addr,
uint16_t data)
{
if (imx6_ahcisata_phy_addr(sc, addr) != 0)
return -1;
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SATA_P0PHYCR, data);
if (imx6_ahcisata_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_DATA, 1) != 0)
return -1;
if (imx6_ahcisata_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_DATA, 0) != 0)
return -1;
if ((addr == SATA_PHY_CLOCK_RESET) && data) {
/* we can't check ACK after RESET */
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SATA_P0PHYCR,
data | SATA_P0PHYCR_CR_WRITE);
return 0;
}
if (imx6_ahcisata_phy_ctrl(sc, SATA_P0PHYCR_CR_WRITE, 1) != 0)
return -1;
if (imx6_ahcisata_phy_ctrl(sc, SATA_P0PHYCR_CR_WRITE, 0) != 0)
return -1;
return 0;
}
static int
imx6_ahcisata_phy_read(struct imx_ahci_softc *sc, uint32_t addr)
{
uint32_t v;
if (imx6_ahcisata_phy_addr(sc, addr) != 0)
return -1;
if (imx6_ahcisata_phy_ctrl(sc, SATA_P0PHYCR_CR_READ, 1) != 0)
return -1;
v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SATA_P0PHYSR);
if (imx6_ahcisata_phy_ctrl(sc, SATA_P0PHYCR_CR_READ, 0) != 0)
return -1;
return SATA_P0PHYSR_CR_DATA_OUT(v);
}
static int
ixm6_ahcisata_init(struct imx_ahci_softc *sc)
{
uint32_t v;
int timeout;
/* AHCISATA clock enable */
v = imx6_ccm_read(CCM_CCGR5);
imx6_ccm_write(CCM_CCGR5, v | CCM_CCGR5_100M_CLK_ENABLE(3));
/* PLL power up */
if (imx6_pll_power(CCM_ANALOG_PLL_ENET, 1) != 0) {
aprint_error_dev(sc->sc_dev,
"couldn't enable CCM_ANALOG_PLL_ENET\n");
return -1;
}
v = imx6_ccm_read(CCM_ANALOG_PLL_ENET);
v |= CCM_ANALOG_PLL_ENET_ENABLE_100M;
imx6_ccm_write(CCM_ANALOG_PLL_ENET, v);
v = iomux_read(IOMUX_GPR13);
/* clear */
v &= ~(IOMUX_GPR13_SATA_PHY_8(7) |
IOMUX_GPR13_SATA_PHY_7(0x1f) |
IOMUX_GPR13_SATA_PHY_6(7) |
IOMUX_GPR13_SATA_SPEED(1) |
IOMUX_GPR13_SATA_PHY_5(1) |
IOMUX_GPR13_SATA_PHY_4(7) |
IOMUX_GPR13_SATA_PHY_3(0xf) |
IOMUX_GPR13_SATA_PHY_2(0x1f) |
IOMUX_GPR13_SATA_PHY_1(1) |
IOMUX_GPR13_SATA_PHY_0(1));
/* setting */
v |= IOMUX_GPR13_SATA_PHY_8(5) | /* Rx 3.0db */
IOMUX_GPR13_SATA_PHY_7(0x12) | /* Rx SATA2m */
IOMUX_GPR13_SATA_PHY_6(3) | /* Rx DPLL mode */
IOMUX_GPR13_SATA_SPEED(1) | /* 3.0GHz */
IOMUX_GPR13_SATA_PHY_5(0) | /* SpreadSpectram */
IOMUX_GPR13_SATA_PHY_4(4) | /* Tx Attenuation 9/16 */
IOMUX_GPR13_SATA_PHY_3(0) | /* Tx Boost 0db */
IOMUX_GPR13_SATA_PHY_2(0x11) | /* Tx Level 1.104V */
IOMUX_GPR13_SATA_PHY_1(1); /* PLL clock enable */
iomux_write(IOMUX_GPR13, v);
/* phy reset */
if (imx6_ahcisata_phy_write(sc, SATA_PHY_CLOCK_RESET,
SATA_PHY_CLOCK_RESET_RST) < 0) {
aprint_error_dev(sc->sc_dev, "cannot reset PHY\n");
return -1;
}
for (timeout = 50; timeout > 0; --timeout) {
delay(100);
v = imx6_ahcisata_phy_read(sc, SATA_PHY_LANE0_OUT_STAT);
if (v < 0) {
aprint_error_dev(sc->sc_dev,
"cannot read LANE0 status\n");
break;
}
if (v & SATA_PHY_LANE0_OUT_STAT_RX_PLL_STATE)
break;
}
if (timeout <= 0)
return -1;
/* Support Staggered Spin-up */
v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SATA_CAP);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SATA_CAP, v | SATA_CAP_SSS);
/* Ports Implmented. must set 1 */
v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SATA_PI);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SATA_PI, v | SATA_PI_PI);
/* set 1ms-timer = AHB clock / 1000 */
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SATA_TIMER1MS,
imx6_get_clock(IMX6CLK_AHB) / 1000);
return 0;
}

76
sys/arch/arm/imx/imx6_ahcisatareg.h Normal file
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/* $NetBSD: imx6_ahcisatareg.h,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_IMX_IMX6_AHCISATAREG_H_
#define _ARM_IMX_IMX6_AHCISATAREG_H_
#define SATA_CAP 0x00000000
#define SATA_CAP_SSS __BIT(27)
#define SATA_PI 0x0000000c
#define SATA_PI_PI __BIT(0)
#define SATA_BISTAFR 0x000000a0
#define SATA_BISTCR 0x000000a4
#define SATA_BISTFCTR 0x000000a8
#define SATA_BISTSR 0x000000ac
#define SATA_OOBR 0x000000bc
#define SATA_GPCR 0x000000d0
#define SATA_GPSR 0x000000d4
#define SATA_TIMER1MS 0x000000e0
#define SATA_TESTR 0x000000f4
#define SATA_VERSIONR 0x000000f8
#define SATA_P0DMACR 0x00000170
#define SATA_P0DMACR_RXTS(n) __SHIFTIN(n, __BITS(7, 4))
#define SATA_P0DMACR_TXTS(n) __SHIFTIN(n, __BITS(3, 0))
#define SATA_P0PHYCR 0x00000178
#define SATA_P0PHYCR_CR_READ __BIT(19)
#define SATA_P0PHYCR_CR_WRITE __BIT(18)
#define SATA_P0PHYCR_CR_CAP_DATA __BIT(17)
#define SATA_P0PHYCR_CR_CAP_ADDR __BIT(16)
#define SATA_P0PHYCR_CR_DATA_IN(v) ((v) & 0xffff)
#define SATA_P0PHYSR 0x0000017c
#define SATA_P0PHYSR_CR_ACK __BIT(18)
#define SATA_P0PHYSR_CR_DATA_OUT(v) ((v) & 0xffff)
/* phy registers */
#define SATA_PHY_CLOCK_CTL_OVRD 0x0013
#define SATA_PHY_CLOCK_CTL_OVRD_MPLL_PWRON __BIT(2)
#define SATA_PHY_CLOCK_RESET 0x7f3f
#define SATA_PHY_CLOCK_RESET_RST __BIT(0)
#define SATA_PHY_LANE0_OUT_STAT 0x2003
#define SATA_PHY_LANE0_OUT_STAT_RX_PLL_STATE __BIT(1)
#define SATA_PHY_LANE0_TX_OVRD 0x2004
#define SATA_PHY_LANE0_TX_OVRD_TX_EN(n) __SHIFTIN(n, __BITS(3, 1))
#define SATA_PHY_LANE0_RX_OVRD 0x2005
#define SATA_PHY_LANE0_RX_OVRD_RX_EN __BIT(2)
#define SATA_PHY_LANE0_RX_OVRD_RX_PLL_PWRON __BIT(1)
#endif /* _ARM_IMX_IMX6_AHCISATAREG_H_ */

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sys/arch/arm/imx/imx6_axi.c Normal file
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/* $NetBSD: imx6_axi.c,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: imx6_axi.c,v 1.1 2014/09/25 05:05:28 ryo Exp $");
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/device.h>
#include <uvm/uvm_extern.h>
#include <arm/imx/imx6_reg.h>
#include <arm/imx/imx6var.h>
#include "bus_dma_generic.h"
#include "locators.h"
struct axi_softc {
device_t sc_dev;
bus_space_tag_t sc_iot;
bus_dma_tag_t sc_dmat;
};
static int axi_match(device_t, struct cfdata *, void *);
static void axi_attach(device_t, device_t, void *);
static int axi_search(device_t, struct cfdata *, const int *, void *);
static int axi_critical_search(device_t, struct cfdata *, const int *, void *);
static int axi_search(device_t, struct cfdata *, const int *, void *);
static int axi_print(void *, const char *);
CFATTACH_DECL_NEW(axi, sizeof(struct axi_softc),
axi_match, axi_attach, NULL, NULL);
/* ARGSUSED */
static int
axi_match(device_t parent __unused, struct cfdata *match __unused,
void *aux __unused)
{
return 1;
}
/* ARGSUSED */
static void
axi_attach(device_t parent __unused, device_t self, void *aux __unused)
{
struct axi_softc *sc;
struct axi_attach_args aa;
aprint_normal(": Advanced eXtensible Interface\n");
aprint_naive("\n");
sc = device_private(self);
sc->sc_iot = &imx_bs_tag;
#if NBUS_DMA_GENERIC > 0
sc->sc_dmat = &imx_bus_dma_tag;
#else
sc->sc_dmat = 0;
#endif
aa.aa_name = "axi";
aa.aa_iot = sc->sc_iot;
aa.aa_dmat = sc->sc_dmat;
config_search_ia(axi_critical_search, self, "axi", &aa);
config_search_ia(axi_search, self, "axi", &aa);
}
/* ARGSUSED */
static int
axi_critical_search(device_t parent, struct cfdata *cf,
const int *ldesc __unused, void *aux)
{
struct axi_attach_args *aa;
aa = aux;
if ((strcmp(cf->cf_name, "imxccm") != 0) &&
(strcmp(cf->cf_name, "imxgpio") != 0) &&
(strcmp(cf->cf_name, "imxiomux") != 0) &&
(strcmp(cf->cf_name, "imxocotp") != 0) &&
(strcmp(cf->cf_name, "imxuart") != 0))
return 0;
aa->aa_name = cf->cf_name;
aa->aa_addr = cf->cf_loc[AXICF_ADDR];
aa->aa_size = cf->cf_loc[AXICF_SIZE];
aa->aa_irq = cf->cf_loc[AXICF_IRQ];
aa->aa_irqbase = cf->cf_loc[AXICF_IRQBASE];
if (config_match(parent, cf, aux) > 0)
config_attach(parent, cf, aux, axi_print);
return 0;
}
/* ARGSUSED */
static int
axi_search(device_t parent, struct cfdata *cf, const int *ldesc __unused,
void *aux)
{
struct axi_attach_args *aa;
aa = aux;
aa->aa_addr = cf->cf_loc[AXICF_ADDR];
aa->aa_size = cf->cf_loc[AXICF_SIZE];
aa->aa_irq = cf->cf_loc[AXICF_IRQ];
aa->aa_irqbase = cf->cf_loc[AXICF_IRQBASE];
if (config_match(parent, cf, aux) > 0)
config_attach(parent, cf, aux, axi_print);
return 0;
}
/* ARGSUSED */
static int
axi_print(void *aux, const char *name __unused)
{
struct axi_attach_args *aa = (struct axi_attach_args *)aux;
if (aa->aa_addr != AXICF_ADDR_DEFAULT) {
aprint_normal(" addr 0x%lx", aa->aa_addr);
if (aa->aa_size > AXICF_SIZE_DEFAULT)
aprint_normal("-0x%lx",
aa->aa_addr + aa->aa_size-1);
}
if (aa->aa_irq != AXICF_IRQ_DEFAULT)
aprint_normal(" intr %d", aa->aa_irq);
if (aa->aa_irqbase != AXICF_IRQBASE_DEFAULT)
aprint_normal(" irqbase %d", aa->aa_irqbase);
return (UNCONF);
}

188
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/* $NetBSD: imx6_board.c,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*
* Copyright (c) 2012 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(1, "$NetBSD: imx6_board.c,v 1.1 2014/09/25 05:05:28 ryo Exp $");
#include "opt_imx.h"
#include "arml2cc.h"
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/cpu.h>
#include <sys/device.h>
#include <arm/locore.h>
#include <arm/cortex/a9tmr_var.h>
#include <arm/cortex/pl310_var.h>
#include <arm/mainbus/mainbus.h>
#include <arm/imx/imx6var.h>
#include <arm/imx/imx6_reg.h>
#include <arm/imx/imx6_mmdcreg.h>
#include <arm/imx/imxwdogreg.h>
bus_space_tag_t imx6_ioreg_bst = &imx_bs_tag;
bus_space_handle_t imx6_ioreg_bsh;
bus_space_tag_t imx6_armcore_bst = &imx_bs_tag;
bus_space_handle_t imx6_armcore_bsh;
void
imx6_bootstrap(vaddr_t iobase)
{
int error;
/* imx6_ioreg is mapped AIPS1+AIPS2 region */
imx6_ioreg_bsh = (bus_space_handle_t)iobase;
error = bus_space_map(imx6_ioreg_bst, IMX6_IOREG_PBASE,
IMX6_IOREG_SIZE, 0, &imx6_ioreg_bsh);
if (error)
panic("%s: failed to map Imx %s registers: %d",
__func__, "io", error);
imx6_armcore_bsh = (bus_space_handle_t) iobase + IMX6_IOREG_SIZE;
error = bus_space_map(imx6_armcore_bst, IMX6_ARMCORE_PBASE,
IMX6_ARMCORE_SIZE, 0, &imx6_armcore_bsh);
if (error)
panic("%s: failed to map Imx %s registers: %d",
__func__, "armcore", error);
#if NARML2CC > 0
arml2cc_init(imx6_armcore_bst, imx6_armcore_bsh, ARMCORE_L2C_BASE);
#endif
}
/*
* probe DDR size from DDR Controller register
*/
psize_t
imx6_memprobe(void)
{
uint32_t ctrl, misc;
int bitwidth;
ctrl = bus_space_read_4(imx6_ioreg_bst, imx6_ioreg_bsh,
IMX6_AIPS1_SIZE + AIPS2_MMDC1_BASE + MMDC1_MDCTL);
misc = bus_space_read_4(imx6_ioreg_bst, imx6_ioreg_bsh,
IMX6_AIPS1_SIZE + AIPS2_MMDC1_BASE + MMDC1_MDMISC);
/* row */
bitwidth = __SHIFTOUT(ctrl, MMDC1_MDCTL_ROW) + 11;
/* column */
switch (__SHIFTOUT(ctrl, MMDC1_MDCTL_COL)) {
case 0:
bitwidth += 9;
break;
case 1:
bitwidth += 10;
break;
case 2:
bitwidth += 11;
break;
case 3:
bitwidth += 8;
break;
case 4:
bitwidth += 12;
break;
default:
printf("AIPS2_MMDC1:MDCTL[COL]: "
"unknown column address width: %llu\n",
__SHIFTOUT(ctrl, MMDC1_MDCTL_COL));
return 0;
}
/* width */
bitwidth += __SHIFTOUT(ctrl, MMDC1_MDCTL_DSIZ) + 1;
/* bank */
bitwidth += __SHIFTOUT(ctrl, MMDC1_MDCTL_SDE_1);
bitwidth += (misc & MMDC1_MDMISC_DDR_4_BANK) ? 2 : 3;
return (psize_t)1 << bitwidth;
}
void
imx6_reset(void)
{
delay(1000); /* wait for flushing FIFO of serial console */
cpsid(I32_bit|F32_bit);
/* software reset signal on wdog */
bus_space_write_2(imx6_ioreg_bst, imx6_ioreg_bsh,
AIPS1_WDOG1_BASE + IMX_WDOG_WCR, WCR_WDE);
/*
* write twice due to errata.
* Reference: ERR004346: IMX6DQCE Chip Errata for the i.MX 6Dual/6Quad
*/
bus_space_write_2(imx6_ioreg_bst, imx6_ioreg_bsh,
AIPS1_WDOG1_BASE + IMX_WDOG_WCR, WCR_WDE);
for (;;)
__asm("wfi");
}
void
imx6_device_register(device_t self, void *aux)
{
prop_dictionary_t dict = device_properties(self);
if (device_is_a(self, "armperiph") &&
device_is_a(device_parent(self), "mainbus")) {
/*
* XXX KLUDGE ALERT XXX
* The iot mainbus supplies is completely wrong since it scales
* addresses by 2. The simpliest remedy is to replace with our
* bus space used for the armcore regisers (which armperiph uses).
*/
struct mainbus_attach_args * const mb = aux;
mb->mb_iot = imx6_armcore_bst;
return;
}
/*
* We need to tell the A9 Global/Watchdog Timer
* what frequency it runs at.
*/
if (device_is_a(self, "a9tmr") || device_is_a(self, "a9wdt")) {
prop_dictionary_set_uint32(dict, "frequency",
792000000 / 2); /* XXX? */
return;
}
}
#ifdef MULTIPROCESSOR
void
imx6_cpu_hatch(struct cpu_info *ci)
{
a9tmr_init_cpu_clock(ci);
}
#endif

730
sys/arch/arm/imx/imx6_ccm.c Normal file
View File

@ -0,0 +1,730 @@
/* $NetBSD: imx6_ccm.c,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*
* Copyright (c) 2010-2012, 2014 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Clock Controller Module (CCM) for i.MX5
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: imx6_ccm.c,v 1.1 2014/09/25 05:05:28 ryo Exp $");
#include "opt_imx.h"
#include "opt_imx6clk.h"
#include "locators.h"
#include <sys/types.h>
#include <sys/time.h>
#include <sys/bus.h>
#include <sys/device.h>
#include <sys/sysctl.h>
#include <sys/cpufreq.h>
#include <sys/malloc.h>
#include <sys/param.h>
#include <machine/cpu.h>
#include <arm/imx/imx6_ccmvar.h>
#include <arm/imx/imx6_ccmreg.h>
#include <arm/imx/imx6var.h>
#include <arm/imx/imx6_reg.h>
#ifndef IMX6_OSC_FREQ
#define IMX6_OSC_FREQ (24 * 1000 * 1000) /* 24MHz */
#endif
struct imxccm_softc {
device_t sc_dev;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_ioh;
/* for sysctl */
struct sysctllog *sc_log;
int sc_sysctlnode_pll1_arm;
int sc_sysctlnode_pll2_sys;
int sc_sysctlnode_pll3_usb1;
int sc_sysctlnode_pll7_usb2;
int sc_sysctlnode_pll4_audio;
int sc_sysctlnode_pll5_video;
int sc_sysctlnode_pll6_enet;
/* int sc_sysctlnode_pll8_mlb; */
int sc_sysctlnode_arm;
int sc_sysctlnode_periph;
int sc_sysctlnode_ahb;
int sc_sysctlnode_ipg;
int sc_sysctlnode_axi;
};
struct imxccm_softc *ccm_softc;
static int imxccm_match(device_t, cfdata_t, void *);
static void imxccm_attach(device_t, device_t, void *);
static int imxccm_sysctl_freq_helper(SYSCTLFN_PROTO);
static int imxccm_sysctl_setup(struct imxccm_softc *);
CFATTACH_DECL_NEW(imxccm, sizeof(struct imxccm_softc),
imxccm_match, imxccm_attach, NULL, NULL);
static int
imxccm_match(device_t parent, cfdata_t cfdata, void *aux)
{
struct axi_attach_args *aa = aux;
if (ccm_softc != NULL)
return 0;
if (aa->aa_addr == IMX6_AIPS1_BASE + AIPS1_CCM_BASE)
return 1;
return 0;
}
static void
imxccm_attach(device_t parent, device_t self, void *aux)
{
struct imxccm_softc * const sc = device_private(self);
struct axi_attach_args *aa = aux;
bus_space_tag_t iot = aa->aa_iot;
ccm_softc = sc;
sc->sc_dev = self;
sc->sc_iot = iot;
sc->sc_log = NULL;
if (bus_space_map(iot, aa->aa_addr, IMX6_CCM_SIZE, 0, &sc->sc_ioh)) {
aprint_error(": can't map registers\n");
return;
}
aprint_normal(": Clock Control Module\n");
aprint_naive("\n");
imxccm_sysctl_setup(sc);
aprint_verbose_dev(self, "PLL_ARM clock=%d\n",
imx6_get_clock(IMX6CLK_PLL1));
aprint_verbose_dev(self, "PLL_SYS clock=%d\n",
imx6_get_clock(IMX6CLK_PLL2));
aprint_verbose_dev(self, "PLL_USB1 clock=%d\n",
imx6_get_clock(IMX6CLK_PLL3));
aprint_verbose_dev(self, "PLL_USB2 clock=%d\n",
imx6_get_clock(IMX6CLK_PLL7));
aprint_verbose_dev(self, "PLL_AUDIO clock=%d\n",
imx6_get_clock(IMX6CLK_PLL4));
aprint_verbose_dev(self, "PLL_VIDEO clock=%d\n",
imx6_get_clock(IMX6CLK_PLL5));
aprint_verbose_dev(self, "PLL_ENET clock=%d\n",
imx6_get_clock(IMX6CLK_PLL6));
aprint_verbose_dev(self, "PLL_MLB clock=%d\n",
imx6_get_clock(IMX6CLK_PLL7));
aprint_verbose_dev(self, "IMX6CLK_PLL2_PFD0=%d\n",
imx6_get_clock(IMX6CLK_PLL2_PFD0));
aprint_verbose_dev(self, "IMX6CLK_PLL2_PFD1=%d\n",
imx6_get_clock(IMX6CLK_PLL2_PFD1));
aprint_verbose_dev(self, "IMX6CLK_PLL2_PFD2=%d\n",
imx6_get_clock(IMX6CLK_PLL2_PFD2));
aprint_verbose_dev(self, "IMX6CLK_PLL3_PFD0=%d\n",
imx6_get_clock(IMX6CLK_PLL3_PFD0));
aprint_verbose_dev(self, "IMX6CLK_PLL3_PFD1=%d\n",
imx6_get_clock(IMX6CLK_PLL3_PFD1));
aprint_verbose_dev(self, "IMX6CLK_PLL3_PFD2=%d\n",
imx6_get_clock(IMX6CLK_PLL3_PFD2));
aprint_verbose_dev(self, "IMX6CLK_PLL3_PFD3=%d\n",
imx6_get_clock(IMX6CLK_PLL3_PFD3));
aprint_verbose_dev(self, "IMX6CLK_ARM_ROOT=%d\n",
imx6_get_clock(IMX6CLK_ARM_ROOT));
aprint_verbose_dev(self, "IMX6CLK_PERIPH=%d\n",
imx6_get_clock(IMX6CLK_PERIPH));
aprint_verbose_dev(self, "IMX6CLK_AHB=%d\n",
imx6_get_clock(IMX6CLK_AHB));
aprint_verbose_dev(self, "IMX6CLK_IPG=%d\n",
imx6_get_clock(IMX6CLK_IPG));
aprint_verbose_dev(self, "IMX6CLK_AXI=%d\n",
imx6_get_clock(IMX6CLK_AXI));
aprint_verbose_dev(self, "IMX6CLK_USDHC1=%d\n",
imx6_get_clock(IMX6CLK_USDHC1_CLK_ROOT));
aprint_verbose_dev(self, "IMX6CLK_USDHC2=%d\n",
imx6_get_clock(IMX6CLK_USDHC2_CLK_ROOT));
aprint_verbose_dev(self, "IMX6CLK_USDHC3=%d\n",
imx6_get_clock(IMX6CLK_USDHC3_CLK_ROOT));
aprint_verbose_dev(self, "IMX6CLK_USDHC4=%d\n",
imx6_get_clock(IMX6CLK_USDHC4_CLK_ROOT));
}
static int
imxccm_sysctl_setup(struct imxccm_softc *sc)
{
const struct sysctlnode *node, *imxnode, *freqnode, *pllnode;
int rv;
rv = sysctl_createv(&sc->sc_log, 0, NULL, &node,
CTLFLAG_PERMANENT, CTLTYPE_NODE,
"machdep", NULL,
NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL);
if (rv != 0)
goto fail;
rv = sysctl_createv(&sc->sc_log, 0, &node, &imxnode,
0, CTLTYPE_NODE,
"imx6", NULL,
NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL);
if (rv != 0)
goto fail;
rv = sysctl_createv(&sc->sc_log, 0, &imxnode, &freqnode,
0, CTLTYPE_NODE,
"frequency", NULL,
NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL);
if (rv != 0)
goto fail;
rv = sysctl_createv(&sc->sc_log, 0, &freqnode, &pllnode,
0, CTLTYPE_NODE,
"pll", NULL,
NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL);
if (rv != 0)
goto fail;
rv = sysctl_createv(&sc->sc_log, 0, &pllnode, &node,
CTLFLAG_READWRITE, CTLTYPE_INT,
"arm", SYSCTL_DESCR("frequency of ARM clock (PLL1)"),
imxccm_sysctl_freq_helper, 0, (void *)sc, 0, CTL_CREATE, CTL_EOL);
if (rv != 0)
goto fail;
sc->sc_sysctlnode_pll1_arm= node->sysctl_num;
rv = sysctl_createv(&sc->sc_log, 0, &pllnode, &node,
0, CTLTYPE_INT,
"system", SYSCTL_DESCR("frequency of system clock (PLL2)"),
imxccm_sysctl_freq_helper, 0, (void *)sc, 0, CTL_CREATE, CTL_EOL);
if (rv != 0)
goto fail;
sc->sc_sysctlnode_pll2_sys = node->sysctl_num;
rv = sysctl_createv(&sc->sc_log, 0, &pllnode, &node,
0, CTLTYPE_INT,
"usb1", SYSCTL_DESCR("frequency of USB1 clock (PLL3)"),
imxccm_sysctl_freq_helper, 0, (void *)sc, 0, CTL_CREATE, CTL_EOL);
if (rv != 0)
goto fail;
sc->sc_sysctlnode_pll3_usb1 = node->sysctl_num;
rv = sysctl_createv(&sc->sc_log, 0, &pllnode, &node,
0, CTLTYPE_INT,
"usb2", SYSCTL_DESCR("frequency of USB2 clock (PLL7)"),
imxccm_sysctl_freq_helper, 0, (void *)sc, 0, CTL_CREATE, CTL_EOL);
if (rv != 0)
goto fail;
sc->sc_sysctlnode_pll7_usb2 = node->sysctl_num;
rv = sysctl_createv(&sc->sc_log, 0, &pllnode, &node,
0, CTLTYPE_INT,
"audio", SYSCTL_DESCR("frequency of AUDIO clock (PLL4)"),
imxccm_sysctl_freq_helper, 0, (void *)sc, 0, CTL_CREATE, CTL_EOL);
if (rv != 0)
goto fail;
sc->sc_sysctlnode_pll4_audio = node->sysctl_num;
rv = sysctl_createv(&sc->sc_log, 0, &pllnode, &node,
0, CTLTYPE_INT,
"video", SYSCTL_DESCR("frequency of VIDEO clock (PLL5)"),
imxccm_sysctl_freq_helper, 0, (void *)sc, 0, CTL_CREATE, CTL_EOL);
if (rv != 0)
goto fail;
sc->sc_sysctlnode_pll5_video = node->sysctl_num;
rv = sysctl_createv(&sc->sc_log, 0, &pllnode, &node,
0, CTLTYPE_INT,
"enet", SYSCTL_DESCR("frequency of ENET clock (PLL6)"),
imxccm_sysctl_freq_helper, 0, (void *)sc, 0, CTL_CREATE, CTL_EOL);
if (rv != 0)
goto fail;
sc->sc_sysctlnode_pll6_enet = node->sysctl_num;
#if 0
rv = sysctl_createv(&sc->sc_log, 0, &pllnode, &node,
0, CTLTYPE_INT,
"mlb", SYSCTL_DESCR("frequency of MediaLinkBus clock (PLL8)"),
imxccm_sysctl_freq_helper, 0, (void *)sc, 0, CTL_CREATE, CTL_EOL);
if (rv != 0)
goto fail;
sc->sc_sysctlnode_pll8_mlb = node->sysctl_num;
#endif
rv = sysctl_createv(&sc->sc_log, 0, &freqnode, &node,
CTLFLAG_READWRITE, CTLTYPE_INT,
"arm", SYSCTL_DESCR("frequency of ARM Root clock"),
imxccm_sysctl_freq_helper, 0, (void *)sc, 0, CTL_CREATE, CTL_EOL);
if (rv != 0)
goto fail;
sc->sc_sysctlnode_arm= node->sysctl_num;
rv = sysctl_createv(&sc->sc_log, 0, &freqnode, &node,
0, CTLTYPE_INT,
"peripheral", SYSCTL_DESCR("current frequency of Peripheral clock"),
imxccm_sysctl_freq_helper, 0, (void *)sc, 0, CTL_CREATE, CTL_EOL);
if (rv != 0)
goto fail;
sc->sc_sysctlnode_periph = node->sysctl_num;
rv = sysctl_createv(&sc->sc_log, 0, &freqnode, &node,
0, CTLTYPE_INT,
"ahb", SYSCTL_DESCR("current frequency of AHB clock"),
imxccm_sysctl_freq_helper, 0, (void *)sc, 0, CTL_CREATE, CTL_EOL);
if (rv != 0)
goto fail;
sc->sc_sysctlnode_ahb = node->sysctl_num;
rv = sysctl_createv(&sc->sc_log, 0, &freqnode, &node,
0, CTLTYPE_INT,
"ipg", SYSCTL_DESCR("current frequency of IPG clock"),
imxccm_sysctl_freq_helper, 0, (void *)sc, 0, CTL_CREATE, CTL_EOL);
if (rv != 0)
goto fail;
sc->sc_sysctlnode_ipg = node->sysctl_num;
rv = sysctl_createv(&sc->sc_log, 0, &freqnode, &node,
0, CTLTYPE_INT,
"axi", SYSCTL_DESCR("current frequency of AXI clock"),
imxccm_sysctl_freq_helper, 0, (void *)sc, 0, CTL_CREATE, CTL_EOL);
if (rv != 0)
goto fail;
sc->sc_sysctlnode_axi = node->sysctl_num;
return 0;
fail:
aprint_error_dev(sc->sc_dev, "cannot initialize sysctl (err=%d)\n", rv);
sysctl_teardown(&sc->sc_log);
sc->sc_log = NULL;
return -1;
}
static int
imxccm_sysctl_freq_helper(SYSCTLFN_ARGS)
{
struct sysctlnode node;
struct imxccm_softc *sc;
int value, ovalue, err;
node = *rnode;
sc = node.sysctl_data;
/* for sysctl read */
if (rnode->sysctl_num == sc->sc_sysctlnode_pll1_arm)
value = imx6_get_clock(IMX6CLK_PLL1);
else if (rnode->sysctl_num == sc->sc_sysctlnode_pll2_sys)
value = imx6_get_clock(IMX6CLK_PLL2);
else if (rnode->sysctl_num == sc->sc_sysctlnode_pll3_usb1)
value = imx6_get_clock(IMX6CLK_PLL3);
else if (rnode->sysctl_num == sc->sc_sysctlnode_pll7_usb2)
value = imx6_get_clock(IMX6CLK_PLL7);
else if (rnode->sysctl_num == sc->sc_sysctlnode_pll4_audio)
value = imx6_get_clock(IMX6CLK_PLL4);
else if (rnode->sysctl_num == sc->sc_sysctlnode_pll5_video)
value = imx6_get_clock(IMX6CLK_PLL5);
else if (rnode->sysctl_num == sc->sc_sysctlnode_pll6_enet)
value = imx6_get_clock(IMX6CLK_PLL6);
#if 0
else if (rnode->sysctl_num == sc->sc_sysctlnode_pll8_mlb)
value = imx6_get_clock(IMX6CLK_PLL8);
#endif
else if (rnode->sysctl_num == sc->sc_sysctlnode_arm)
value = imx6_get_clock(IMX6CLK_ARM_ROOT);
else if (rnode->sysctl_num == sc->sc_sysctlnode_periph)
value = imx6_get_clock(IMX6CLK_PERIPH);
else if (rnode->sysctl_num == sc->sc_sysctlnode_ipg)
value = imx6_get_clock(IMX6CLK_IPG);
else if (rnode->sysctl_num == sc->sc_sysctlnode_axi)
value = imx6_get_clock(IMX6CLK_AXI);
else
return EOPNOTSUPP;
#ifdef SYSCTL_BY_MHZ
value /= 1000 * 1000; /* Hz -> MHz */
#endif
ovalue = value;
node.sysctl_data = &value;
err = sysctl_lookup(SYSCTLFN_CALL(&node));
if (err != 0 || newp == NULL)
return err;
/* for sysctl write */
if (value == ovalue)
return 0;
#ifdef SYSCTL_BY_MHZ
value *= 1000 * 1000; /* MHz -> Hz */
#endif
if (rnode->sysctl_num == sc->sc_sysctlnode_arm)
return imx6_set_clock(IMX6CLK_ARM_ROOT, value);
return 0;
}
uint32_t
imx6_ccm_read(uint32_t reg)
{
if (ccm_softc == NULL)
return 0;
return bus_space_read_4(ccm_softc->sc_iot, ccm_softc->sc_ioh, reg);
}
void
imx6_ccm_write(uint32_t reg, uint32_t val)
{
if (ccm_softc == NULL)
return;
bus_space_write_4(ccm_softc->sc_iot, ccm_softc->sc_ioh, reg, val);
}
int
imx6_set_clock(enum imx6_clock clk, uint32_t freq)
{
uint32_t v;
if (ccm_softc == NULL)
return 0;
switch (clk) {
case IMX6CLK_ARM_ROOT:
{
uint32_t pll;
int cacrr;
for (cacrr = 7; cacrr >= 0; cacrr--) {
pll = (uint64_t)freq * (cacrr + 1) * 2 / IMX6_OSC_FREQ;
if (pll >= 54 && pll <= 108) {
v = imx6_ccm_read(CCM_CACRR);
v &= ~CCM_CACRR_ARM_PODF;
imx6_ccm_write(CCM_CACRR, v | __SHIFTIN(cacrr, CCM_CACRR_ARM_PODF));
v = imx6_ccm_read(CCM_ANALOG_PLL_ARM);
v &= ~CCM_ANALOG_PLL_ARM_DIV_SELECT;
imx6_ccm_write(CCM_ANALOG_PLL_ARM, v | __SHIFTIN(pll, CCM_ANALOG_PLL_ARM_DIV_SELECT));
cpufreq_set_all(imx6_get_clock(IMX6CLK_ARM_ROOT));
return 0;
}
}
return EINVAL;
}
break;
default:
aprint_error_dev(ccm_softc->sc_dev,
"clock %d: not supported yet\n", clk);
return EINVAL;
}
return 0;
}
uint32_t
imx6_get_clock(enum imx6_clock clk)
{
uint32_t d, denom, num, sel, v;
uint64_t freq;
if (ccm_softc == NULL)
return 0;
switch (clk) {
/* CLOCK SWITCHER */
case IMX6CLK_PLL1:
v = imx6_ccm_read(CCM_ANALOG_PLL_ARM);
freq = IMX6_OSC_FREQ * (v & CCM_ANALOG_PLL_ARM_DIV_SELECT) / 2;
break;
case IMX6CLK_PLL2:
v = imx6_ccm_read(CCM_ANALOG_PLL_SYS);
freq = IMX6_OSC_FREQ * ((v & CCM_ANALOG_PLL_SYS_DIV_SELECT) ? 22 : 20);
break;
case IMX6CLK_PLL3:
v = imx6_ccm_read(CCM_ANALOG_PLL_USB1);
freq = IMX6_OSC_FREQ * ((v & CCM_ANALOG_PLL_USB1_DIV_SELECT) ? 22 : 20);
break;
case IMX6CLK_PLL4:
v = imx6_ccm_read(CCM_ANALOG_PLL_AUDIO);
d = __SHIFTOUT(v, CCM_ANALOG_PLL_AUDIO_DIV_SELECT);
num = imx6_ccm_read(CCM_ANALOG_PLL_AUDIO_NUM);
denom = imx6_ccm_read(CCM_ANALOG_PLL_AUDIO_DENOM);
freq = (uint64_t)IMX6_OSC_FREQ * (d + num / denom);
d = __SHIFTOUT(v, CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT);
freq = freq >> (2 - d);
break;
case IMX6CLK_PLL5:
v = imx6_ccm_read(CCM_ANALOG_PLL_VIDEO);
d = __SHIFTOUT(v, CCM_ANALOG_PLL_VIDEO_DIV_SELECT);
num = imx6_ccm_read(CCM_ANALOG_PLL_VIDEO_NUM);
denom = imx6_ccm_read(CCM_ANALOG_PLL_VIDEO_DENOM);
freq = (uint64_t)IMX6_OSC_FREQ * (d + num / denom);
d = __SHIFTOUT(v, CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT);
freq = freq >> (2 - d);
break;
case IMX6CLK_PLL6:
v = imx6_ccm_read(CCM_ANALOG_PLL_ENET);
switch (v & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK) {
case 0:
freq = 25 * 1000 * 1000;
break;
case 1:
freq = 50 * 1000 * 1000;
break;
case 2:
freq = 100 * 1000 * 1000;
break;
case 3:
freq = 125 * 1000 * 1000;
break;
}
break;
case IMX6CLK_PLL7:
v = imx6_ccm_read(CCM_ANALOG_PLL_USB2);
freq = IMX6_OSC_FREQ * ((v & CCM_ANALOG_PLL_USBn_DIV_SELECT(1)) ? 22 : 20);
break;
#if 0
case IMX6CLK_PLL8:
/* XXX notyet */
break;
#endif
case IMX6CLK_PLL2_PFD0:
freq = imx6_get_clock(IMX6CLK_PLL2);
v = imx6_ccm_read(CCM_ANALOG_PFD_528);
freq = freq * 18 / __SHIFTOUT(v, CCM_ANALOG_PFD_528_PFD0_FRAC);
break;
case IMX6CLK_PLL2_PFD1:
freq = imx6_get_clock(IMX6CLK_PLL2);
v = imx6_ccm_read(CCM_ANALOG_PFD_528);
freq = freq * 18 / __SHIFTOUT(v, CCM_ANALOG_PFD_528_PFD1_FRAC);
break;
case IMX6CLK_PLL2_PFD2:
freq = imx6_get_clock(IMX6CLK_PLL2);
v = imx6_ccm_read(CCM_ANALOG_PFD_528);
freq = freq * 18 / __SHIFTOUT(v, CCM_ANALOG_PFD_528_PFD2_FRAC);
break;
case IMX6CLK_PLL3_PFD3:
freq = imx6_get_clock(IMX6CLK_PLL3);
v = imx6_ccm_read(CCM_ANALOG_PFD_480);
freq = freq * 18 / __SHIFTOUT(v, CCM_ANALOG_PFD_480_PFD3_FRAC);
break;
case IMX6CLK_PLL3_PFD2:
freq = imx6_get_clock(IMX6CLK_PLL3);
v = imx6_ccm_read(CCM_ANALOG_PFD_480);
freq = freq * 18 / __SHIFTOUT(v, CCM_ANALOG_PFD_480_PFD2_FRAC);
break;
case IMX6CLK_PLL3_PFD1:
freq = imx6_get_clock(IMX6CLK_PLL3);
v = imx6_ccm_read(CCM_ANALOG_PFD_480);
freq = freq * 18 / __SHIFTOUT(v, CCM_ANALOG_PFD_480_PFD1_FRAC);
break;
case IMX6CLK_PLL3_PFD0:
freq = imx6_get_clock(IMX6CLK_PLL3);
v = imx6_ccm_read(CCM_ANALOG_PFD_480);
freq = freq * 18 / __SHIFTOUT(v, CCM_ANALOG_PFD_480_PFD0_FRAC);
break;
/* CLOCK ROOT GEN */
case IMX6CLK_ARM_ROOT:
freq = imx6_get_clock(IMX6CLK_PLL1);
v = __SHIFTOUT(imx6_ccm_read(CCM_CACRR), CCM_CACRR_ARM_PODF);
freq = freq / (v + 1);
break;
case IMX6CLK_PERIPH:
v = imx6_ccm_read(CCM_CBCDR);
if (v & CCM_CBCDR_PERIPH_CLK_SEL) {
v = imx6_ccm_read(CCM_CBCMR);
sel = __SHIFTOUT(v, CCM_CBCMR_PERIPH_CLK2_SEL);
switch (sel) {
case 0:
freq = imx6_get_clock(IMX6CLK_PLL3);
break;
case 1:
case 2:
freq = IMX6_OSC_FREQ;
break;
case 3:
freq = 0;
aprint_error_dev(ccm_softc->sc_dev,
"IMX6CLK_PERIPH: CCM_CBCMR:CCM_CBCMR_PERIPH_CLK2_SEL is set reserved value\n");
break;
}
} else {
v = imx6_ccm_read(CCM_CBCMR);
sel = __SHIFTOUT(v, CCM_CBCMR_PRE_PERIPH_CLK_SEL);
switch (sel) {
case 0:
freq = imx6_get_clock(IMX6CLK_PLL2);
break;
case 1:
freq = imx6_get_clock(IMX6CLK_PLL2_PFD2);
break;
case 2:
freq = imx6_get_clock(IMX6CLK_PLL2_PFD0);
break;
case 3:
freq = imx6_get_clock(IMX6CLK_PLL2_PFD2) / 2;
break;
}
}
break;
case IMX6CLK_AHB:
freq = imx6_get_clock(IMX6CLK_PERIPH);
v = imx6_ccm_read(CCM_CBCDR);
freq = freq / (__SHIFTOUT(v, CCM_CBCDR_AHB_PODF) + 1);
break;
case IMX6CLK_IPG:
freq = imx6_get_clock(IMX6CLK_AHB);
v = imx6_ccm_read(CCM_CBCDR);
freq = freq / (__SHIFTOUT(v, CCM_CBCDR_IPG_PODF) + 1);
break;
case IMX6CLK_AXI:
v = imx6_ccm_read(CCM_CBCDR);
if (v & CCM_CBCDR_AXI_SEL) {
if (v & CCM_CBCDR_AXI_ALT_SEL) {
freq = imx6_get_clock(IMX6CLK_PLL2_PFD2);
} else {
freq = imx6_get_clock(IMX6CLK_PLL3_PFD1);
}
} else {
freq = imx6_get_clock(IMX6CLK_PERIPH);
freq = freq / (__SHIFTOUT(v, CCM_CBCDR_AXI_PODF) + 1);
}
break;
case IMX6CLK_USDHC1_CLK_ROOT:
v = imx6_ccm_read(CCM_CSCMR1);
freq = imx6_get_clock((v & CCM_CSCMR1_USDHC1_CLK_SEL) ?
IMX6CLK_PLL2_PFD0 : IMX6CLK_PLL2_PFD2);
v = imx6_ccm_read(CCM_CSCDR1);
freq = freq / (__SHIFTOUT(v, CCM_CSCDR1_USDHC1_PODF) + 1);
break;
case IMX6CLK_USDHC2_CLK_ROOT:
v = imx6_ccm_read(CCM_CSCMR1);
freq = imx6_get_clock((v & CCM_CSCMR1_USDHC2_CLK_SEL) ?
IMX6CLK_PLL2_PFD0 : IMX6CLK_PLL2_PFD2);
v = imx6_ccm_read(CCM_CSCDR1);
freq = freq / (__SHIFTOUT(v, CCM_CSCDR1_USDHC2_PODF) + 1);
break;
case IMX6CLK_USDHC3_CLK_ROOT:
v = imx6_ccm_read(CCM_CSCMR1);
freq = imx6_get_clock((v & CCM_CSCMR1_USDHC3_CLK_SEL) ?
IMX6CLK_PLL2_PFD0 : IMX6CLK_PLL2_PFD2);
v = imx6_ccm_read(CCM_CSCDR1);
freq = freq / (__SHIFTOUT(v, CCM_CSCDR1_USDHC3_PODF) + 1);
break;
case IMX6CLK_USDHC4_CLK_ROOT:
v = imx6_ccm_read(CCM_CSCMR1);
freq = imx6_get_clock((v & CCM_CSCMR1_USDHC4_CLK_SEL) ?
IMX6CLK_PLL2_PFD0 : IMX6CLK_PLL2_PFD2);
v = imx6_ccm_read(CCM_CSCDR1);
freq = freq / (__SHIFTOUT(v, CCM_CSCDR1_USDHC4_PODF) + 1);
break;
default:
aprint_error_dev(ccm_softc->sc_dev,
"clock %d: not supported yet\n", clk);
return 0;
}
return freq;
}
int
imx6_pll_power(uint32_t pllreg, int on)
{
uint32_t v;
int timeout;
switch (pllreg) {
case CCM_ANALOG_PLL_USB1:
case CCM_ANALOG_PLL_USB2:
v = imx6_ccm_read(pllreg);
if (on) {
v |= CCM_ANALOG_PLL_USBn_ENABLE;
v &= ~CCM_ANALOG_PLL_USBn_BYPASS;
} else {
v &= ~CCM_ANALOG_PLL_USBn_ENABLE;
}
imx6_ccm_write(pllreg, v);
return 0;
case CCM_ANALOG_PLL_ENET:
v = imx6_ccm_read(pllreg);
if (on)
v &= ~CCM_ANALOG_PLL_ENET_POWERDOWN;
else
v |= CCM_ANALOG_PLL_ENET_POWERDOWN;
imx6_ccm_write(pllreg, v);
for (timeout = 100000; timeout > 0; timeout--) {
if (imx6_ccm_read(pllreg) &
CCM_ANALOG_PLL_ENET_LOCK)
break;
}
if (timeout <= 0)
break;
if (on) {
v &= ~CCM_ANALOG_PLL_ENET_BYPASS;
v |= CCM_ANALOG_PLL_ENET_ENABLE;
} else {
v &= ~CCM_ANALOG_PLL_ENET_ENABLE;
}
imx6_ccm_write(pllreg, v);
return 0;
case CCM_ANALOG_PLL_ARM:
case CCM_ANALOG_PLL_SYS:
case CCM_ANALOG_PLL_AUDIO:
case CCM_ANALOG_PLL_VIDEO:
case CCM_ANALOG_PLL_MLB:
/* notyet */
default:
break;
}
return -1;
}

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/* $NetBSD: imx6_ccmreg.h,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_IMX_IMX6_CCMREG_H
#define _ARM_IMX_IMX6_CCMREG_H
#include <sys/cdefs.h>
#define IMX6_CCM_SIZE 0x8000
/* 0x00000000 = 0x020c4000 */
#define CCM_CCR 0x00000000
#define CCM_CCDR 0x00000004
#define CCM_CSR 0x00000008
#define CCM_CCSR 0x0000000c
#define CCM_CACRR 0x00000010
#define CCM_CACRR_ARM_PODF __BITS(2, 0)
#define CCM_CBCDR 0x00000014
#define CCM_CBCDR_PERIPH_CLK2_PODF __BITS(29, 27)
/* source of mmdc_ch1_axi_clk_root */
#define CCM_CBCDR_PERIPH2_CLK_SEL __BIT(26)
/* source of mmdc_ch0_axi_clk_root */
#define CCM_CBCDR_PERIPH_CLK_SEL __BIT(25)
#define CCM_CBCDR_MMDC_CH0_AXI_PODF __BITS(21, 19)
#define CCM_CBCDR_AXI_PODF __BITS(18, 16)
#define CCM_CBCDR_AHB_PODF __BITS(12, 10)
#define CCM_CBCDR_IPG_PODF __BITS(9, 8)
#define CCM_CBCDR_AXI_ALT_SEL __BIT(7)
#define CCM_CBCDR_AXI_SEL __BIT(6)
#define CCM_CBCDR_MMDC_CH1_AXI_PODF __BITS(5, 3)
#define CCM_CBCDR_PERIPH2_CLK2_PODF __BITS(2, 0)
#define CCM_CBCMR 0x00000018
#define CCM_CBCMR_GPU3D_SHADER_PODF __BITS(31, 29)
#define CCM_CBCMR_GPU3D_CORE_PODF __BITS(28, 26)
#define CCM_CBCMR_GPU2D_CORE_CLK_PODF __BITS(25, 23)
#define CCM_CBCMR_PRE_PERIPH2_CLK_SEL __BITS(22, 21)
#define CCM_CBCMR_PERIPH2_CLK2_SEL __BIT(20)
#define CCM_CBCMR_PRE_PERIPH_CLK_SEL __BITS(19, 18)
#define CCM_CBCMR_GPU2D_CLK_SEL __BITS(17, 16)
#define CCM_CBCMR_VPU_AXI_CLK_SEL __BITS(15, 14)
#define CCM_CBCMR_PERIPH_CLK2_SEL __BITS(13, 12)
#define CCM_CBCMR_VDOAXI_CLK_SEL __BIT(11)
#define CCM_CBCMR_PCIE_AXI_CLK_SE __BIT(10)
#define CCM_CBCMR_GPU3D_SHADER_CLK_SEL __BITS(9, 8)
#define CCM_CBCMR_GPU3D_CORE_CLK_SEL __BITS(5, 4)
#define CCM_CBCMR_GPU3D_AXI_CLK_SEL __BIT(1)
#define CCM_CBCMR_GPU2D_AXI_CLK_SEL __BIT(0)
#define CCM_CSCMR1 0x0000001c
#define CCM_CSCMR1_ACLK_EIM_SLOW_SEL __BITS(30, 29)
#define CCM_CSCMR1_ACLK_SEL __BITS(28, 27)
#define CCM_CSCMR1_ACLK_EIM_SLOW_PODF __BITS(25, 23)
#define CCM_CSCMR1_ACLK_PODF __BITS(22, 20)
#define CCM_CSCMR1_USDHC4_CLK_SEL __BIT(19)
#define CCM_CSCMR1_USDHC3_CLK_SEL __BIT(18)
#define CCM_CSCMR1_USDHC2_CLK_SEL __BIT(17)
#define CCM_CSCMR1_USDHC1_CLK_SEL __BIT(16)
#define CCM_CSCMR1_SSI3_CLK_SEL __BITS(15, 14)
#define CCM_CSCMR1_SSI2_CLK_SEL __BITS(13, 12)
#define CCM_CSCMR1_SSI1_CLK_SEL __BITS(11, 10)
#define CCM_CSCMR1_PERCLK_PODF __BITS(5, 0)
#define CCM_CSCDR1 0x00000024
#define CCM_CSCDR1_VPU_AXI_PODF __BITS(25, 27)
#define CCM_CSCDR1_USDHC4_PODF __BITS(22, 24)
#define CCM_CSCDR1_USDHC3_PODF __BITS(19, 21)
#define CCM_CSCDR1_USDHC2_PODF __BITS(16, 18)
#define CCM_CSCDR1_USDHC1_PODF __BITS(13, 11)
#define CCM_CSCDR1_UART_CLK_PODF __BITS(5, 0)
#define CCM_CCGR5 0x0000007c
#define CCM_CCGR5_UART_SERIAL_CLK_ENABLE(n) __SHIFTIN(n, __BITS(27, 26))
#define CCM_CCGR5_UART_CLK_ENABLE(n) __SHIFTIN(n, __BITS(25, 24))
#define CCM_CCGR5_SSI3_CLK_ENABLE(n) __SHIFTIN(n, __BITS(23, 22))
#define CCM_CCGR5_SSI2_CLK_ENABLE(n) __SHIFTIN(n, __BITS(21, 20))
#define CCM_CCGR5_SSI1_CLK_ENABLE(n) __SHIFTIN(n, __BITS(19, 18))
#define CCM_CCGR5_SPDIF_CLK_ENABLE(n) __SHIFTIN(n, __BITS(15, 14))
#define CCM_CCGR5_SPBA_CLK_ENABLE(n) __SHIFTIN(n, __BITS(13, 12))
#define CCM_CCGR5_SDMA_CLK_ENABLE(n) __SHIFTIN(n, __BITS(7, 6))
#define CCM_CCGR5_100M_CLK_ENABLE(n) __SHIFTIN(n, __BITS(5, 4))
#define CCM_CCGR5_ROM_CLK_ENABLE(n) __SHIFTIN(n, __BITS(1, 0))
#define CCM_CCGR6 0x00000080
#define CCM_CCGR6_VPU_CLK_ENABLE(n) __SHIFTIN(n, __BITS(15, 14))
#define CCM_CCGR6_VDOAXICLK_CLK_ENABLE(n) __SHIFTIN(n, __BITS(13, 12))
#define CCM_CCGR6_EIM_SLOW_CLK_ENABLE(n) __SHIFTIN(n, __BITS(11, 10))
#define CCM_CCGR6_USDHC4_CLK_ENABLE(n) __SHIFTIN(n, __BITS(9, 8))
#define CCM_CCGR6_USDHC3_CLK_ENABLE(n) __SHIFTIN(n, __BITS(7, 6))
#define CCM_CCGR6_USDHC2_CLK_ENABLE(n) __SHIFTIN(n, __BITS(5, 4))
#define CCM_CCGR6_USDHC1_CLK_ENABLE(n) __SHIFTIN(n, __BITS(3, 2))
#define CCM_CCGR6_USBOH3_CLK_ENABLE(n) __SHIFTIN(n, __BITS(1, 0))
/* 0x00004000 = 0x020c8000 */
#define CCM_ANALOG_PLL_ARM 0x00004000 /* = 020c8000 */
#define CCM_ANALOG_PLL_ARM_SET 0x00004004
#define CCM_ANALOG_PLL_ARM_CLR 0x00004008
#define CCM_ANALOG_PLL_ARM_TOG 0x0000400c
#define CCM_ANALOG_PLL_ARM_DIV_SELECT __BITS(6, 0)
#define CCM_ANALOG_PLL_USB1 0x00004010
#define CCM_ANALOG_PLL_USB1_SET 0x00004014
#define CCM_ANALOG_PLL_USB1_CLR 0x00004018
#define CCM_ANALOG_PLL_USB1_TOG 0x0000401c
#define CCM_ANALOG_PLL_USB1_DIV_SELECT __BITS(1, 0)
#define CCM_ANALOG_PLL_USB2 0x00004020
#define CCM_ANALOG_PLL_USB2_SET 0x00004024
#define CCM_ANALOG_PLL_USB2_CLR 0x00004028
#define CCM_ANALOG_PLL_USB2_TOG 0x0000402c
#define CCM_ANALOG_PLL_USBn_LOCK __BIT(31)
#define CCM_ANALOG_PLL_USBn_BYPASS __BIT(16)
#define CCM_ANALOG_PLL_USBn_ENABLE __BIT(13)
#define CCM_ANALOG_PLL_USBn_POWER __BIT(12)
#define CCM_ANALOG_PLL_USBn_EN_USB_CLK __BIT(6)
#define CCM_ANALOG_PLL_USBn_DIV_SELECT(n) __BITS(1, 0)
#define CCM_ANALOG_PLL_SYS 0x00004030
#define CCM_ANALOG_PLL_SYS_SET 0x00004034
#define CCM_ANALOG_PLL_SYS_CLR 0x00004038
#define CCM_ANALOG_PLL_SYS_TOG 0x0000403c
#define CCM_ANALOG_PLL_SYS_DIV_SELECT __BIT(0)
#define CCM_ANALOG_PLL_SYS_SS 0x00004040
#define CCM_ANALOG_PLL_SYS_NUM 0x00004050
#define CCM_ANALOG_PLL_SYS_DENOM 0x00004060
#define CCM_ANALOG_PLL_AUDIO 0x00004070
#define CCM_ANALOG_PLL_AUDIO_SET 0x00004074
#define CCM_ANALOG_PLL_AUDIO_CLR 0x00004078
#define CCM_ANALOG_PLL_AUDIO_TOG 0x0000407c
#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT __BITS(20, 19)
#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT __BITS(6, 0)
#define CCM_ANALOG_PLL_AUDIO_NUM 0x00004080
#define CCM_ANALOG_PLL_AUDIO_DENOM 0x00004090
#define CCM_ANALOG_PLL_VIDEO 0x000040a0
#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT __BITS(20, 19)
#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT __BITS(6, 0)
#define CCM_ANALOG_PLL_VIDEO_SET 0x000040a4
#define CCM_ANALOG_PLL_VIDEO_CLR 0x000040a8
#define CCM_ANALOG_PLL_VIDEO_TOG 0x000040ac
#define CCM_ANALOG_PLL_VIDEO_NUM 0x000040b0
#define CCM_ANALOG_PLL_VIDEO_DENOM 0x000040c0
#define CCM_ANALOG_PLL_MLB 0x000040d0
#define CCM_ANALOG_PLL_MLB_SET 0x000040d4
#define CCM_ANALOG_PLL_MLB_CLR 0x000040d8
#define CCM_ANALOG_PLL_MLB_TOG 0x000040dc
#define CCM_ANALOG_PLL_ENET 0x000040e0
#define CCM_ANALOG_PLL_ENET_SET 0x000040e4
#define CCM_ANALOG_PLL_ENET_CLR 0x000040e8
#define CCM_ANALOG_PLL_ENET_TOG 0x000040ec
#define CCM_ANALOG_PLL_ENET_LOCK __BIT(31)
#define CCM_ANALOG_PLL_ENET_ENABLE_100M __BIT(20) /* SATA */
#define CCM_ANALOG_PLL_ENET_ENABLE_125M __BIT(19) /* PCIe */
#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN __BIT(18)
#define CCM_ANALOG_PLL_ENET_BYPASS __BIT(16)
#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(s) __SHIFTIN(s, __BITS(15, 14))
#define CCM_ANALOG_PLL_ENET_ENABLE __BIT(13) /* Ether */
#define CCM_ANALOG_PLL_ENET_POWERDOWN __BIT(12)
#define CCM_ANALOG_PLL_ENET_DIV_SELECT(d) __SHIFTIN(d, __BITS(1, 0))
#define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK __SHIFTIN(3, __BITS(1, 0))
#define CCM_ANALOG_PFD_480 0x000040f0
#define CCM_ANALOG_PFD_480_SET 0x000040f4
#define CCM_ANALOG_PFD_480_CLR 0x000040f8
#define CCM_ANALOG_PFD_480_TOG 0x000040fc
#define CCM_ANALOG_PFD_480_PFD3_CLKGATE __BIT(31)
#define CCM_ANALOG_PFD_480_PFD3_STABLE __BIT(30)
#define CCM_ANALOG_PFD_480_PFD3_FRAC __BITS(29, 24)
#define CCM_ANALOG_PFD_480_PFD2_CLKGATE __BIT(23)
#define CCM_ANALOG_PFD_480_PFD2_STABLE __BIT(22)
#define CCM_ANALOG_PFD_480_PFD2_FRAC __BITS(21, 16)
#define CCM_ANALOG_PFD_480_PFD1_CLKGATE __BIT(15)
#define CCM_ANALOG_PFD_480_PFD1_STABLE __BIT(14)
#define CCM_ANALOG_PFD_480_PFD1_FRAC __BITS(13, 8)
#define CCM_ANALOG_PFD_480_PFD0_CLKGATE __BIT(7)
#define CCM_ANALOG_PFD_480_PFD0_STABLE __BIT(6)
#define CCM_ANALOG_PFD_480_PFD0_FRAC __BITS(5, 0)
#define CCM_ANALOG_PFD_528 0x00004100
#define CCM_ANALOG_PFD_528_SET 0x00004104
#define CCM_ANALOG_PFD_528_CLR 0x00004108
#define CCM_ANALOG_PFD_528_TOG 0x0000410c
#define CCM_ANALOG_PFD_528_PFD2_CLKGATE __BIT(23)
#define CCM_ANALOG_PFD_528_PFD2_STABLE __BIT(22)
#define CCM_ANALOG_PFD_528_PFD2_FRAC __BITS(21, 16)
#define CCM_ANALOG_PFD_528_PFD1_CLKGATE __BIT(15)
#define CCM_ANALOG_PFD_528_PFD1_STABLE __BIT(14)
#define CCM_ANALOG_PFD_528_PFD1_FRAC __BITS(13, 8)
#define CCM_ANALOG_PFD_528_PFD0_CLKGATE __BIT(7)
#define CCM_ANALOG_PFD_528_PFD0_STABLE __BIT(6)
#define CCM_ANALOG_PFD_528_PFD0_FRAC __BITS(5, 0)
#define CCM_ANALOG_MISC0 0x00004150
#define CCM_ANALOG_MISC0_SET 0x00004154
#define CCM_ANALOG_MISC0_CLR 0x00004158
#define CCM_ANALOG_MISC0_TOG 0x0000415C
#define CCM_ANALOG_MISC2 0x00004170
#define CCM_ANALOG_MISC2_SET 0x00004174
#define CCM_ANALOG_MISC2_CLR 0x00004178
#define CCM_ANALOG_MISC2_TOG 0x0000417C
#define CCM_TEMPMON_TEMPSENSE0 0x00004180
#define CCM_TEMPMON_TEMPSENSE0_ALARM_VALUE __BIT(31, 30)
#define CCM_TEMPMON_TEMPSENSE0_TEMP_CNT __BITS(19, 8)
#define CCM_TEMPMON_TEMPSENSE0_FINISHED __BIT(2)
#define CCM_TEMPMON_TEMPSENSE0_MEASURE_TEMP __BIT(1)
#define CCM_TEMPMON_TEMPSENSE0_POWER_DOWN __BIT(0)
#define CCM_TEMPMON_TEMPSENSE1 0x00004180
#define CCM_TEMPMON_TEMPSENSE1_MEASURE_FREQ __BITS(15, 0)
#define USB_ANALOG_USB1_VBUS_DETECT 0x000041a0
#define USB_ANALOG_USB1_CHRG_DETECT 0x000041b0
#define USB_ANALOG_USB_CHRG_DETECT_EN_B __BIT(20)
#define USB_ANALOG_USB_CHRG_DETECT_CHK_CHRG_B __BIT(19)
#define USB_ANALOG_USB_CHRG_DETECT_CHK_CHK_CONTACT __BIT(18)
#define USB_ANALOG_USB1_VBUS_DETECT_STAT 0x000041c0
#define USB_ANALOG_USB1_CHRG_DETECT_STAT 0x000041d0
#define USB_ANALOG_USB1_MISC 0x000041f0
#define USB_ANALOG_USB2_VBUS_DETECT 0x00004200
#define USB_ANALOG_USB2_CHRG_DETECT 0x00004210
#define USB_ANALOG_USB2_VBUS_DETECT_STAT 0x00004220
#define USB_ANALOG_USB2_CHRG_DETECT_STAT 0x00004230
#define USB_ANALOG_USB2_MISC 0x00004250
#define USB_ANALOG_DIGPROG 0x00004260
/* 0x00005000 = 0x020c9000 */
#define USBPHY1_PWD 0x00005000 /* = 020c9000 */
#define USBPHY1_PWD_SET 0x00005004
#define USBPHY1_PWD_CLR 0x00005008
#define USBPHY1_PWD_TOG 0x0000500c
#define USBPHY1_TX 0x00005010
#define USBPHY1_TX_SET 0x00005014
#define USBPHY1_TX_CLR 0x00005018
#define USBPHY1_TX_TOG 0x0000501c
#define USBPHY_TX_USBPHY_TX_EDGECTRL __BITS(28, 26)
#define USBPHY_TX_TXCAL45DP __BITS(19, 16)
#define USBPHY_TX_TXCAL45DN __BITS(11, 8)
#define USBPHY_TX_D_CAL __BITS(3, 0)
#define USBPHY1_RX 0x00005020
#define USBPHY1_RX_SET 0x00005024
#define USBPHY1_RX_CLR 0x00005028
#define USBPHY1_RX_TOG 0x0000502c
#define USBPHY1_CTRL 0x00005030
#define USBPHY1_CTRL_SET 0x00005034
#define USBPHY1_CTRL_CLR 0x00005038
#define USBPHY1_CTRL_TOG 0x0000503c
#define USBPHY_CTRL_SFTRST __BIT(31)
#define USBPHY_CTRL_CLKGATE __BIT(30)
#define USBPHY_CTRL_ENUTMILEVEL3 __BIT(15)
#define USBPHY_CTRL_ENUTMILEVEL2 __BIT(14)
#define USBPHY1_STATUS 0x00005040
#define USBPHY1_DEBUG 0x00005050
#define USBPHY1_DEBUG0_STATUS 0x00005060
#define USBPHY1_DEBUG1 0x00005070
#define USBPHY1_VERSION 0x00005080
#define USBPHY2_PWD 0x00006000 /* = 020ca000 */
#define USBPHY2_PWD_SET 0x00006004
#define USBPHY2_PWD_CLR 0x00006008
#define USBPHY2_PWD_TOG 0x0000600c
#define USBPHY2_TX 0x00006010
#define USBPHY2_TX_SET 0x00006014
#define USBPHY2_TX_CLR 0x00006018
#define USBPHY2_TX_TOG 0x0000601c
#define USBPHY2_RX 0x00006020
#define USBPHY2_RX_SET 0x00006024
#define USBPHY2_RX_CLR 0x00006028
#define USBPHY2_RX_TOG 0x0000602c
#define USBPHY2_CTRL 0x00006030
#define USBPHY2_CTRL_SET 0x00006034
#define USBPHY2_CTRL_CLR 0x00006038
#define USBPHY2_CTRL_TOG 0x0000603c
#define USBPHY2_STATUS 0x00006040
#define USBPHY2_DEBUG 0x00006050
#define USBPHY2_DEBUG0_STATUS 0x00006060
#define USBPHY2_DEBUG1 0x00006070
#define USBPHY2_VERSION 0x00006080
#endif /* _ARM_IMX_IMX6_CCMREG_H */

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/* $NetBSD: imx6_ccmvar.h,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*
* Copyright (c) 2012 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_IMX_IMX6_CCMVAR_H_
#define _ARM_IMX_IMX6_CCMVAR_H_
enum imx6_clock {
IMX6CLK_PLL1, /* = PLL_ARM */
IMX6CLK_PLL2, /* = PLL_SYS = 528_PLL (24MHz * 22) */
IMX6CLK_PLL3, /* = PLL_USB1 = 480_PLL1 */
/* (USB/OTG PHY, 480PFD0-480PFD3, 24MHz*20) */
IMX6CLK_PLL4, /* = PLL_AUDIO */
IMX6CLK_PLL5, /* = PLL_VIDEO */
IMX6CLK_PLL6, /* = PLL_ENET (20MHz = 24MHz * 5/6) */
IMX6CLK_PLL7, /* = PLL_USB2 (USB2 PHY, HOST PHY, 24MHz*20) */
IMX6CLK_PLL8, /* = PLL_MLB (Media Link Bus) */
IMX6CLK_PLL2_PFD0,
IMX6CLK_PLL2_PFD1,
IMX6CLK_PLL2_PFD2,
IMX6CLK_PLL3_PFD0,
IMX6CLK_PLL3_PFD1,
IMX6CLK_PLL3_PFD2,
IMX6CLK_PLL3_PFD3,
IMX6CLK_ARM_ROOT, /* CPU clock of ARM core */
IMX6CLK_PERIPH,
IMX6CLK_AHB,
IMX6CLK_IPG,
IMX6CLK_AXI,
IMX6CLK_MMDC_CH0,
IMX6CLK_MMDC_CH1,
IMX6CLK_USDHC1_CLK_ROOT,
IMX6CLK_USDHC2_CLK_ROOT,
IMX6CLK_USDHC3_CLK_ROOT,
IMX6CLK_USDHC4_CLK_ROOT,
};
uint32_t imx6_get_clock(enum imx6_clock);
int imx6_set_clock(enum imx6_clock, uint32_t);
int imx6_pll_power(uint32_t, int);
uint32_t imx6_ccm_read(uint32_t);
void imx6_ccm_write(uint32_t, uint32_t);
#endif /* _ARM_IMX_IMX6_CCMVAR_H_ */

131
sys/arch/arm/imx/imx6_clock.c Normal file
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@ -0,0 +1,131 @@
/* $NetBSD: imx6_clock.c,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*
* Copyright (c) 2009 Genetec corp. All rights reserved.
* Written by Hashimoto Kenichi for Genetec corp.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP.
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: imx6_clock.c,v 1.1 2014/09/25 05:05:28 ryo Exp $");
#include "opt_imx.h"
#include "opt_imx6clk.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/evcnt.h>
#include <sys/atomic.h>
#include <sys/time.h>
#include <sys/timetc.h>
#include <sys/types.h>
#include <sys/device.h>
#include <dev/clock_subr.h>
#include <machine/intr.h>
#include <sys/bus.h>
#include <arm/cpufunc.h>
#include <arm/imx/imx6_reg.h>
#include <arm/imx/imx6var.h>
#include <arm/imx/imxepitreg.h>
#include <arm/imx/imx6_ccmvar.h>
#include <arm/imx/imxclockvar.h>
#include "locators.h"
#include "imxccm.h" /* if CCM driver is configured into the kernel */
static int imxclock_match(device_t, struct cfdata *, void *);
static void imxclock_attach(device_t, device_t, void *);
struct imxclock_softc *epit1_sc = NULL;
struct imxclock_softc *epit2_sc = NULL;
CFATTACH_DECL_NEW(imxclock, sizeof(struct imxclock_softc),
imxclock_match, imxclock_attach, NULL, NULL);
static int
imxclock_match(device_t parent, struct cfdata *match, void *aux)
{
struct axi_attach_args *aa = aux;
if ( (aa->aa_addr != IMX6_AIPS1_BASE + AIPS1_EPIT1_BASE) &&
(aa->aa_addr != IMX6_AIPS1_BASE + AIPS1_EPIT2_BASE) ) {
return 0;
}
return 2;
}
static void
imxclock_attach(device_t parent, device_t self, void *aux)
{
struct imxclock_softc *sc = device_private(self);
struct axi_attach_args *aa = aux;
aprint_normal("\n");
sc->sc_dev = self;
sc->sc_iot = aa->aa_iot;
sc->sc_intr = aa->aa_irq;
if (aa->aa_size == AXICF_SIZE_DEFAULT)
aa->aa_size = AIPS1_EPIT_SIZE;
switch ( aa->aa_addr ) {
case IMX6_AIPS1_BASE + AIPS1_EPIT1_BASE:
epit1_sc = sc;
break;
case IMX6_AIPS1_BASE + AIPS1_EPIT2_BASE:
epit2_sc = sc;
break;
default:
panic("%s: invalid address %p", device_xname(self), (void *)aa->aa_addr);
break;
}
if (bus_space_map(aa->aa_iot, aa->aa_addr, aa->aa_size, 0, &sc->sc_ioh))
panic("%s: Cannot map registers", device_xname(self));
sc->sc_clksrc = EPITCR_CLKSRC_IPG;
}
int
imxclock_get_timerfreq(struct imxclock_softc *sc)
{
unsigned int ipg_freq;
#if NIMXCCM > 0
ipg_freq = imx6_get_clock(IMX6CLK_IPG);
#else
#ifndef IMX6_IPGCLK_FREQ
#error IMX6_IPGCLK_FREQ need to be defined.
#endif
ipg_freq = IMX6_IPGCLK_FREQ;
#endif
return ipg_freq;
}

117
sys/arch/arm/imx/imx6_gpio.c Normal file
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@ -0,0 +1,117 @@
/* $NetBSD: imx6_gpio.c,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Matt Thomas
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: imx6_gpio.c,v 1.1 2014/09/25 05:05:28 ryo Exp $");
#include "opt_imx.h"
#include "locators.h"
#include "gpio.h"
#include <sys/param.h>
#include <sys/evcnt.h>
#include <sys/atomic.h>
#include <machine/intr.h>
#include <arm/cpu.h>
#include <arm/armreg.h>
#include <arm/cpufunc.h>
#include <sys/bus.h>
#include <arm/imx/imx6_reg.h>
#include <arm/imx/imx6var.h>
#include <arm/pic/picvar.h>
#include <arm/imx/imxgpioreg.h>
#include <arm/imx/imxgpiovar.h>
#if NGPIO > 0
#include <sys/gpio.h>
#include <dev/gpio/gpiovar.h>
#endif
const int imxgpio_ngroups = GPIO_NGROUPS;
int
imxgpio_match(device_t parent, cfdata_t cfdata, void *aux)
{
struct axi_attach_args *aa = aux;
switch(aa->aa_addr) {
case IMX6_AIPS1_BASE + AIPS1_GPIO1_BASE:
case IMX6_AIPS1_BASE + AIPS1_GPIO2_BASE:
case IMX6_AIPS1_BASE + AIPS1_GPIO3_BASE:
case IMX6_AIPS1_BASE + AIPS1_GPIO4_BASE:
case IMX6_AIPS1_BASE + AIPS1_GPIO5_BASE:
case IMX6_AIPS1_BASE + AIPS1_GPIO6_BASE:
case IMX6_AIPS1_BASE + AIPS1_GPIO7_BASE:
return 1;
}
return 0;
}
void
imxgpio_attach(device_t parent, device_t self, void *aux)
{
struct axi_attach_args * const aa = aux;
bus_space_handle_t ioh;
int error, group;
if (aa->aa_irq == AXICF_IRQ_DEFAULT &&
aa->aa_irqbase != AXICF_IRQBASE_DEFAULT) {
aprint_error_dev(self, "missing intr in config\n");
return;
}
if (aa->aa_irq != AXICF_IRQ_DEFAULT &&
aa->aa_irqbase == AXICF_IRQBASE_DEFAULT) {
aprint_error_dev(self, "missing irqbase in config\n");
return;
}
if (aa->aa_size == AXICF_SIZE_DEFAULT)
aa->aa_size = GPIO_SIZE;
error = bus_space_map(aa->aa_iot, aa->aa_addr, aa->aa_size,
0, &ioh);
if (error) {
aprint_error(": failed to map register %#lx@%#lx: %d\n",
aa->aa_size, aa->aa_addr, error);
return;
}
group = (aa->aa_addr - IMX6_AIPS1_BASE - AIPS1_GPIO1_BASE) / 0x4000;
imxgpio_attach_common(self, aa->aa_iot, ioh, group,
aa->aa_irq, aa->aa_irqbase);
}

44
sys/arch/arm/imx/imx6_intr.h
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@ -1,4 +1,4 @@
/* $NetBSD: imx6_intr.h,v 1.1 2012/09/01 00:07:32 matt Exp $ */
/* $NetBSD: imx6_intr.h,v 1.2 2014/09/25 05:05:28 ryo Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@ -40,26 +40,26 @@
#include <arm/cortex/gic_intr.h>
#include <arm/cortex/a9tmr_intr.h> /* A9 Timer PPIs */
#define IRQ_IOMUXC 32
#define IRQ_DAP 33
#define IRQ_SDMA 34
#define IRQ_VPU_JPEG 35
#define IRQ_SNVS 36
#define IRQ_IPU1_ERROR 37
#define IRQ_IPU1_SYNC 38
#define IRQ_IPU2_ERROR 39
#define IRQ_IPU2_SYNC 40
#define IRQ_GPU3D 41
#define IRQ_GPU2D_IDLE 42
#define IRQ_GPU2D 43
#define IRQ_VPU 44
#define IRQ_APBH 45
#define IRQ_IOMUXC 32
#define IRQ_DAP 33
#define IRQ_SDMA 34
#define IRQ_VPU_JPEG 35
#define IRQ_SNVS_PMIC 36
#define IRQ_IPU1_ERROR 37
#define IRQ_IPU1_SYNC 38
#define IRQ_IPU2_ERROR 39
#define IRQ_IPU2_SYNC 40
#define IRQ_GPU3D 41
#define IRQ_GPU2D_IDLE 42
#define IRQ_GPU2D 43
#define IRQ_VPU 44
#define IRQ_APBH 45
#define IRQ_EIM 46
#define IRQ_BCH 47
#define IRQ_GPMI 48
#define IRQ_GPMI 48
#define IRQ_DTCP 49
#define IRQ_VDOA 50
#define IRQ_SNVS 51
#define IRQ_SNVS 51
#define IRQ_SNVS_SEC 52
#define IRQ_CSU 53
#define IRQ_USDHC1 54
@ -94,7 +94,7 @@
#define IRQ_ESAI 83
#define IRQ_SPDIF 84
#define IRQ_MLB 85
#define IRQ__RSVD86 86
#define IRQ_PMU 86
#define IRQ_GPT 87
#define IRQ_EPIT1 88
#define IRQ_EPIT2 89
@ -152,9 +152,9 @@
#define IRQ_ASC2 141
#define IRQ_FLEXCAN1 142
#define IRQ_FLEXCAN2 143
#define IRQ__RSVD139 144
#define IRQ__RSVD139 145
#define IRQ__RSVD139 146
#define IRQ__RSVD144 144
#define IRQ__RSVD145 145
#define IRQ__RSVD146 146
#define IRQ_HDMI_MASTER 147
#define IRQ_HDMI_CEC 148
#define IRQ_MLB150L 149
@ -167,6 +167,6 @@
#define IRQ_DCIC1 156
#define IRQ_DCIC2 157
#define IRQ_MLB150H 158
#define IRQ_PMU 159
#define IRQ_PMU_D 159
#endif /* _ARM_ARM_IMX6INTR_H_ */

202
sys/arch/arm/imx/imx6_iomux.c Normal file
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@ -0,0 +1,202 @@
/* $NetBSD: imx6_iomux.c,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*
* Copyright (c) 2009, 2010 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: imx6_iomux.c,v 1.1 2014/09/25 05:05:28 ryo Exp $");
#include <sys/bus.h>
#include <sys/device.h>
#include <sys/param.h>
#include <arm/imx/imx6var.h>
#include <arm/imx/imx6_reg.h>
#include <arm/imx/imx6_iomuxreg.h>
#include "locators.h"
struct imxiomux_softc {
device_t sc_dev;
bus_addr_t sc_addr;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_ioh;
};
static struct imxiomux_softc *iomux_softc;
static int imxiomux_match(device_t, struct cfdata *, void *);
static void imxiomux_attach(device_t, device_t, void *);
CFATTACH_DECL_NEW(imxiomux, sizeof(struct imxiomux_softc),
imxiomux_match, imxiomux_attach, NULL, NULL);
/* ARGSUSED */
static int
imxiomux_match(device_t parent __unused, struct cfdata *match __unused, void *aux)
{
struct axi_attach_args *aa;
aa = aux;
if (iomux_softc != NULL)
return 0;
switch (aa->aa_addr) {
case (IMX6_AIPS1_BASE + AIPS1_IOMUXC_BASE):
return 1;
}
return 0;
}
/* ARGSUSED */
static void
imxiomux_attach(device_t parent __unused, device_t self, void *aux)
{
struct imxiomux_softc *sc;
struct axi_attach_args *aa;
aa = aux;
sc = device_private(self);
sc->sc_dev = self;
sc->sc_iot = aa->aa_iot;
sc->sc_addr = aa->aa_addr;
if (aa->aa_size == AXICF_SIZE_DEFAULT)
aa->aa_size = AIPS1_IOMUXC_SIZE;
aprint_naive("\n");
aprint_normal(": IOMUX Controller\n");
if (bus_space_map(sc->sc_iot, sc->sc_addr, aa->aa_size, 0,
&sc->sc_ioh)) {
aprint_error_dev(self, "Cannot map registers\n");
return;
}
iomux_softc = sc;
return;
}
uint32_t
iomux_read(uint32_t reg)
{
if (iomux_softc == NULL)
return 0;
return bus_space_read_4(iomux_softc->sc_iot, iomux_softc->sc_ioh, reg);
}
void
iomux_write(uint32_t reg, uint32_t val)
{
if (iomux_softc == NULL)
return;
bus_space_write_4(iomux_softc->sc_iot, iomux_softc->sc_ioh, reg, val);
}
static void
iomux_set_function_sub(struct imxiomux_softc *sc, uint32_t pin, uint32_t fn)
{
bus_size_t mux_ctl_reg = IOMUX_PIN_TO_MUX_ADDRESS(pin);
if (mux_ctl_reg != IOMUX_MUX_NONE)
bus_space_write_4(sc->sc_iot, sc->sc_ioh,
mux_ctl_reg, fn);
}
void
iomux_set_function(unsigned int pin, unsigned int fn)
{
if (iomux_softc == NULL)
return;
iomux_set_function_sub(iomux_softc, pin, fn);
}
static void
iomux_set_pad_sub(struct imxiomux_softc *sc, uint32_t pin, uint32_t config)
{
bus_size_t pad_ctl_reg = IOMUX_PIN_TO_PAD_ADDRESS(pin);
if (pad_ctl_reg != IOMUX_PAD_NONE)
bus_space_write_4(sc->sc_iot, sc->sc_ioh,
pad_ctl_reg, config);
}
void
iomux_set_pad(unsigned int pin, unsigned int config)
{
if (iomux_softc == NULL)
return;
iomux_set_pad_sub(iomux_softc, pin, config);
}
#if 0
void
iomux_set_input(unsigned int input, unsigned int config)
{
bus_size_t input_ctl_reg = input;
if (iomux_softc == NULL)
return;
bus_space_write_4(iomux_softc->sc_iot, iomux_softc->sc_ioh,
input_ctl_reg, config);
}
#endif
#if 0
void
iomux_mux_config(const struct iomux_conf *conflist)
{
int i;
if (iomux_softc == NULL)
return;
for (i = 0; conflist[i].pin != IOMUX_CONF_EOT; i++) {
iomux_set_pad_sub(iomux_softc, conflist[i].pin, conflist[i].pad);
iomux_set_function_sub(iomux_softc, conflist[i].pin,
conflist[i].mux);
}
}
void
iomux_input_config(const struct iomux_input_conf *conflist)
{
int i;
if (iomux_softc == NULL)
return;
for (i = 0; conflist[i].inout != -1; i++) {
iomux_set_inout(iomux_softc, conflist[i].inout,
conflist[i].inout_mode);
}
}
#endif

721
sys/arch/arm/imx/imx6_iomuxreg.h Normal file
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@ -0,0 +1,721 @@
/* $NetBSD: imx6_iomuxreg.h,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_IMX_IMX6_IOMUXREG_H_
#define _ARM_IMX_IMX6_IOMUXREG_H_
#define IOMUX_GPR0 0x00000000
#define IOMUX_GPR1 0x00000004
#define IOMUX_GPR1_CFG_L1_CLK_REMOVAL_EN __BIT(31)
#define IOMUX_GPR1_APP_CLK_REQ_N __BIT(30)
#define IOMUX_GPR1_APP_REQ_EXIT_L1 __BIT(28)
#define IOMUX_GPR1_APP_READY_ENTR_L23 __BIT(27)
#define IOMUX_GPR1_APP_REQ_ENTR_L1 __BIT(26)
#define IOMUX_GPR1_MIPI_COLOR_SW __BIT(25)
#define IOMUX_GPR1_MIPI_DPI_OFF __BIT(24)
#define IOMUX_GPR1_Reserved __BIT(23
#define IOMUX_GPR1_EXC_MON __BIT(22)
#define IOMUX_GPR1_ENET_CLK_SEL __BIT(21)
#define IOMUX_GPR1_MIPI_IPU2_MUX __BIT(20)
#define IOMUX_GPR1_MIPI_IPU1_MUX __BIT(19)
#define IOMUX_GPR1_TEST_POWERDOWN __BIT(18)
#define IOMUX_GPR1_IPU_VPU_MUX __BIT(17)
#define IOMUX_GPR1_REF_SSP_EN __BIT(16)
#define IOMUX_GPR1_USB_EXP_MODE __BIT(15)
#define IOMUX_GPR1_SYS_INT __BIT(14)
#define IOMUX_GPR1_USB_OTG_ID_SEL __BIT(13)
#define IOMUX_GPR1_GINT __BIT(12)
#define IOMUX_GPR1_ADDRS3 __BITS(11, 10)
#define IOMUX_GPR1_ACT_CS3 __BIT(9)
#define IOMUX_GPR1_ADDRS2 __BITS(8, 7)
#define IOMUX_GPR1_ACT_CS2 __BIT(6)
#define IOMUX_GPR1_ADDRS1 __BITS(5, 4)
#define IOMUX_GPR1_ACT_CS1 __BIT(3)
#define IOMUX_GPR1_ADDRS0 __BITS(2, 1)
#define IOMUX_GPR1_ACT_CS0 __BIT(0)
#define IOMUX_GPR2 0x00000008
#define IOMUX_GPR3 0x0000000c
#define IOMUX_GPR4 0x00000010
#define IOMUX_GPR5 0x00000014
#define IOMUX_GPR6 0x00000018
#define IOMUX_GPR7 0x0000001c
#define IOMUX_GPR8 0x00000020
#define IOMUX_GPR9 0x00000024
#define IOMUX_GPR10 0x00000028
#define IOMUX_GPR11 0x0000002c
#define IOMUX_GPR12 0x00000030
#define IOMUX_GPR13 0x00000034
#define IOMUX_GPR13_SDMA_STOP_REQ __BIT(30)
#define IOMUX_GPR13_CAN2_STOP_REQ __BIT(29)
#define IOMUX_GPR13_CAN1_STOP_REQ __BIT(28)
#define IOMUX_GPR13_ENET_STOP_REQ __BIT(27)
#define IOMUX_GPR13_SATA_PHY_8(n) __SHIFTIN(n, __BITS(26, 24))
#define IOMUX_GPR13_SATA_PHY_7(n) __SHIFTIN(n, __BITS(23, 19))
#define IOMUX_GPR13_SATA_PHY_6(n) __SHIFTIN(n, __BITS(18, 16))
#define IOMUX_GPR13_SATA_SPEED(n) __SHIFTIN(n, __BIT(15))
#define IOMUX_GPR13_SATA_PHY_5(n) __SHIFTIN(n, __BIT(14))
#define IOMUX_GPR13_SATA_PHY_4(n) __SHIFTIN(n, __BITS(13, 11))
#define IOMUX_GPR13_SATA_PHY_3(n) __SHIFTIN(n, __BITS(10, 7))
#define IOMUX_GPR13_SATA_PHY_2(n) __SHIFTIN(n, __BITS(6, 2))
#define IOMUX_GPR13_SATA_PHY_1(n) __SHIFTIN(n, __BIT(1))
#define IOMUX_GPR13_SATA_PHY_0(n) __SHIFTIN(n, __BIT(0))
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 0x0000004c
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 0x00000050
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 0x00000054
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC 0x00000058
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0 0x0000005c
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1 0x00000060
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2 0x00000064
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3 0x00000068
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL 0x0000006c
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0 0x00000070
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL 0x00000074
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1 0x00000078
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2 0x0000007c
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3 0x00000080
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC 0x00000084
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25 0x00000088
#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_B 0x0000008c
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16 0x00000090
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17 0x00000094
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18 0x00000098
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19 0x0000009c
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 0x000000a0
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x000000a4
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22 0x000000a8
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23 0x000000ac
#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_B 0x000000b0
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24 0x000000b4
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25 0x000000b8
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26 0x000000bc
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27 0x000000c0
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x000000c4
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29 0x000000c8
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30 0x000000cc
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31 0x000000d0
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24 0x000000d4
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23 0x000000d8
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22 0x000000dc
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21 0x000000e0
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20 0x000000e4
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19 0x000000e8
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18 0x000000ec
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17 0x000000f0
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16 0x000000f4
#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_B 0x000000f8
#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_B 0x000000fc
#define IOMUXC_SW_MUX_CTL_PAD_EIM_OE_B 0x00000100
#define IOMUXC_SW_MUX_CTL_PAD_EIM_RW 0x00000104
#define IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B 0x00000108
#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_B 0x0000010c
#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_B 0x00000110
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD00 0x00000114
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD01 0x00000118
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD02 0x0000011c
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD03 0x00000120
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD04 0x00000124
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD05 0x00000128
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD06 0x0000012c
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD07 0x00000130
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD08 0x00000134
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD09 0x00000138
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD10 0x0000013c
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD11 0x00000140
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD12 0x00000144
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD13 0x00000148
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD14 0x0000014c
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD15 0x00000150
#define IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_B 0x00000154
#define IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK 0x00000158
#define IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK 0x0000015c
#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15 0x00000160
#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02 0x00000164
#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03 0x00000168
#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04 0x0000016c
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00 0x00000170
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01 0x00000174
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02 0x00000178
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03 0x0000017c
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04 0x00000180
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05 0x00000184
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06 0x00000188
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07 0x0000018c
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08 0x00000190
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09 0x00000194
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10 0x00000198
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11 0x0000019c
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12 0x000001a0
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13 0x000001a4
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14 0x000001a8
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15 0x000001ac
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16 0x000001b0
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17 0x000001b4
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18 0x000001b8
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19 0x000001bc
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20 0x000001c0
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21 0x000001c4
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22 0x000001c8
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23 0x000001cc
#define IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO 0x000001d0
#define IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK 0x000001d4
#define IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER 0x000001d8
#define IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV 0x000001dc
#define IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1 0x000001e0
#define IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0 0x000001e4
#define IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN 0x000001e8
#define IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1 0x000001ec
#define IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0 0x000001f0
#define IOMUXC_SW_MUX_CTL_PAD_ENET_MDC 0x000001f4
#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 0x000001f8
#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 0x000001fc
#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 0x00000200
#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 0x00000204
#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 0x00000208
#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 0x0000020c
#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 0x00000210
#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 0x00000214
#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 0x00000218
#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4 0x0000021c
#define IOMUXC_SW_MUX_CTL_PAD_GPIO00 0x00000220
#define IOMUXC_SW_MUX_CTL_PAD_GPIO01 0x00000224
#define IOMUXC_SW_MUX_CTL_PAD_GPIO09 0x00000228
#define IOMUXC_SW_MUX_CTL_PAD_GPIO03 0x0000022c
#define IOMUXC_SW_MUX_CTL_PAD_GPIO06 0x00000230
#define IOMUXC_SW_MUX_CTL_PAD_GPIO02 0x00000234
#define IOMUXC_SW_MUX_CTL_PAD_GPIO04 0x00000238
#define IOMUXC_SW_MUX_CTL_PAD_GPIO05 0x0000023c
#define IOMUXC_SW_MUX_CTL_PAD_GPIO07 0x00000240
#define IOMUXC_SW_MUX_CTL_PAD_GPIO08 0x00000244
#define IOMUXC_SW_MUX_CTL_PAD_GPIO16 0x00000248
#define IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x0000024c
#define IOMUXC_SW_MUX_CTL_PAD_GPIO18 0x00000250
#define IOMUXC_SW_MUX_CTL_PAD_GPIO19 0x00000254
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK 0x00000258
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC 0x0000025c
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN 0x00000260
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC 0x00000264
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04 0x00000268
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05 0x0000026c
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06 0x00000270
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07 0x00000274
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08 0x00000278
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09 0x0000027c
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10 0x00000280
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11 0x00000284
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12 0x00000288
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13 0x0000028c
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14 0x00000290
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15 0x00000294
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16 0x00000298
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17 0x0000029c
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18 0x000002a0
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19 0x000002a4
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x000002a8
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 0x000002ac
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5 0x000002b0
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4 0x000002b4
#define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD 0x000002b8
#define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK 0x000002bc
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 0x000002c0
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 0x000002c4
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2 0x000002c8
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3 0x000002cc
#define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET 0x000002d0
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x000002d4
#define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x000002d8
#define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x000002dc
#define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B 0x000002e0
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B 0x000002e4
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B 0x000002e8
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B 0x000002ec
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B 0x000002f0
#define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD 0x000002f4
#define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK 0x000002f8
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 0x000002fc
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 0x00000300
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 0x00000304
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 0x00000308
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 0x0000030c
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x00000310
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x00000314
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x00000318
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0 0x0000031c
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1 0x00000320
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2 0x00000324
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3 0x00000328
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4 0x0000032c
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5 0x00000330
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6 0x00000334
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7 0x00000338
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 0x0000033c
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 0x00000340
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 0x00000344
#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD 0x00000348
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 0x0000034c
#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK 0x00000350
#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK 0x00000354
#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD 0x00000358
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 0x0000035c
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 0x00000360
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 0x00000364
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 0x00000368
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC 0x0000036c
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0 0x00000370
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1 0x00000374
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2 0x00000378
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3 0x0000037c
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL 0x00000380
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0 0x00000384
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL 0x00000388
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1 0x0000038c
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2 0x00000390
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3 0x00000394
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC 0x00000398
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25 0x0000039c
#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_B 0x000003a0
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16 0x000003a4
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17 0x000003a8
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18 0x000003ac
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19 0x000003b0
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20 0x000003b4
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x000003b8
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22 0x000003bc
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23 0x000003c0
#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_B 0x000003c4
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24 0x000003c8
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25 0x000003cc
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26 0x000003d0
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27 0x000003d4
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x000003d8
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29 0x000003dc
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30 0x000003e0
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31 0x000003e4
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24 0x000003e8
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23 0x000003ec
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22 0x000003f0
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21 0x000003f4
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20 0x000003f8
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19 0x000003fc
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18 0x00000400
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17 0x00000404
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16 0x00000408
#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_B 0x0000040c
#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_B 0x00000410
#define IOMUXC_SW_PAD_CTL_PAD_EIM_OE_B 0x00000414
#define IOMUXC_SW_PAD_CTL_PAD_EIM_RW 0x00000418
#define IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_B 0x0000041c
#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_B 0x00000420
#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_B 0x00000424
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD00 0x00000428
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD01 0x0000042c
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD02 0x00000430
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD03 0x00000434
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD04 0x00000438
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD05 0x0000043c
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD06 0x00000440
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD07 0x00000444
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD08 0x00000448
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD09 0x0000044c
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD10 0x00000450
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD11 0x00000454
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD12 0x00000458
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD13 0x0000045c
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD14 0x00000460
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD15 0x00000464
#define IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_B 0x00000468
#define IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK 0x0000046c
#define IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK 0x00000470
#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15 0x00000474
#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02 0x00000478
#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03 0x0000047c
#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04 0x00000480
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00 0x00000484
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01 0x00000488
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02 0x0000048c
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03 0x00000490
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04 0x00000494
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05 0x00000498
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06 0x0000049c
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07 0x000004a0
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08 0x000004a4
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09 0x000004a8
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10 0x000004ac
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11 0x000004b0
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12 0x000004b4
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13 0x000004b8
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14 0x000004bc
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15 0x000004c0
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16 0x000004c4
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17 0x000004c8
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18 0x000004cc
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19 0x000004d0
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20 0x000004d4
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21 0x000004d8
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22 0x000004dc
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23 0x000004e0
#define IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO 0x000004e4
#define IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK 0x000004e8
#define IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER 0x000004ec
#define IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV 0x000004f0
#define IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1 0x000004f4
#define IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0 0x000004f8
#define IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN 0x000004fc
#define IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1 0x00000500
#define IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0 0x00000504
#define IOMUXC_SW_PAD_CTL_PAD_ENET_MDC 0x00000508
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P 0x0000050c
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 0x00000510
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 0x00000514
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P 0x00000518
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P 0x0000051c
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x00000520
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P 0x00000524
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x00000528
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 0x0000052c
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 0x00000530
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 0x00000534
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 0x00000538
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 0x0000053c
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 0x00000540
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 0x00000544
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 0x00000548
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 0x0000054c
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 0x00000550
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 0x00000554
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 0x00000558
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 0x0000055c
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 0x00000560
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 0x00000564
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 0x00000568
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B 0x0000056c
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B 0x00000570
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B 0x00000574
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B 0x00000578
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET 0x0000057c
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 0x00000580
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 0x00000584
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P 0x00000588
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 0x0000058c
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x00000590
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P 0x00000594
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x00000598
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 0x0000059c
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 0x000005a0
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B 0x000005a4
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P 0x000005a8
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x000005ac
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P 0x000005b0
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x000005b4
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P 0x000005b8
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 0x000005bc
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P 0x000005c0
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 0x000005c4
#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0 0x000005c8
#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0 0x000005cc
#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1 0x000005d0
#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 0x000005d4
#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2 0x000005d8
#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2 0x000005dc
#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3 0x000005e0
#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3 0x000005e4
#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4 0x000005e8
#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4 0x000005ec
#define IOMUXC_SW_PAD_CTL_PAD_GPIO00 0x000005f0
#define IOMUXC_SW_PAD_CTL_PAD_GPIO01 0x000005f4
#define IOMUXC_SW_PAD_CTL_PAD_GPIO09 0x000005f8
#define IOMUXC_SW_PAD_CTL_PAD_GPIO03 0x000005fc
#define IOMUXC_SW_PAD_CTL_PAD_GPIO06 0x00000600
#define IOMUXC_SW_PAD_CTL_PAD_GPIO02 0x00000604
#define IOMUXC_SW_PAD_CTL_PAD_GPIO04 0x00000608
#define IOMUXC_SW_PAD_CTL_PAD_GPIO05 0x0000060c
#define IOMUXC_SW_PAD_CTL_PAD_GPIO07 0x00000610
#define IOMUXC_SW_PAD_CTL_PAD_GPIO08 0x00000614
#define IOMUXC_SW_PAD_CTL_PAD_GPIO16 0x00000618
#define IOMUXC_SW_PAD_CTL_PAD_GPIO17 0x0000061c
#define IOMUXC_SW_PAD_CTL_PAD_GPIO18 0x00000620
#define IOMUXC_SW_PAD_CTL_PAD_GPIO19 0x00000624
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK 0x00000628
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC 0x0000062c
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN 0x00000630
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC 0x00000634
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04 0x00000638
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05 0x0000063c
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06 0x00000640
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07 0x00000644
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08 0x00000648
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09 0x0000064c
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10 0x00000650
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11 0x00000654
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12 0x00000658
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13 0x0000065c
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14 0x00000660
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15 0x00000664
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16 0x00000668
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17 0x0000066c
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18 0x00000670
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19 0x00000674
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS 0x00000678
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD 0x0000067c
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB 0x00000680
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI 0x00000684
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK 0x00000688
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO 0x0000068c
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7 0x00000690
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6 0x00000694
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5 0x00000698
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4 0x0000069c
#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD 0x000006a0
#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK 0x000006a4
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0 0x000006a8
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1 0x000006ac
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2 0x000006b0
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3 0x000006b4
#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET 0x000006b8
#define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE 0x000006bc
#define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE 0x000006c0
#define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B 0x000006c4
#define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B 0x000006c8
#define IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B 0x000006cc
#define IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B 0x000006d0
#define IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B 0x000006d4
#define IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B 0x000006d8
#define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD 0x000006dc
#define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK 0x000006e0
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 0x000006e4
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 0x000006e8
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 0x000006ec
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 0x000006f0
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 0x000006f4
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 0x000006f8
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 0x000006fc
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 0x00000700
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0 0x00000704
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1 0x00000708
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2 0x0000070c
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3 0x00000710
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4 0x00000714
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5 0x00000718
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6 0x0000071c
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7 0x00000720
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 0x00000724
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 0x00000728
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 0x0000072c
#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD 0x00000730
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 0x00000734
#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK 0x00000738
#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK 0x0000073c
#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD 0x00000740
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 0x00000744
#define IOMUXC_SW_PAD_CTL_GRP_B7DS 0x00000748
#define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x0000074c
#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x00000750
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0 0x00000754
#define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x00000758
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1 0x0000075c
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2 0x00000760
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3 0x00000764
#define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x00000768
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4 0x0000076c
#define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x00000770
#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x00000774
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5 0x00000778
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6 0x0000077c
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7 0x00000780
#define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x00000784
#define IOMUXC_SW_PAD_CTL_GRP_B1DS 0x00000788
#define IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x0000078c
#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII 0x00000790
#define IOMUXC_SW_PAD_CTL_GRP_B2DS 0x00000794
#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x00000798
#define IOMUXC_SW_PAD_CTL_GRP_B3DS 0x0000079c
#define IOMUXC_SW_PAD_CTL_GRP_B4DS 0x000007a0
#define IOMUXC_SW_PAD_CTL_GRP_B5DS 0x000007a4
#define IOMUXC_SW_PAD_CTL_GRP_B6DS 0x000007a8
#define IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM 0x000007ac
#define IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT 0x000007b0
#define IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT 0x000007b4
#define IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT 0x000007b8
#define IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT 0x000007bc
#define IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT 0x000007c0
#define IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT 0x000007c4
#define IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT 0x000007c8
#define IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT 0x000007cc
#define IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT 0x000007d0
#define IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT 0x000007d4
#define IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT 0x000007d8
#define IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT 0x000007dc
#define IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT 0x000007e0
#define IOMUXC_FLEXCAN1_RX_SELECT_INPUT 0x000007e4
#define IOMUXC_FLEXCAN2_RX_SELECT_INPUT 0x000007e8
#define IOMUXC_CCM_PMIC_READY_SELECT_INPUT 0x000007f0
#define IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT 0x000007f4
#define IOMUXC_ECSPI1_MISO_SELECT_INPUT 0x000007f8
#define IOMUXC_ECSPI1_MOSI_SELECT_INPUT 0x000007fc
#define IOMUXC_ECSPI1_SS0_SELECT_INPUT 0x00000800
#define IOMUXC_ECSPI1_SS1_SELECT_INPUT 0x00000804
#define IOMUXC_ECSPI1_SS2_SELECT_INPUT 0x00000808
#define IOMUXC_ECSPI1_SS3_SELECT_INPUT 0x0000080c
#define IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT 0x00000810
#define IOMUXC_ECSPI2_MISO_SELECT_INPUT 0x00000814
#define IOMUXC_ECSPI2_MOSI_SELECT_INPUT 0x00000818
#define IOMUXC_ECSPI2_SS0_SELECT_INPUT 0x0000081c
#define IOMUXC_ECSPI2_SS1_SELECT_INPUT 0x00000820
#define IOMUXC_ECSPI4_SS0_SELECT_INPUT 0x00000824
#define IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT 0x00000828
#define IOMUXC_ECSPI5_MISO_SELECT_INPUT 0x0000082c
#define IOMUXC_ECSPI5_MOSI_SELECT_INPUT 0x00000830
#define IOMUXC_ECSPI5_SS0_SELECT_INPUT 0x00000834
#define IOMUXC_ECSPI5_SS1_SELECT_INPUT 0x00000838
#define IOMUXC_ENET_REF_CLK_SELECT_INPUT 0x0000083c
#define IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT 0x00000840
#define IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT 0x00000844
#define IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT 0x00000848
#define IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT 0x0000084c
#define IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT 0x00000850
#define IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT 0x00000854
#define IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT 0x00000858
#define IOMUXC_ESAI_RX_FS_SELECT_INPUT 0x0000085c
#define IOMUXC_ESAI_TX_FS_SELECT_INPUT 0x00000860
#define IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT 0x00000864
#define IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT 0x00000868
#define IOMUXC_ESAI_RX_CLK_SELECT_INPUT 0x0000086c
#define IOMUXC_ESAI_TX_CLK_SELECT_INPUT 0x00000870
#define IOMUXC_ESAI_SDO0_SELECT_INPUT 0x00000874
#define IOMUXC_ESAI_SDO1_SELECT_INPUT 0x00000878
#define IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT 0x0000087c
#define IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT 0x00000880
#define IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT 0x00000884
#define IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT 0x00000888
#define IOMUXC_HDMI_ICECIN_SELECT_INPUT 0x0000088c
#define IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT 0x00000890
#define IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT 0x00000894
#define IOMUXC_I2C1_SCL_IN_SELECT_INPUT 0x00000898
#define IOMUXC_I2C1_SDA_IN_SELECT_INPUT 0x0000089c
#define IOMUXC_I2C2_SCL_IN_SELECT_INPUT 0x000008a0
#define IOMUXC_I2C2_SDA_IN_SELECT_INPUT 0x000008a4
#define IOMUXC_I2C3_SCL_IN_SELECT_INPUT 0x000008a8
#define IOMUXC_I2C3_SDA_IN_SELECT_INPUT 0x000008ac
#define IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT 0x000008b0
#define IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT 0x000008b4
#define IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT 0x000008b8
#define IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT 0x000008bc
#define IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT 0x000008c0
#define IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT 0x000008c4
#define IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT 0x000008c8
#define IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT 0x000008cc
#define IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT 0x000008d0
#define IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT 0x000008d4
#define IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT 0x000008d8
#define IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT 0x000008dc
#define IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT 0x000008e0
#define IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT 0x000008e4
#define IOMUXC_KEY_COL5_SELECT_INPUT 0x000008e8
#define IOMUXC_KEY_COL6_SELECT_INPUT 0x000008ec
#define IOMUXC_KEY_COL7_SELECT_INPUT 0x000008f0
#define IOMUXC_KEY_ROW5_SELECT_INPUT 0x000008f4
#define IOMUXC_KEY_ROW6_SELECT_INPUT 0x000008f8
#define IOMUXC_KEY_ROW7_SELECT_INPUT 0x000008fc
#define IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT 0x00000900
#define IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT 0x00000904
#define IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT 0x00000908
#define IOMUXC_SDMA_EVENTS14_SELECT_INPUT 0x0000090c
#define IOMUXC_SDMA_EVENTS15_SELECT_INPUT 0x00000910
#define IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT 0x00000914
#define IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT 0x00000918
#define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x0000091c
#define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x00000920
#define IOMUXC_UART2_UART_RTS_B_SELECT_INPUT 0x00000924
#define IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT 0x00000928
#define IOMUXC_UART3_UART_RTS_B_SELECT_INPUT 0x0000092c
#define IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT 0x00000930
#define IOMUXC_UART4_UART_RTS_B_SELECT_INPUT 0x00000934
#define IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT 0x00000938
#define IOMUXC_UART5_UART_RTS_B_SELECT_INPUT 0x0000093c
#define IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT 0x00000940
#define IOMUXC_USB_OTG_OC_SELECT_INPUT 0x00000944
#define IOMUXC_USB_H1_OC_SELECT_INPUT 0x00000948
/* IOMUXC_SW_MUX_CTL_PAD_xxx */
#define IOMUX_CONFIG_SION __BIT(4)
#define IOMUX_CONFIG_ALT0 0
#define IOMUX_CONFIG_ALT1 1
#define IOMUX_CONFIG_ALT2 2
#define IOMUX_CONFIG_ALT3 3
#define IOMUX_CONFIG_ALT4 4
#define IOMUX_CONFIG_ALT5 5
#define IOMUX_CONFIG_ALT6 6
#define IOMUX_CONFIG_ALT7 7
/* IOMUXC_SW_PAD_CTL_PAD_xxx */
#define PAD_CTL_DDR_SEL_MASK __BITS(19, 18)
#define PAD_CTL_DDR_SEL_0 __SHIFTIN(0, PAD_CTL_DDR_SEL_MASK)
#define PAD_CTL_DDR_SEL_1 __SHIFTIN(1, PAD_CTL_DDR_SEL_MASK)
#define PAD_CTL_DDR_SEL_2 __SHIFTIN(2, PAD_CTL_DDR_SEL_MASK)
#define PAD_CTL_DDR_SEL_3 __SHIFTIN(3, PAD_CTL_DDR_SEL_MASK)
#define PAD_CTL_HYS __BIT(16)
#define PAD_CTL_PUS_MASK __BITS(15, 14)
#define PAD_CTL_PUS_100K_PD __SHIFTIN(0x0, PAD_CTL_PUS_MASK)
#define PAD_CTL_PUS_47K_PU __SHIFTIN(0x1, PAD_CTL_PUS_MASK)
#define PAD_CTL_PUS_100K_PU __SHIFTIN(0x2, PAD_CTL_PUS_MASK)
#define PAD_CTL_PUS_22K_PU __SHIFTIN(0x3, PAD_CTL_PUS_MASK)
#define PAD_CTL_PUE __BIT(13)
#define PAD_CTL_PKE __BIT(12)
#define PAD_CTL_PULL (PAD_CTL_PKE|PAD_CTL_PUE)
#define PAD_CTL_KEEPER (PAD_CTL_PKE|0)
#define PAD_CTL_DSE_MASK __BITS(5, 3)
#define PAD_CTL_DSE_HIZ __SHIFTIN(0x0, PAD_CTL_DSE_MASK)
#define PAD_CTL_DSE_290OHM __SHIFTIN(0x1, PAD_CTL_DSE_MASK)
#define PAD_CTL_DSE_121OHM __SHIFTIN(0x2, PAD_CTL_DSE_MASK)
#define PAD_CTL_DSE_76OHM __SHIFTIN(0x3, PAD_CTL_DSE_MASK)
#define PAD_CTL_DSE_47OHM __SHIFTIN(0x4, PAD_CTL_DSE_MASK)
#define PAD_CTL_DSE_45OHM __SHIFTIN(0x5, PAD_CTL_DSE_MASK)
#define PAD_CTL_DSE_37OHM __SHIFTIN(0x6, PAD_CTL_DSE_MASK)
#define PAD_CTL_DSE_31OHM __SHIFTIN(0x7, PAD_CTL_DSE_MASK)
/* IOMUXC_SW_PAD_CTL_PAD_xxx */
#define INPUT_DAISY_0 0
#define INPUT_DAISY_1 1
#define INPUT_DAISY_2 2
#define INPUT_DAISY_3 3
#define INPUT_DAISY_4 4
#define INPUT_DAISY_5 5
#define INPUT_DAISY_6 6
#define INPUT_DAISY_7 7
/*
* IOMUX index macro
*/
#define IOMUX_PIN_TO_MUX_ADDRESS(pin) (((pin) >> 16) & 0xffff)
#define IOMUX_PIN_TO_PAD_ADDRESS(pin) (((pin) >> 0) & 0xffff)
#define IOMUX_MUX_NONE 0xffff
#define IOMUX_PAD_NONE 0xffff
#define IOMUX_PIN(mux_adr, pad_adr) \
(((mux_adr) << 16) | (((pad_adr) << 0)))
#define MUX_PIN(name) \
IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_##name, \
IOMUXC_SW_PAD_CTL_PAD_##name)
#endif /* _ARM_IMX_IMX6_IOMUXREG_H_ */

212
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/* $NetBSD: imx6_mmdcreg.h,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_IMX_IMX6_MMDCREG_H_
#define _ARM_IMX_IMX6_MMDCREG_H_
#include <sys/cdefs.h>
#define MMDC1_MDCTL 0x00000000
#define MMDC1_MDCTL_SDE_0 __BIT(31)
#define MMDC1_MDCTL_SDE_1 __BIT(30)
#define MMDC1_MDCTL_ROW __BITS(26, 24)
#define MMDC1_MDCTL_COL __BITS(22, 20)
#define MMDC1_MDCTL_BL __BIT(19)
#define MMDC1_MDCTL_DSIZ __BITS(17, 16)
#define MMDC1_MDPDC 0x00000004
#define MMDC1_MDOTC 0x00000008
#define MMDC1_MDCFG0 0x0000000c
#define MMDC1_MDCFG1 0x00000010
#define MMDC1_MDCFG2 0x00000014
#define MMDC1_MDMISC 0x00000018
#define MMDC1_MDMISC_CS0_RDY __BIT(31)
#define MMDC1_MDMISC_CS1_RDY __BIT(30)
#define MMDC1_MDMISC_CALIB_PER_CS __BIT(20)
#define MMDC1_MDMISC_ADDR_MIRROR __BIT(19)
#define MMDC1_MDMISC_LHD __BIT(18)
#define MMDC1_MDMISC_WALAT __BITS(17, 16)
#define MMDC1_MDMISC_BI_ON __BIT(12)
#define MMDC1_MDMISC_LPDDR2_S2 __BIT(11)
#define MMDC1_MDMISC_MIF3_MODE __BITS(10, 9)
#define MMDC1_MDMISC_RALAT __BITS(8, 6)
#define MMDC1_MDMISC_DDR_4_BANK __BIT(5)
#define MMDC1_MDMISC_DDR_TYPE __BITS(4, 3)
#define MMDC1_MDMISC_LPDDR2_2CH __BIT(2)
#define MMDC1_MDMISC_RST __BIT(1)
#define MMDC1_MDSCR 0x0000001c
#define MMDC1_MDREF 0x00000020
#define MMDC1_MDRWD 0x0000002c
#define MMDC1_MDOR 0x00000030
#define MMDC1_MDMRR 0x00000034
#define MMDC1_MDCFG3LP 0x00000038
#define MMDC1_MDMR4 0x0000003c
#define MMDC1_MDASP 0x00000040
#define MMDC1_MAARCR 0x00000400
#define MMDC1_MAPSR 0x00000404
#define MMDC1_MAEXIDR0 0x00000408
#define MMDC1_MAEXIDR1 0x0000040c
#define MMDC1_MADPCR0 0x00000410
#define MMDC1_MADPCR1 0x00000414
#define MMDC1_MADPSR0 0x00000418
#define MMDC1_MADPSR1 0x0000041c
#define MMDC1_MADPSR2 0x00000420
#define MMDC1_MADPSR3 0x00000424
#define MMDC1_MADPSR4 0x00000428
#define MMDC1_MADPSR5 0x0000042c
#define MMDC1_MASBS0 0x00000430
#define MMDC1_MASBS1 0x00000434
#define MMDC1_MAGENP 0x00000440
#define MMDC1_MPZQHWCTRL 0x00000800
#define MMDC1_MPZQSWCTRL 0x00000804
#define MMDC1_MPWLGCR 0x00000808
#define MMDC1_MPWLDECTRL0 0x0000080c
#define MMDC1_MPWLDECTRL1 0x00000810
#define MMDC1_MPWLDLST 0x00000814
#define MMDC1_MPODTCTRL 0x00000818
#define MMDC1_MPRDDQBY0DL 0x0000081c
#define MMDC1_MPRDDQBY1DL 0x00000820
#define MMDC1_MPRDDQBY2DL 0x00000824
#define MMDC1_MPRDDQBY3DL 0x00000828
#define MMDC1_MPWRDQBY0DL 0x0000082c
#define MMDC1_MPWRDQBY1DL 0x00000830
#define MMDC1_MPWRDQBY2DL 0x00000834
#define MMDC1_MPWRDQBY3DL 0x00000838
#define MMDC1_MPDGCTRL0 0x0000083c
#define MMDC1_MPDGCTRL1 0x00000840
#define MMDC1_MPDGDLST0 0x00000844
#define MMDC1_MPRDDLCTL 0x00000848
#define MMDC1_MPRDDLST 0x0000084c
#define MMDC1_MPWRDLCTL 0x00000850
#define MMDC1_MPWRDLST 0x00000854
#define MMDC1_MPSDCTRL 0x00000858
#define MMDC1_MPZQLP2CTL 0x0000085c
#define MMDC1_MPRDDLHWCTL 0x00000860
#define MMDC1_MPWRDLHWCTL 0x00000864
#define MMDC1_MPRDDLHWST0 0x00000868
#define MMDC1_MPRDDLHWST1 0x0000086c
#define MMDC1_MPWRDLHWST0 0x00000870
#define MMDC1_MPWRDLHWST1 0x00000874
#define MMDC1_MPWLHWERR 0x00000878
#define MMDC1_MPDGHWST0 0x0000087c
#define MMDC1_MPDGHWST1 0x00000880
#define MMDC1_MPDGHWST2 0x00000884
#define MMDC1_MPDGHWST3 0x00000888
#define MMDC1_MPPDCMPR1 0x0000088c
#define MMDC1_MPPDCMPR2 0x00000890
#define MMDC1_MPSWDAR0 0x00000894
#define MMDC1_MPSWDRDR0 0x00000898
#define MMDC1_MPSWDRDR1 0x0000089c
#define MMDC1_MPSWDRDR2 0x000008a0
#define MMDC1_MPSWDRDR3 0x000008a4
#define MMDC1_MPSWDRDR4 0x000008a8
#define MMDC1_MPSWDRDR5 0x000008ac
#define MMDC1_MPSWDRDR6 0x000008b0
#define MMDC1_MPSWDRDR7 0x000008b4
#define MMDC1_MPMUR0 0x000008b8
#define MMDC1_MPWRCADL 0x000008bc
#define MMDC1_MPDCCR 0x000008c0
#define MMDC2_MDCTL 0x00004000
#define MMDC2_MDPDC 0x00004004
#define MMDC2_MDOTC 0x00004008
#define MMDC2_MDCFG0 0x0000400c
#define MMDC2_MDCFG1 0x00004010
#define MMDC2_MDCFG2 0x00004014
#define MMDC2_MDMISC 0x00004018
#define MMDC2_MDSCR 0x0000401c
#define MMDC2_MDREF 0x00004020
#define MMDC2_MDRWD 0x0000402c
#define MMDC2_MDOR 0x00004030
#define MMDC2_MDMRR 0x00004034
#define MMDC2_MDCFG3LP 0x00004038
#define MMDC2_MDMR4 0x0000403c
#define MMDC2_MDASP 0x00004040
#define MMDC2_MAARCR 0x00004400
#define MMDC2_MAPSR 0x00004404
#define MMDC2_MAEXIDR0 0x00004408
#define MMDC2_MAEXIDR1 0x0000440c
#define MMDC2_MADPCR0 0x00004410
#define MMDC2_MADPCR1 0x00004414
#define MMDC2_MADPSR0 0x00004418
#define MMDC2_MADPSR1 0x0000441c
#define MMDC2_MADPSR2 0x00004420
#define MMDC2_MADPSR3 0x00004424
#define MMDC2_MADPSR4 0x00004428
#define MMDC2_MADPSR5 0x0000442c
#define MMDC2_MASBS0 0x00004430
#define MMDC2_MASBS1 0x00004434
#define MMDC2_MAGENP 0x00004440
#define MMDC2_MPZQHWCTRL 0x00004800
#define MMDC2_MPZQSWCTRL 0x00004804
#define MMDC2_MPWLGCR 0x00004808
#define MMDC2_MPWLDECTRL0 0x0000480c
#define MMDC2_MPWLDECTRL1 0x00004810
#define MMDC2_MPWLDLST 0x00004814
#define MMDC2_MPODTCTRL 0x00004818
#define MMDC2_MPRDDQBY0DL 0x0000481c
#define MMDC2_MPRDDQBY1DL 0x00004820
#define MMDC2_MPRDDQBY2DL 0x00004824
#define MMDC2_MPRDDQBY3DL 0x00004828
#define MMDC2_MPWRDQBY0DL 0x0000482c
#define MMDC2_MPWRDQBY1DL 0x00004830
#define MMDC2_MPWRDQBY2DL 0x00004834
#define MMDC2_MPWRDQBY3DL 0x00004838
#define MMDC2_MPDGCTRL0 0x0000483c
#define MMDC2_MPDGCTRL1 0x00004840
#define MMDC2_MPDGDLST0 0x00004844
#define MMDC2_MPRDDLCTL 0x00004848
#define MMDC2_MPRDDLST 0x0000484c
#define MMDC2_MPWRDLCTL 0x00004850
#define MMDC2_MPWRDLST 0x00004854
#define MMDC2_MPSDCTRL 0x00004858
#define MMDC2_MPZQLP2CTL 0x0000485c
#define MMDC2_MPRDDLHWCTL 0x00004860
#define MMDC2_MPWRDLHWCTL 0x00004864
#define MMDC2_MPRDDLHWST0 0x00004868
#define MMDC2_MPRDDLHWST1 0x0000486c
#define MMDC2_MPWRDLHWST0 0x00004870
#define MMDC2_MPWRDLHWST1 0x00004874
#define MMDC2_MPWLHWERR 0x00004878
#define MMDC2_MPDGHWST0 0x0000487c
#define MMDC2_MPDGHWST1 0x00004880
#define MMDC2_MPDGHWST2 0x00004884
#define MMDC2_MPDGHWST3 0x00004888
#define MMDC2_MPPDCMPR1 0x0000488c
#define MMDC2_MPPDCMPR2 0x00004890
#define MMDC2_MPSWDAR0 0x00004894
#define MMDC2_MPSWDRDR0 0x00004898
#define MMDC2_MPSWDRDR1 0x0000489c
#define MMDC2_MPSWDRDR2 0x000048a0
#define MMDC2_MPSWDRDR3 0x000048a4
#define MMDC2_MPSWDRDR4 0x000048a8
#define MMDC2_MPSWDRDR5 0x000048ac
#define MMDC2_MPSWDRDR6 0x000048b0
#define MMDC2_MPSWDRDR7 0x000048b4
#define MMDC2_MPMUR0 0x000048b8
#define MMDC2_MPWRCADL 0x000048bc
#define MMDC2_MPDCCR 0x000048c0
#endif /* _ARM_IMX_IMX6_MMDCREG_H_ */

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/* $NetBSD: imx6_ocotp.c,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* i.MX6 On-Chip OTP Controller
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: imx6_ocotp.c,v 1.1 2014/09/25 05:05:28 ryo Exp $");
#include <sys/bus.h>
#include <sys/device.h>
#include <sys/param.h>
#include <arm/imx/imx6var.h>
#include <arm/imx/imx6_reg.h>
#include <arm/imx/imx6_ocotpreg.h>
#include <arm/imx/imx6_ocotpvar.h>
#include "locators.h"
struct imxocotp_softc {
device_t sc_dev;
bus_addr_t sc_addr;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_ioh;
};
static struct imxocotp_softc *ocotp_softc;
static int imxocotp_match(device_t, struct cfdata *, void *);
static void imxocotp_attach(device_t, device_t, void *);
CFATTACH_DECL_NEW(imxocotp, sizeof(struct imxocotp_softc),
imxocotp_match, imxocotp_attach, NULL, NULL);
/* ARGSUSED */
static int
imxocotp_match(device_t parent __unused, struct cfdata *match __unused, void *aux)
{
struct axi_attach_args *aa;
aa = aux;
if (ocotp_softc != NULL)
return 0;
switch (aa->aa_addr) {
case (IMX6_AIPS2_BASE + AIPS2_OCOTP_CTRL_BASE):
return 1;
}
return 0;
}
/* ARGSUSED */
static void
imxocotp_attach(device_t parent __unused, device_t self, void *aux)
{
struct imxocotp_softc *sc;
struct axi_attach_args *aa;
uint32_t v;
aa = aux;
sc = device_private(self);
sc->sc_dev = self;
sc->sc_iot = aa->aa_iot;
sc->sc_addr = aa->aa_addr;
if (aa->aa_size == AXICF_SIZE_DEFAULT)
aa->aa_size = AIPS2_OCOTP_CTRL_SIZE;
aprint_naive("\n");
aprint_normal(": On-Chip OTP Controller\n");
if (bus_space_map(sc->sc_iot, sc->sc_addr, aa->aa_size, 0,
&sc->sc_ioh)) {
aprint_error_dev(self, "Cannot map registers\n");
return;
}
ocotp_softc = sc;
v = imxocotp_read(OCOTP_VERSION);
aprint_normal_dev(self, "OCOTP_VERSION %d.%d.%d\n", (v >> 24) & 0xff, (v >> 16) & 0xff, v & 0xffff);
return;
}
uint32_t
imxocotp_read(uint32_t addr)
{
struct imxocotp_softc *sc;
if ((sc = ocotp_softc) == NULL)
return 0;
if (addr > AIPS2_OCOTP_CTRL_SIZE)
return 0;
return bus_space_read_4(sc->sc_iot, sc->sc_ioh, addr);
}

80
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@ -0,0 +1,80 @@
/* $NetBSD: imx6_ocotpreg.h,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_IMX_IMX6_OCOTP_H_
#define _ARM_IMX_IMX6_OCOTP_H_
#define OCOTP_CTRL 0x00000000
#define OCOTP_CTRL_SET 0x00000004
#define OCOTP_CTRL_CLR 0x00000008
#define OCOTP_CTRL_TOG 0x0000000c
#define OCOTP_TIMING 0x00000010
#define OCOTP_DATA 0x00000020
#define OCOTP_READ_CTRL 0x00000030
#define OCOTP_READ_FUSE_DATA 0x00000040
#define OCOTP_SW_STICKY 0x00000050
#define OCOTP_SCS 0x00000060
#define OCOTP_SCS_SET 0x00000064
#define OCOTP_SCS_CLR 0x00000068
#define OCOTP_SCS_TOG 0x0000006c
#define OCOTP_VERSION 0x00000090
#define OCOTP_LOCK 0x00000400
#define OCOTP_CFG0 0x00000410
#define OCOTP_CFG1 0x00000420
#define OCOTP_CFG2 0x00000430
#define OCOTP_CFG3 0x00000440
#define OCOTP_CFG4 0x00000450
#define OCOTP_CFG5 0x00000460
#define OCOTP_CFG6 0x00000470
#define OCOTP_MEM0 0x00000480
#define OCOTP_MEM1 0x00000490
#define OCOTP_MEM2 0x000004a0
#define OCOTP_MEM3 0x000004b0
#define OCOTP_MEM4 0x000004c0
#define OCOTP_ANA0 0x000004d0
#define OCOTP_ANA1 0x000004e0
#define OCOTP_ANA2 0x000004f0
#define OCOTP_SRK0 0x00000580
#define OCOTP_SRK1 0x00000590
#define OCOTP_SRK2 0x000005a0
#define OCOTP_SRK3 0x000005b0
#define OCOTP_SRK4 0x000005c0
#define OCOTP_SRK5 0x000005d0
#define OCOTP_SRK6 0x000005e0
#define OCOTP_SRK7 0x000005f0
#define OCOTP_RESP0 0x00000600
#define OCOTP_HSJC_RESP1 0x00000610
#define OCOTP_MAC0 0x00000620
#define OCOTP_MAC1 0x00000630
#define OCOTP_GP1 0x00000660
#define OCOTP_GP2 0x00000670
#define OCOTP_MISC_CONF 0x000006d0
#define OCOTP_FIELD_RETURN 0x000006e0
#define OCOTP_SRK_REVOKE 0x000006f0
#endif /* _ARM_IMX_IMX6_OCOTP_H_ */

34
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@ -0,0 +1,34 @@
/* $NetBSD: imx6_ocotpvar.h,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_IMX_IMX6_OCOTPVAR_H_
#define _ARM_IMX_IMX6_OCOTPVAR_H_
uint32_t imxocotp_read(uint32_t);
#endif /* _ARM_IMX_IMX6_OCOTPVAR_H_ */

86
sys/arch/arm/imx/imx6_reg.h
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@ -1,4 +1,4 @@
/* $NetBSD: imx6_reg.h,v 1.1 2012/09/01 00:07:32 matt Exp $ */
/* $NetBSD: imx6_reg.h,v 1.2 2014/09/25 05:05:28 ryo Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@ -31,6 +31,17 @@
#ifndef _ARM_IMX_IMX6_REG_H_
#define _ARM_IMX_IMX6_REG_H_
#define IMX6_IOREG_PBASE IMX6_AIPS1_BASE
#define IMX6_IOREG_SIZE (IMX6_AIPS1_SIZE + IMX6_AIPS2_SIZE)
#define IMX6_ARMCORE_PBASE IMX6_MPCORE_BASE
#define IMX6_ARMCORE_SIZE IMX6_MPCORE_SIZE
#define IMX6_IO_SIZE (IMX6_IOREG_SIZE + IMX6_ARMCORE_SIZE)
#define ARMCORE_SCU_BASE 0x00000000
#define ARMCORE_L2C_BASE 0x00002000
#define IMX6_MEM_BASE 0x10000000
#define IMX6_MEM_SIZE 0xF0000000
@ -46,8 +57,8 @@
#define IMX6_HSI_BASE 0x02208000
#define IMX6_HSI_SIZE 0x00004000
#define IMX6_GPU2D_BASE 0x02204000
#define IMX6_GPU2D_SIZE 0x00004000
#define IMX6_OPENVG_BASE 0x02204000
#define IMX6_OPENVG_SIZE 0x00004000
#define IMX6_SATA_BASE 0x02200000
#define IMX6_SATA_SIZE 0x00004000
@ -74,7 +85,7 @@
#define IMX6_L2CC_SIZE 0x00001000
#define IMX6_MPCORE_BASE 0x00a00000
#define IMX6_MPCORE_SIZE 0x00a00000
#define IMX6_MPCORE_SIZE 0x00100000
#define IMX6_OCRAM1_BASE 0x00940000
#define IMX6_OCRAM1_SIZE 0x000c0000
@ -122,10 +133,12 @@
#define AIPS1_DCIC2_BASE 0x000e8000
#define AIPS1_DCIC1_BASE 0x000e4000
#define AIPS1_IOMUXC_BASE 0x000e0000
#define AIPS1_IOMUXC_SIZE 0x00001000
#define AIPS1_GPC_BASE 0x000dc000
#define AIPS1_SRC_BASE 0x000d8000
#define AIPS1_EPIT2_BASE 0x000d4000
#define AIPS1_EPIT1_BASE 0x000d0000
#define AIPS1_EPIT_SIZE 0x00000020
#define AIPS1_SNVS_HP_BASE 0x000cc000
#define AIPS1_USBPHY2_BASE 0x000ca000
#define AIPS1_USBPHY1_BASE 0x000c9000
@ -133,6 +146,7 @@
#define AIPS1_CCM_BASE 0x000c4000
#define AIPS1_WDOG2_BASE 0x000c0000
#define AIPS1_WDOG1_BASE 0x000bc000
#define AIPS1_WDOG_SIZE 0x00000010
#define AIPS1_KPP_BASE 0x000b8000
#define AIPS1_GPIO7_BASE 0x000b4000
#define AIPS1_GPIO6_BASE 0x000b0000
@ -141,6 +155,7 @@
#define AIPS1_GPIO3_BASE 0x000a4000
#define AIPS1_GPIO2_BASE 0x000a0000
#define AIPS1_GPIO1_BASE 0x0009c000
#define GPIO_NGROUPS 7
#define AIPS1_GPT_BASE 0x00098000
#define AIPS1_CAN2_BASE 0x00094000
#define AIPS1_CAN1_BASE 0x00090000
@ -164,35 +179,38 @@
#define AIPS1_ECSPI1_BASE 0x00008000
#define AIPS1_SPDIF_BASE 0x00004000
#define AIPS2_UART5_BASE 0x001f4000
#define AIPS2_UART4_BASE 0x001f0000
#define AIPS2_UART3_BASE 0x001ec000
#define AIPS2_UART2_BASE 0x001e8000
#define AIPS2_VDOA_BASE 0x001e3000
#define AIPS2_MIPIDSI_BASE 0x001e0000
#define AIPS2_MIPICSI_BASE 0x001dc000
#define AIPS2_AUDMUX_BASE 0x001d8000
#define AIPS2_TZASC2_BASE 0x001d4000
#define AIPS2_TZASC1_BASE 0x001d0000
#define AIPS2_CSU_BASE 0x001c0000
#define AIPS2_OCOTP_CTRL_BASE 0x001bc000
#define AIPS2_WEIM_BASE 0x001b8000
#define AIPS2_MMDC1_BASE 0x001b4000
#define AIPS2_MMDC0_BASE 0x001b0000
#define AIPS2_ROMCP_BASE 0x001ac000
#define AIPS2_I2C3_BASE 0x001a8000
#define AIPS2_I2C2_BASE 0x001a4000
#define AIPS2_I2C1_BASE 0x001a0000
#define AIPS2_USDHC4_BASE 0x0019c000
#define AIPS2_USDHC3_BASE 0x00198000
#define AIPS2_USDHC2_BASE 0x00194000
#define AIPS2_USDHC1_BASE 0x00190000
#define AIPS2_MLB150_BASE 0x0018c000
#define AIPS2_ENET_BASE 0x00188000
#define AIPS2_USBOH3A_BASE 0x00184000
#define AIPS2_USBOH3B_BASE 0x00180000
#define AIPS2_CONFIG_BASE 0x0017c000
#define AIPS2_DAP_BASE 0x00140000
#define AIPS2_CAAM_BASE 0x00100000
#define AIPS2_UART5_BASE 0x000f4000
#define AIPS2_UART4_BASE 0x000f0000
#define AIPS2_UART3_BASE 0x000ec000
#define AIPS2_UART2_BASE 0x000e8000
#define AIPS2_VDOA_BASE 0x000e3000
#define AIPS2_MIPIDSI_BASE 0x000e0000
#define AIPS2_MIPICSI_BASE 0x000dc000
#define AIPS2_AUDMUX_BASE 0x000d8000
#define AIPS2_TZASC2_BASE 0x000d4000
#define AIPS2_TZASC1_BASE 0x000d0000
#define AIPS2_CSU_BASE 0x000c0000
#define AIPS2_OCOTP_CTRL_BASE 0x000bc000
#define AIPS2_OCOTP_CTRL_SIZE 0x00000700
#define AIPS2_WEIM_BASE 0x000b8000
#define AIPS2_MMDC2_BASE 0x000b4000
#define AIPS2_MMDC1_BASE 0x000b0000
#define AIPS2_ROMCP_BASE 0x000ac000
#define AIPS2_I2C3_BASE 0x000a8000
#define AIPS2_I2C2_BASE 0x000a4000
#define AIPS2_I2C1_BASE 0x000a0000
#define AIPS2_USDHC4_BASE 0x0009c000
#define AIPS2_USDHC3_BASE 0x00098000
#define AIPS2_USDHC2_BASE 0x00094000
#define AIPS2_USDHC1_BASE 0x00090000
#define AIPS2_USDHC_SIZE 0x000000d0
#define AIPS2_MLB150_BASE 0x0008c000
#define AIPS2_ENET_BASE 0x00088000
#define AIPS2_ENET_SIZE 0x00000800
#define AIPS2_USBOH_BASE 0x00084000
#define AIPS2_USBOH_SIZE 0x00000820
#define AIPS2_CONFIG_BASE 0x0007c000
#define AIPS2_DAP_BASE 0x00040000
#define AIPS2_CAAM_BASE 0x00000000
#endif /* _ARM_IMX_IMX6_REG_H_ */

100
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/* $NetBSD: imx6_srcreg.h,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _IMX6_SRCREG_H_
#define _IMX6_SRCREG_H_
#include <sys/cdefs.h>
/* SRC - System Reset Controller */
#define SRC_SCR 0x00000000
#define SRC_SCR_DBG_RST_MASK_PG __BIT(25)
#define SRC_SCR_CORE3_ENABLE __BIT(24)
#define SRC_SCR_CORE2_ENABLE __BIT(23)
#define SRC_SCR_CORE1_ENABLE __BIT(22)
#define SRC_SCR_CORES_DBG_RST __BIT(21)
#define SRC_SCR_CORE3_DBG_RST __BIT(20)
#define SRC_SCR_CORE2_DBG_RST __BIT(19)
#define SRC_SCR_CORE1_DBG_RST __BIT(18)
#define SRC_SCR_CORE0_DBG_RST __BIT(17)
#define SRC_SCR_CORE3_RST __BIT(16)
#define SRC_SCR_CORE2_RST __BIT(15)
#define SRC_SCR_CORE1_RST __BIT(14)
#define SRC_SCR_CORE0_RST __BIT(13)
#define SRC_SCR_SW_IPU2_RST __BIT(12)
#define SRC_SCR_EIM_RST __BIT(11)
#define SRC_SCR_MASK_WDOG_RST __BITS(10, 7)
#define SRC_SCR_WARM_RST_BYPASS_COUNT __BITS(6, 5)
#define SRC_SCR_SW_OPEN_VG_RS __BIT(4)
#define SRC_SCR_SW_IPU1_RST __BIT(3)
#define SRC_SCR_SW_VPU_RST __BIT(2)
#define SRC_SCR_SW_GPU_RST __BIT(1)
#define SRC_SCR_WARM_RESET_ENABLE __BIT(0)
#define SRC_SBMR1 0x00000004
#define SRC_SRSR 0x00000008
#define SRC_SRSR_WARM_BOOT __BIT(16)
#define SRC_SRSR_RESERVED7 __BITS(15, 7)
#define SRC_SRSR_JTAG_SW_RST __BIT(6)
#define SRC_SRSR_JTAG_RST_B __BIT(5)
#define SRC_SRSR_WDOG_RST_B __BIT(4)
#define SRC_SRSR_IPP_USER_RESET_ __BIT(3)
#define SRC_SRSR_CSU_RESET_B __BIT(2)
#define SRC_SRSR_RESERVED1 __BIT(1)
#define SRC_SRSR_IPP_RESET_B __BIT(0)
#define SRC_SISR 0x00000014
#define SRC_SISR_CORE3_WDOG_RST_REQ __BIT(8)
#define SRC_SISR_CORE2_WDOG_RST_REQ __BIT(7)
#define SRC_SISR_CORE1_WDOG_RST_REQ __BIT(6)
#define SRC_SISR_CORE0_WDOG_RST_REQ __BIT(5)
#define SRC_SISR_IPU2_PASSED_RESET __BIT(4)
#define SRC_SISR_OPEN_VG_PASSED_RESET __BIT(3)
#define SRC_SISR_IPU1_PASSED_RESET __BIT(2)
#define SRC_SISR_VPU_PASSED_RESET __BIT(1)
#define SRC_SISR_GPU_PASSED_RESET __BIT(0)
#define SRC_SIMR 0x00000018
#define SRC_SIMR_MASK_IPU2_PASSED_RESET _BIT(4)
#define SRC_SIMR_MASK_OPEN_VG_PASSED_RESET _BIT(3)
#define SRC_SIMR_MASK_IPU_PASSED_RESET _BIT(2)
#define SRC_SIMR_MASK_VPU_PASSED_RESET _BIT(1)
#define SRC_SIMR_MASK_GPU_PASSED_RESET _BIT(0)
#define SRC_SBMR2 0x0000001c
#define SRC_GPR1 0x00000020 /* core0 entry */
#define SRC_GPR2 0x00000024
#define SRC_GPR3 0x00000028 /* core1 entry */
#define SRC_GPR4 0x0000002c
#define SRC_GPR5 0x00000030 /* core2 entry */
#define SRC_GPR6 0x00000034
#define SRC_GPR7 0x00000038 /* core3 entry */
#define SRC_GPR8 0x0000003c
#define SRC_GPR9 0x00000040
#define SRC_GPR10 0x00000044
#define SRC_GPR10_CORE3_ERROR_STATUS __BIT(27)
#define SRC_GPR10_CORE2_ERROR_STATUS __BIT(26)
#define SRC_GPR10_CORE1_ERROR_STATUS __BIT(25)
#endif /* _IMX6_SRCREG_H_ */

62
sys/arch/arm/imx/imx6_uart.c Normal file
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@ -0,0 +1,62 @@
/* $NetBSD: imx6_uart.c,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*
* Copyright (c) 2013 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#include "opt_imxuart.h"
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/device.h>
#include <arm/imx/imx6_reg.h>
#include <arm/imx/imx6var.h>
#include <arm/imx/imxuartreg.h>
#include <arm/imx/imxuartvar.h>
int
imxuart_match(device_t parent, struct cfdata *cf, void *aux)
{
struct axi_attach_args * const aa = aux;
switch (aa->aa_addr) {
case (IMX6_AIPS1_BASE + AIPS1_UART1_BASE):
case (IMX6_AIPS2_BASE + AIPS2_UART2_BASE):
case (IMX6_AIPS2_BASE + AIPS2_UART3_BASE):
case (IMX6_AIPS2_BASE + AIPS2_UART4_BASE):
case (IMX6_AIPS2_BASE + AIPS2_UART5_BASE):
return 1;
}
return 0;
}
void
imxuart_attach(device_t parent, device_t self, void *aux)
{
struct axi_attach_args * aa = aux;
imxuart_attach_common(parent, self,
aa->aa_iot, aa->aa_addr, aa->aa_size, aa->aa_irq, 0);
}

112
sys/arch/arm/imx/imx6_usb.c Normal file
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/* $NetBSD: imx6_usb.c,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*
* Copyright (c) 2012 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: imx6_usb.c,v 1.1 2014/09/25 05:05:28 ryo Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/conf.h>
#include <sys/kernel.h>
#include <sys/device.h>
#include <sys/intr.h>
#include <sys/bus.h>
#include <dev/usb/usb.h>
#include <dev/usb/usbdi.h>
#include <dev/usb/usbdivar.h>
#include <dev/usb/usb_mem.h>
#include <dev/usb/ehcireg.h>
#include <dev/usb/ehcivar.h>
#include <arm/imx/imx6_reg.h>
#include <arm/imx/imx6var.h>
#include <arm/imx/imx6_ccmreg.h>
#include <arm/imx/imx6_ccmvar.h>
#include <arm/imx/imxusbvar.h>
#include "locators.h"
static int imxusbc_search(device_t, cfdata_t, const int *, void *);
static int imxusbc_print(void *, const char *);
int
imxusbc_attach_common(device_t parent, device_t self, bus_space_tag_t iot)
{
struct imxusbc_softc *sc;
uint32_t v;
sc = device_private(self);
sc->sc_iot = iot;
/* Map entire USBOH registers. Host controller drivers
* re-use subregions of this. */
if (bus_space_map(iot, IMX6_AIPS2_BASE + AIPS2_USBOH_BASE, /* XXX */
AIPS2_USBOH_SIZE, 0, &sc->sc_ioh))
return -1;
/* USBOH3 clock enable */
v = imx6_ccm_read(CCM_CCGR6);
imx6_ccm_write(CCM_CCGR6, v | CCM_CCGR6_USBOH3_CLK_ENABLE(3));
/* attach OTG/EHCI host controllers */
config_search_ia(imxusbc_search, self, "imxusbc", NULL);
return 0;
}
static int
imxusbc_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
{
struct imxusbc_softc *sc;
struct imxusbc_attach_args aa;
sc = device_private(parent);
aa.aa_iot = sc->sc_iot;
aa.aa_ioh = sc->sc_ioh;
aa.aa_dmat = &imx_bus_dma_tag;
aa.aa_unit = cf->cf_loc[IMXUSBCCF_UNIT];
aa.aa_irq = cf->cf_loc[IMXUSBCCF_IRQ];
if (config_match(parent, cf, &aa) > 0)
config_attach(parent, cf, &aa, imxusbc_print);
return 0;
}
/* ARGSUSED */
static int
imxusbc_print(void *aux, const char *name __unused)
{
struct imxusbc_attach_args *iaa;
iaa = (struct imxusbc_attach_args *)aux;
aprint_normal(" unit %d intr %d", iaa->aa_unit, iaa->aa_irq);
return UNCONF;
}

112
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/* $NetBSD: imx6_usbreg.h,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _IMX6_USBREG_H_
#define _IMX6_USBREG_H_
#include <sys/cdefs.h>
#define USBC_UOG_CAPLENGTH 0x00000100
#define USBC_UOG_PORTSC1 0x00000184
#define USBC_UOG_USBMODE 0x000001a8
#define USBC_UOG_USBMODE_SDIS __BIT(4)
#define USBC_UOG_USBMODE_SLOM __BIT(3)
#define USBC_UOG_USBMODE_ES __BIT(2)
#define USBC_UOG_USBMODE_CM __BITS(1, 0)
#define USBC_UH1_CAPLENGTH 0x00000300
#define USBC_UH1_PORTSC1 0x00000384
#define USBC_UH_PORTSC1_PTS_1 __BITS(31, 30)
#define USBC_UH_PORTSC1_PE __BIT(2)
#define USBC_UH_PORTSC1_PTS_2 __BIT(25)
#define USBC_UH_PORTSC1_PTS_MASK (__BITS(31, 30) | __BIT(25))
#define USBC_UH_PORTSC1_PTS_UTMI 0
#define USBC_UH_PORTSC1_PTS_ULPI __BIT(31)
#define USBC_UH_PORTSC1_PTS_SERIAL (__BIT(31) | __BIT(30))
#define USBC_UH_PORTSC1_PTS_HSIC __BIT(25)
#define USBC_UH1_USBMODE 0x000003a8
#define USBC_UH_USBMODE_SDIS __BIT(4)
#define USBC_UH_USBMODE_SLOM __BIT(3)
#define USBC_UH_USBMODE_ES __BIT(2)
#define USBC_UH_USBMODE_CM __BITS(1, 0)
#define USBC_UH_USBMODE_CM_IDLE 0
#define USBC_UH_USBMODE_CM_DEVICE_CONTROLLER 2
#define USBC_UH_USBMODE_CM_HOST_CONTROLLER 3
#define USBC_UH2_CAPLENGTH 0x00000500
#define USBC_UH2_PORTSC1 0x00000584
#define USBC_UH2_USBMODE 0x000005a8
#define USBC_UH3_CAPLENGTH 0x00000700
#define USBC_UH3_PORTSC1 0x00000784
#define USBC_UH3_USBMODE 0x000007a8
#define USBNC_USB_OTG_CTRL 0x00000800
#define USBNC_USB_OTG_CTRL_WIR __BIT(31)
#define USBNC_USB_OTG_CTRL_WKUP_VBUS_EN __BIT(17)
#define USBNC_USB_OTG_CTRL_WKUP_ID_EN __BIT(16)
#define USBNC_USB_OTG_CTRL_WKUP_SW __BIT(15)
#define USBNC_USB_OTG_CTRL_WKUP_SW_EN __BIT(14)
#define USBNC_USB_OTG_CTRL_UTMI_ON_CLOCK __BIT(13)
#define USBNC_USB_OTG_CTRL_WIE __BIT(10)
#define USBNC_USB_OTG_CTRL_PWR_POL __BIT(9)
#define USBNC_USB_OTG_CTRL_OVER_CUR_POL __BIT(8)
#define USBNC_USB_OTG_CTRL_OVER_CUR_DIS __BIT(7)
#define USBNC_USB_UH1_CTRL 0x00000804
#define USBNC_USB_UH1_CTRL_WIR __BIT(31)
#define USBNC_USB_UH1_CTRL_WKUP_VBUS_EN __BIT(17)
#define USBNC_USB_UH1_CTRL_WKUP_ID_EN __BIT(16)
#define USBNC_USB_UH1_CTRL_WKUP_SW __BIT(15)
#define USBNC_USB_UH1_CTRL_WKUP_SW_EN __BIT(14)
#define USBNC_USB_UH1_CTRL_UTMI_ON_CLOCK __BIT(13)
#define USBNC_USB_UH1_CTRL_WIE __BIT(10)
#define USBNC_USB_UH1_CTRL_PWR_POL __BIT(9)
#define USBNC_USB_UH1_CTRL_OVER_CUR_POL __BIT(8)
#define USBNC_USB_UH1_CTRL_OVER_CUR_DIS __BIT(7)
#define USBNC_USB_UH2_CTRL 0x00000808
#define USBNC_USB_UH2_CTRL_WKUP_SW __BIT(15)
#define USBNC_USB_UH2_CTRL_WKUP_SW_EN __BIT(14)
#define USBNC_USB_UH2_CTRL_UTMI_ON_CLOCK __BIT(13)
#define USBNC_USB_UH2_CTRL_WIE __BIT(10)
#define USBNC_USB_UH3_CTRL 0x0000080c
#define USBNC_USB_UH3_CTRL_WKUP_SW __BIT(15)
#define USBNC_USB_UH3_CTRL_WKUP_SW_EN __BIT(14)
#define USBNC_USB_UH3_CTRL_UTMI_ON_CLOCK __BIT(13)
#define USBNC_USB_UH3_CTRL_WIE __BIT(10)
#define USBNC_USB_UH2_HSIC_CTRL 0x00000810
#define USBNC_USB_UH2_HSIC_CTRL_CLK_VLK __BIT(31)
#define USBNC_USB_UH2_HSIC_CTRL_HSIC_EN __BIT(12)
#define USBNC_USB_UH2_HSIC_CTRL_HSIC_CLK_ON __BIT(11)
#define USBNC_USB_UH3_HSIC_CTRL 0x00000814
#define USBNC_USB_UH3_HSIC_CTRL_CLK_VLK __BIT(31)
#define USBNC_USB_UH3_HSIC_CTRL_HSIC_EN __BIT(12)
#define USBNC_USB_UH3_HSIC_CTRL_HSIC_CLK_ON __BIT(11)
#define USBNC_USB_OTG_PHY_CTRL_0 0x00000818
#define USBNC_USB_OTG_PHY_CTRL_0_UTMI_CLK_VLD __BIT(31)
#define USBNC_USB_UH1_PHY_CTRL_0 0x0000081c
#define USBNC_USB_UH1_PHY_CTRL_0_UTMI_CLK_VLD __BIT(31)
#endif /* _IMX6_USBREG_H_ */

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/* $NetBSD: imx6_usdhc.c,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*-
* Copyright (c) 2012 Genetec Corporation. All rights reserved.
* Written by Hiroyuki Bessho for Genetec Corporation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS''
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: imx6_usdhc.c,v 1.1 2014/09/25 05:05:28 ryo Exp $");
#include "opt_imx.h"
#include <sys/param.h>
#include <sys/device.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/pmf.h>
#include <machine/intr.h>
#include <dev/sdmmc/sdhcvar.h>
#include <dev/sdmmc/sdmmcvar.h>
#include <arm/imx/imx6_reg.h>
#include <arm/imx/imx6var.h>
#include <arm/imx/imx6_ccmvar.h>
#include <arm/imx/imx6_ccmreg.h>
struct sdhc_axi_softc {
struct sdhc_softc sc_sdhc;
/* we have only one slot */
struct sdhc_host *sc_hosts[1];
void *sc_ih;
};
static int sdhc_match(device_t, cfdata_t, void *);
static void sdhc_attach(device_t, device_t, void *);
CFATTACH_DECL_NEW(sdhc_axi, sizeof(struct sdhc_axi_softc),
sdhc_match, sdhc_attach, NULL, NULL);
static int
sdhc_match(device_t parent, cfdata_t cf, void *aux)
{
struct axi_attach_args *aa = aux;
switch (aa->aa_addr) {
case IMX6_AIPS2_BASE + AIPS2_USDHC1_BASE:
case IMX6_AIPS2_BASE + AIPS2_USDHC2_BASE:
case IMX6_AIPS2_BASE + AIPS2_USDHC3_BASE:
case IMX6_AIPS2_BASE + AIPS2_USDHC4_BASE:
return 1;
}
return 0;
}
static void
sdhc_attach(device_t parent, device_t self, void *aux)
{
struct sdhc_axi_softc *sc = device_private(self);
struct axi_attach_args *aa = aux;
bus_space_tag_t iot = aa->aa_iot;
bus_space_handle_t ioh;
u_int perclk = 0, v;
sc->sc_sdhc.sc_dev = self;
sc->sc_sdhc.sc_dmat = aa->aa_dmat;
if (bus_space_map(iot, aa->aa_addr, AIPS2_USDHC_SIZE, 0, &ioh)) {
aprint_error_dev(self, "can't map\n");
return;
}
aprint_normal(": Ultra Secured Digial Host Controller\n");
aprint_naive("\n");
sc->sc_sdhc.sc_host = sc->sc_hosts;
switch (aa->aa_addr) {
case IMX6_AIPS2_BASE + AIPS2_USDHC1_BASE:
v = imx6_ccm_read(CCM_CCGR6);
imx6_ccm_write(CCM_CCGR6, v | CCM_CCGR6_USDHC1_CLK_ENABLE(3));
perclk = imx6_get_clock(IMX6CLK_USDHC1_CLK_ROOT);
break;
case IMX6_AIPS2_BASE + AIPS2_USDHC2_BASE:
v = imx6_ccm_read(CCM_CCGR6);
imx6_ccm_write(CCM_CCGR6, v | CCM_CCGR6_USDHC2_CLK_ENABLE(3));
perclk = imx6_get_clock(IMX6CLK_USDHC2_CLK_ROOT);
break;
case IMX6_AIPS2_BASE + AIPS2_USDHC3_BASE:
v = imx6_ccm_read(CCM_CCGR6);
imx6_ccm_write(CCM_CCGR6, v | CCM_CCGR6_USDHC3_CLK_ENABLE(3));
perclk = imx6_get_clock(IMX6CLK_USDHC3_CLK_ROOT);
break;
case IMX6_AIPS2_BASE + AIPS2_USDHC4_BASE:
v = imx6_ccm_read(CCM_CCGR6);
imx6_ccm_write(CCM_CCGR6, v | CCM_CCGR6_USDHC4_CLK_ENABLE(3));
perclk = imx6_get_clock(IMX6CLK_USDHC4_CLK_ROOT);
break;
}
sc->sc_sdhc.sc_clkbase = perclk / 1000;
sc->sc_sdhc.sc_flags |=
SDHC_FLAG_USDHC |
SDHC_FLAG_NO_PWR0 |
SDHC_FLAG_HAVE_DVS |
SDHC_FLAG_32BIT_ACCESS |
SDHC_FLAG_ENHANCED;
sc->sc_ih = intr_establish(aa->aa_irq, IPL_SDMMC, IST_LEVEL,
sdhc_intr, &sc->sc_sdhc);
if (sc->sc_ih == NULL) {
aprint_error_dev(self, "can't establish interrupt\n");
return;
}
if (sdhc_host_found(&sc->sc_sdhc, iot, ioh, AIPS2_USDHC_SIZE)) {
aprint_error_dev(self, "can't initialize host\n");
return;
}
if (!pmf_device_register1(self, sdhc_suspend, sdhc_resume,
sdhc_shutdown)) {
aprint_error_dev(self,
"can't establish power hook\n");
}
}

63
sys/arch/arm/imx/imx6_wdog.c Normal file
View File

@ -0,0 +1,63 @@
/* $NetBSD: imx6_wdog.c,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*
* Copyright (c) 2010 Genetec Corporation. All rights reserved.
* Written by Hiroyuki Bessho for Genetec Corporation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: imx6_wdog.c,v 1.1 2014/09/25 05:05:28 ryo Exp $");
#include "opt_imx.h"
#include <sys/param.h>
#include <sys/device.h>
#include <sys/bus.h>
#include <arm/imx/imx6var.h>
#include <arm/imx/imx6_reg.h>
#include <arm/imx/imxwdogvar.h>
int
wdog_match(device_t parent, struct cfdata *cf, void *aux)
{
struct axi_attach_args *aa = aux;
switch (aa->aa_addr) {
case IMX6_AIPS1_BASE + AIPS1_WDOG1_BASE:
case IMX6_AIPS1_BASE + AIPS1_WDOG2_BASE:
return 1;
}
return (0);
}
void
wdog_attach(device_t parent, device_t self, void *aux)
{
struct axi_attach_args *aa = aux;
wdog_attach_common(parent, self, aa->aa_iot, aa->aa_addr,
AIPS1_WDOG_SIZE, aa->aa_irq);
}

76
sys/arch/arm/imx/imx6var.h Normal file
View File

@ -0,0 +1,76 @@
/* $NetBSD: imx6var.h,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_IMX_IMX6VAR_H
#define _ARM_IMX_IMX6VAR_H
#include <sys/cdefs.h>
struct axi_attach_args {
const char *aa_name;
bus_space_tag_t aa_iot;
bus_dma_tag_t aa_dmat;
bus_addr_t aa_addr;
bus_size_t aa_size;
int aa_irq;
int aa_irqbase;
};
extern struct bus_space imx_bs_tag;
extern struct arm32_bus_dma_tag imx_bus_dma_tag;
extern bus_space_tag_t imx6_armcore_bst;
extern bus_space_handle_t imx6_armcore_bsh;
/* gpio utility functions in imxgpio.c */
void gpio_set_direction(uint32_t, uint32_t);
void gpio_data_write(uint32_t, uint32_t);
bool gpio_data_read(uint32_t);
/* iomux utility functions in imx6_iomux.c */
struct iomux_conf {
u_int pin;
#define IOMUX_CONF_EOT ((u_int)(-1))
u_short mux;
u_short pad;
};
uint32_t iomux_read(uint32_t);
void iomux_write(uint32_t, uint32_t);
void iomux_set_function(u_int, u_int);
void iomux_set_pad(u_int, u_int);
void iomux_set_input(u_int, u_int);
void iomux_mux_config(const struct iomux_conf *);
/* imx6_board.c */
void imx6_bootstrap(vaddr_t);
psize_t imx6_memprobe(void);
void imx6_reset(void) __dead;
void imx6_device_register(device_t, void *);
void imx6_cpu_hatch(struct cpu_info *);
#endif /* _ARM_IMX_IMX6VAR_H */

9
sys/arch/arm/imx/imxgpio.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: imxgpio.c,v 1.4 2014/03/22 05:19:18 hkenken Exp $ */
/* $NetBSD: imxgpio.c,v 1.5 2014/09/25 05:05:28 ryo Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
@ -29,7 +29,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: imxgpio.c,v 1.4 2014/03/22 05:19:18 hkenken Exp $");
__KERNEL_RCSID(0, "$NetBSD: imxgpio.c,v 1.5 2014/09/25 05:05:28 ryo Exp $");
#define _INTR_PRIVATE
@ -65,7 +65,7 @@ __KERNEL_RCSID(0, "$NetBSD: imxgpio.c,v 1.4 2014/03/22 05:19:18 hkenken Exp $");
#include <dev/gpio/gpiovar.h>
#endif
#define MAX_NGROUP 4
#define MAX_NGROUP 8
static void gpio_pic_block_irqs(struct pic_softc *, size_t, uint32_t);
static void gpio_pic_unblock_irqs(struct pic_softc *, size_t, uint32_t);
@ -352,6 +352,8 @@ imxgpio_attach_common(device_t self, bus_space_tag_t iot,
{
struct gpio_softc * const gpio = device_private(self);
KASSERT(index < MAX_NGROUP);
gpio->gpio_dev = self;
gpio->gpio_memt = iot;
gpio->gpio_memh = ioh;
@ -381,7 +383,6 @@ imxgpio_attach_common(device_t self, bus_space_tag_t iot,
#endif
}
aprint_normal("\n");
gpio_handles.iot = iot;
gpio_handles.unit[index].softc = gpio;

13
sys/arch/arm/imx/imxuart.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: imxuart.c,v 1.14 2014/08/10 16:44:33 tls Exp $ */
/* $NetBSD: imxuart.c,v 1.15 2014/09/25 05:05:28 ryo Exp $ */
/*
* Copyright (c) 2009, 2010 Genetec Corporation. All rights reserved.
@ -96,10 +96,11 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: imxuart.c,v 1.14 2014/08/10 16:44:33 tls Exp $");
__KERNEL_RCSID(0, "$NetBSD: imxuart.c,v 1.15 2014/09/25 05:05:28 ryo Exp $");
#include "opt_imxuart.h"
#include "opt_ddb.h"
#include "opt_ddbparam.h"
#include "opt_kgdb.h"
#include "opt_lockdebug.h"
#include "opt_multiprocessor.h"
@ -1931,6 +1932,14 @@ imxuintr_read(struct imxuart_softc *sc)
rd & 0xff, imxuart_cnm_state);
if (!cn_trapped) {
#if defined(DDB) && defined(DDB_KEYCODE)
/*
* Temporary hack so that I can force the kernel into
* the debugger via the serial port
*/
if ((rd & 0xff) == DDB_KEYCODE)
Debugger();
#endif
sc->sc_rbuf_in = IMXUART_RBUF_INC(sc, sc->sc_rbuf_in, 1);
cc--;
}

11
sys/arch/arm/imx/imxusb.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: imxusb.c,v 1.6 2014/07/25 07:49:56 hkenken Exp $ */
/* $NetBSD: imxusb.c,v 1.7 2014/09/25 05:05:28 ryo Exp $ */
/*
* Copyright (c) 2009, 2010 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi and Hiroyuki Bessho for Genetec Corporation.
@ -25,7 +25,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: imxusb.c,v 1.6 2014/07/25 07:49:56 hkenken Exp $");
__KERNEL_RCSID(0, "$NetBSD: imxusb.c,v 1.7 2014/09/25 05:05:28 ryo Exp $");
#include "opt_imx.h"
@ -91,7 +91,7 @@ imxehci_attach(device_t parent, device_t self, void *aux)
usbd_status r;
uint32_t id, hwhost, hwdevice;
const char *comma;
sc->sc_hsc.sc_dev = self;
iot = sc->sc_iot = sc->sc_hsc.iot = aa->aa_iot;
sc->sc_unit = aa->aa_unit;
@ -99,7 +99,8 @@ imxehci_attach(device_t parent, device_t self, void *aux)
hsc->sc_bus.hci_private = sc;
hsc->sc_flags |= EHCIF_ETTF;
aprint_normal("\n");
aprint_naive("\n");
aprint_normal(": i.MX USB Controller\n");
/* per unit registers */
if (bus_space_subregion(iot, aa->aa_ioh,
@ -118,7 +119,7 @@ imxehci_attach(device_t parent, device_t self, void *aux)
hcirev = bus_space_read_2(iot, sc->sc_hsc.ioh, EHCI_HCIVERSION);
aprint_normal_dev(self,
"i.MX USB Controller id=%d revision=%d HCI revision=0x%x\n",
"id=%d revision=%d HCI revision=0x%x\n",
(int)__SHIFTOUT(id, IMXUSB_ID_ID),
(int)__SHIFTOUT(id, IMXUSB_ID_REVISION),
hcirev);

7
sys/arch/arm/imx/imxwdog.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: imxwdog.c,v 1.2 2014/05/02 03:05:41 hkenken Exp $ */
/* $NetBSD: imxwdog.c,v 1.3 2014/09/25 05:05:28 ryo Exp $ */
/*
* Copyright (c) 2010 Genetec Corporation. All rights reserved.
@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: imxwdog.c,v 1.2 2014/05/02 03:05:41 hkenken Exp $");
__KERNEL_RCSID(0, "$NetBSD: imxwdog.c,v 1.3 2014/09/25 05:05:28 ryo Exp $");
#include "opt_imx.h"
@ -184,6 +184,5 @@ wdog_attach_common(device_t parent, device_t self,
reg |= WCR_WDE;
wdog_write(sc, IMX_WDOG_WCR, reg);
}
}
}
}

23
sys/arch/arm/imx/imxwdogreg.h
View File

@ -27,7 +27,7 @@
*/
/*
* Watchdog register definitions for Freescale i.MX31 and i.MX51
* Watchdog register definitions for Freescale i.MX31/i.MX51/i.MX6
*
* MCIMX31 and MCIMX31L Application Processors
* Reference Manual
@ -36,10 +36,16 @@
* 1/2007
*
* MCIMX51 Multimedia Applications Processor
* Reference Manual
* MCIMX51RM
* Rev. 1
* 2/2010
* Reference Manual
* MCIMX51RM
* Rev. 1
* 2/2010
*
* i.MX 6Dual/6Quad Applications Processor
* Reference Manual
* IMX6DQRM
* Rev. 1
* 4/2013
*/
#ifndef _ARM_IMX_IMXWDOGREG_H
@ -69,16 +75,17 @@
/* only for i.MX31 */
#define WRSR_CMON __BIT(2)
#define WRSR_EXT __BIT(3)
#define WRSR_PWR __BIT(4)
#define WRSR_JRST __BIT(5)
/* i.MX31 and iMX6 */
#define WRSR_PWR __BIT(4)
/* only for i.MX51 */
/* only for i.MX51 and i.MX6 */
#define IMX_WDOG_WICR 0x0006 /* Watchdog Interrupt Control Register */
#define WICR_WICT __BITS(7,0) /* interrupt count timeout */
#define WICR_WTIS __BIT(14) /* interrupt status [w1c] */
#define WICR_WIE __BIT(15) /* interrupt enable */
/* only for i.MX51 */
/* only for i.MX51 and i.MX6 */
#define IMX_WDOG_WMCR 0x0008
#define WMCR_PDE __BIT(0) /* power down enable */

427
sys/arch/evbarm/conf/NITROGEN6X Normal file
View File

@ -0,0 +1,427 @@
# $NetBSD: NITROGEN6X,v 1.1 2014/09/25 05:05:28 ryo Exp $
#
# Nitrogen6X
# - http://boundarydevices.com/products/nitrogen6x-board-imx6-arm-cortex-a9-sbc/
#
include "arch/evbarm/conf/std.nitrogen6"
#options INCLUDE_CONFIG_FILE # embed config file in kernel binary
# estimated number of users
maxusers 32
# CPU options
options CPU_CORTEX
options CPU_CORTEXA9
options IMX6
options MULTIPROCESSOR
options PMAPCOUNTERS
# Standard system options
options INSECURE # disable kernel security levels - X needs this
options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
#options NTP # NTP phase/frequency locked loop
options KTRACE # system call tracing via ktrace(1)
# Note: SysV IPC parameters can be changed dynamically; see sysctl(8).
options SYSVMSG # System V-like message queues
options SYSVSEM # System V-like semaphores
options SYSVSHM # System V-like memory sharing
#options USERCONF # userconf(4) support
#options PIPE_SOCKETPAIR # smaller, but slower pipe(2)
options SYSCTL_INCLUDE_DESCR # Include sysctl descriptions in kernel
# Alternate buffer queue strategies for better responsiveness under high
# disk I/O load.
#options BUFQ_READPRIO
options BUFQ_PRIOCSCAN
# Diagnostic/debugging support options
options VERBOSE_INIT_ARM # verbose bootstraping messages
#options PERFCTRS # performance counters
options DIAGNOSTIC # internally consistency checks
#options DEBUG
#options PMAP_DEBUG # Enable pmap_debug_level code
options LOCKDEBUG # expensive locking checks/support
options KMEMSTATS # kernel memory statistics (vmstat -m)
options IRQSTATS # manage IRQ statistics
#options NO_POWERSAVE # uncomment this to run under ICE
#makeoptions COPTS="-O2"
options DDB # in-kernel debugger
options DDB_KEYCODE=0x1d # ^]
#options DDB_COMMANDONENTER="bt" # execute command when ddb is entered
options DDB_ONPANIC=1 # see also sysctl(7): `ddb.onpanic'
options DDB_HISTORY_SIZE=100 # Enable history editing in DDB
options DDB_VERBOSE_HELP
#options IPKDB # remote kernel debugging
#options KGDB
#options KGDB_DEVNAME="\"imxuart\""
#options KGDB_DEVADDR=0x021e8000
#options KGDB_DEVRATE=115200
makeoptions DEBUG="-g" # compile full symbol table
makeoptions COPY_SYMTAB=1
#options SYSCALL_STATS # per syscall counts
#options SYSCALL_TIMES # per syscall times
#options SYSCALL_TIMES_HASCOUNTER # use 'broken' rdtsc (soekris)
# Compatibility options
options COMPAT_NETBSD32 # allow running arm (e.g. non-earm) binaries
#options COMPAT_43 # 4.3BSD compatibility.
#options COMPAT_09 # NetBSD 0.9,
#options COMPAT_10 # NetBSD 1.0,
#options COMPAT_11 # NetBSD 1.1,
#options COMPAT_12 # NetBSD 1.2,
#options COMPAT_13 # NetBSD 1.3,
#options COMPAT_14 # NetBSD 1.4,
#options COMPAT_15 # NetBSD 1.5,
#options COMPAT_16 # NetBSD 1.6,
#options COMPAT_20 # NetBSD 2.0,
#options COMPAT_30 # NetBSD 3.0,
#options COMPAT_40 # NetBSD 4.0,
#options COMPAT_50 # NetBSD 5.0,
options COMPAT_60 # NetBSD 6.0, and
options COMPAT_70 # NetBSD 7.0 binary compatibility.
#options TCP_COMPAT_42 # 4.2BSD TCP/IP bug compat. Not recommended.
options COMPAT_OSSAUDIO # OSS (Voxware) audio driver compatibility
#options COMPAT_NDIS # NDIS network driver
options COMPAT_BSDPTY # /dev/[pt]ty?? ptys.
# Wedge support
options DKWEDGE_AUTODISCOVER # Automatically add dk(4) instances
options DKWEDGE_METHOD_GPT # Supports GPT partitions as wedges
# File systems
file-system FFS # UFS
file-system MFS # memory file system
file-system NFS # Network File System client
file-system TMPFS # Efficient memory file-system
file-system EXT2FS # second extended file system (linux)
file-system LFS # log-structured file system
file-system NTFS # Windows/NT file system (experimental)
file-system CD9660 # ISO 9660 + Rock Ridge file system
file-system MSDOSFS # MS-DOS file system
file-system FDESC # /dev/fd
file-system KERNFS # /kern
file-system NULLFS # loopback file system
file-system OVERLAY # overlay file system
file-system PROCFS # /proc
file-system PUFFS # Userspace file systems (e.g. ntfs-3g & sshfs)
file-system SMBFS # experimental - CIFS; also needs nsmb (below)
file-system UMAPFS # NULLFS + uid and gid remapping
file-system UNION # union file system
file-system CODA # Coda File System; also needs vcoda (below)
file-system PTYFS # /dev/ptm support
#file-system UDF # experimental - OSTA UDF CD/DVD file-system
#file-system HFS # experimental - Apple HFS+ (read-only)
#file-system NILFS # experimental - NTT's NiLFS(2)
# File system options
options QUOTA # legacy UFS quotas
options QUOTA2 # new, in-filesystem UFS quotas
options FFS_EI # FFS Endian Independent support
options WAPBL # File system journaling support
# Note that UFS_DIRHASH is suspected of causing kernel memory corruption.
# It is not recommended for general use.
#options UFS_DIRHASH # UFS Large Directory Hashing - Experimental
options NFSSERVER # Network File System server
#options EXT2FS_SYSTEM_FLAGS # makes ext2fs file flags (append and
# immutable) behave as system flags.
#options FFS_NO_SNAPSHOT # No FFS snapshot support
# Networking options
#options GATEWAY # packet forwarding
options INET # IP + ICMP + TCP + UDP
options INET6 # IPv6
options IPSEC # IP security
#options IPSEC_DEBUG # debug for IP security
#options MPLS # MultiProtocol Label Switching (needs ifmpls)
#options MROUTING # IP multicast routing
#options PIM # Protocol Independent Multicast
options NETATALK # AppleTalk networking protocols
options PPP_BSDCOMP # BSD-Compress compression support for PPP
options PPP_DEFLATE # Deflate compression support for PPP
options PPP_FILTER # Active filter support for PPP (requires bpf)
options IPFILTER_LOG # ipmon(8) log support
options IPFILTER_LOOKUP # ippool(8) support
options IPFILTER_COMPAT # Compat for IP-Filter
#options IPFILTER_DEFAULT_BLOCK # block all packets by default
#options TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG
#options ALTQ # Manipulate network interfaces' output queues
#options ALTQ_BLUE # Stochastic Fair Blue
#options ALTQ_CBQ # Class-Based Queueing
#options ALTQ_CDNR # Diffserv Traffic Conditioner
#options ALTQ_FIFOQ # First-In First-Out Queue
#options ALTQ_FLOWVALVE # RED/flow-valve (red-penalty-box)
#options ALTQ_HFSC # Hierarchical Fair Service Curve
#options ALTQ_LOCALQ # Local queueing discipline
#options ALTQ_PRIQ # Priority Queueing
#options ALTQ_RED # Random Early Detection
#options ALTQ_RIO # RED with IN/OUT
#options ALTQ_WFQ # Weighted Fair Queueing
# Device options
# Console options. also need IMXUARTCONSOLE
options CONSDEVNAME="\"imxuart\"",CONADDR=0x021e8000,CONSPEED=115200
options CONS_OVERRIDE
# These options enable verbose messages for several subsystems.
# Warning, these may compile large string tables into the kernel!
options MIIVERBOSE # verbose PHY autoconfig messages
#options PCIVERBOSE # verbose PCI device autoconfig messages
#options PCI_CONFIG_DUMP # verbosely dump PCI config space
#options PCMCIAVERBOSE # verbose PCMCIA configuration messages
#options SCSIVERBOSE # Verbose SCSI errors
options USBVERBOSE # verbose USB device autoconfig messages
# Kernel root file system and dump configuration.
config netbsd root on wd0a type ?
#
# Device configuration
#
mainbus0 at root
cpu* at mainbus?
# The MPCore interrupt controller and global timer
armperiph0 at mainbus? # A9 On-Chip Peripherals
armgic0 at armperiph? # ARM Generic Interrupt Controller
arml2cc0 at armperiph? flags 0 # ARM PL310 L2CC
a9tmr0 at armperiph? # A9 Global Timer
#a9wdt0 at armperiph? flags 0 # A9 Watchdog Timer
axi0 at mainbus?
# Enhanced Periodic Interrupt Timer
#imxclock0 at axi? addr 0x020d0000 irq 88
#imxclock1 at axi? addr 0x020d4000 irq 89
# GPIO
imxgpio0 at axi? addr 0x0209c000 irqbase 256 irq 98
imxgpio1 at axi? addr 0x020a0000 irqbase 288 irq 100
imxgpio2 at axi? addr 0x020a4000 irqbase 320 irq 102
imxgpio3 at axi? addr 0x020a8000 irqbase 352 irq 104
imxgpio4 at axi? addr 0x020ac000 irqbase 384 irq 106
imxgpio5 at axi? addr 0x020b0000 irqbase 416 irq 108
imxgpio6 at axi? addr 0x020b4000 irqbase 448 irq 110
gpio* at imxgpio?
options IMX_GPIO_INTR_SPLIT
# Clock Control
imxccm0 at axi? addr 0x020c4000
# On-Chip OTP Controller
imxocotp0 at axi? addr 0x021bc000
# IOMUX
imxiomux0 at axi? addr 0x020e0000
# WatchDog
imxwdog0 at axi? addr 0x020bc000 irq 112 flags 0
#imxwdog1 at axi? addr 0x020c0000 irq 113 flags 0
# Serial
imxuart0 at axi? addr 0x02020000 irq 58 # UART1
imxuart1 at axi? addr 0x021e8000 irq 59 # UART2
#imxuart2 at axi? addr 0x021ec000 irq 60 # UART3
#imxuart3 at axi? addr 0x021f0000 irq 61 # UART4
#imxuart4 at axi? addr 0x021f4000 irq 62 # UART5
options IMXUARTCONSOLE
# SATA
ahcisata* at axi? addr 0x02200000 irq 71
atabus* at ahcisata? channel ?
wd* at atabus? drive ? flags 0x0000
# ATAPI bus support
atapibus* at atapi?
# ATAPI devices
# flags have the same meaning as for IDE drives.
cd* at atapibus? drive ? flags 0x0000 # ATAPI CD-ROM drives
sd* at atapibus? drive ? flags 0x0000 # ATAPI disk drives
st* at atapibus? drive ? flags 0x0000 # ATAPI tape drives
uk* at atapibus? drive ? flags 0x0000 # ATAPI unknown
# Network Interfaces
enet0 at axi? addr 0x02188000 irq 150 # iMX6 SoC Ethernet
# MII/PHY support
acphy* at mii? phy ? # DAltima AC101 and AMD Am79c874 PHYs
amhphy* at mii? phy ? # AMD 79c901 Ethernet PHYs
atphy* at mii? phy ? # Attansic/Atheros PHYs
bmtphy* at mii? phy ? # Broadcom BCM5201 and BCM5202 PHYs
brgphy* at mii? phy ? # Broadcom BCM5400-family PHYs
ciphy* at mii? phy ? # Cicada CS8201 Gig-E PHYs
dmphy* at mii? phy ? # Davicom DM9101 PHYs
etphy* at mii? phy ? # Agere/LSI ET1011 TruePHY Gig-E PHYs
exphy* at mii? phy ? # 3Com internal PHYs
gentbi* at mii? phy ? # Generic Ten-Bit 1000BASE-[CLS]X PHYs
glxtphy* at mii? phy ? # Level One LXT-1000 PHYs
gphyter* at mii? phy ? # NS83861 Gig-E PHY
icsphy* at mii? phy ? # Integrated Circuit Systems ICS189x
igphy* at mii? phy ? # Intel IGP01E1000
ihphy* at mii? phy ? # Intel 82577 PHYs
ikphy* at mii? phy ? # Intel 82563 PHYs
inphy* at mii? phy ? # Intel 82555 PHYs
iophy* at mii? phy ? # Intel 82553 PHYs
lxtphy* at mii? phy ? # Level One LXT-970 PHYs
makphy* at mii? phy ? # Marvell Semiconductor 88E1000 PHYs
micphy* at mii? phy ? # Micrel KSZ9021RNI PHYs
nsphy* at mii? phy ? # NS83840 PHYs
nsphyter* at mii? phy ? # NS83843 PHYs
pnaphy* at mii? phy ? # generic HomePNA PHYs
qsphy* at mii? phy ? # Quality Semiconductor QS6612 PHYs
rgephy* at mii? phy ? # Realtek 8169S/8110 internal PHYs
rlphy* at mii? phy ? # Realtek 8139/8201L PHYs
sqphy* at mii? phy ? # Seeq 80220/80221/80223 PHYs
tlphy* at mii? phy ? # ThunderLAN PHYs
tqphy* at mii? phy ? # TDK Semiconductor PHYs
ukphy* at mii? phy ? # generic unknown PHYs
urlphy* at mii? phy ? # Realtek RTL8150L internal PHYs
# USB Controller and Devices
imxusbc0 at axi? addr 0x02184000
ehci0 at imxusbc0 unit 0 irq 75 # OTG
ehci1 at imxusbc0 unit 1 irq 72 # Host1
#ehci2 at imxusbc0 unit 2 irq 73 # Host2
#ehci3 at imxusbc0 unit 3 irq 74 # Host3
usb* at ehci?
# USB device drivers
include "dev/usb/usbdevices.config"
# SD/MMC controller
#sdhc0 at axi? addr 0x02190000 irq 54 # uSDHC1
#sdhc1 at axi? addr 0x02194000 irq 55 # uSDHC2
#sdhc2 at axi? addr 0x02198000 irq 56 # uSDHC3
#sdhc3 at axi? addr 0x0219c000 irq 57 # uSDHC4
#sdmmc* at sdhc?
#options SDHC_DEBUG
#options SDMMC_DEBUG
#
#ld* at sdmmc? # MMC/SD card
# Pseudo-Devices
pseudo-device crypto # /dev/crypto device
pseudo-device swcrypto # software crypto implementation
# disk/mass storage pseudo-devices
pseudo-device bio # RAID control device driver
pseudo-device ccd # concatenated/striped disk devices
pseudo-device cgd # cryptographic disk devices
pseudo-device raid # RAIDframe disk driver
#options RAID_AUTOCONFIG # auto-configuration of RAID components
#Options to enable various other RAIDframe RAID types.
#options RF_INCLUDE_EVENODD=1
#options RF_INCLUDE_RAID5_RS=1
#options RF_INCLUDE_PARITYLOGGING=1
#options RF_INCLUDE_CHAINDECLUSTER=1
#options RF_INCLUDE_INTERDECLUSTER=1
#options RF_INCLUDE_PARITY_DECLUSTERING=1
#options RF_INCLUDE_PARITY_DECLUSTERING_DS=1
pseudo-device fss # file system snapshot device
pseudo-device putter # for puffs and pud
pseudo-device md # memory disk device (ramdisk)
options MEMORY_DISK_HOOKS # enable root ramdisk
options MEMORY_DISK_DYNAMIC # loaded via kernel module(7)
pseudo-device vnd # disk-like interface to files
options VND_COMPRESSION # compressed vnd(4)
# network pseudo-devices
pseudo-device bpfilter # Berkeley packet filter
#pseudo-device carp # Common Address Redundancy Protocol
#pseudo-device ipfilter # IP filter (firewall) and NAT
pseudo-device loop # network loopback
#pseudo-device ifmpls # MPLS pseudo-interface
pseudo-device ppp # Point-to-Point Protocol
pseudo-device pppoe # PPP over Ethernet (RFC 2516)
pseudo-device sl # Serial Line IP
pseudo-device strip # Starmode Radio IP (Metricom)
pseudo-device irframetty # IrDA frame line discipline
pseudo-device tun # network tunneling over tty
pseudo-device tap # virtual Ethernet
pseudo-device gre # generic L3 over IP tunnel
pseudo-device gif # IPv[46] over IPv[46] tunnel (RFC1933)
#pseudo-device faith # IPv[46] tcp relay translation i/f
pseudo-device stf # 6to4 IPv6 over IPv4 encapsulation
pseudo-device vlan # IEEE 802.1q encapsulation
pseudo-device bridge # simple inter-network bridging
#options BRIDGE_IPF # bridge uses IP/IPv6 pfil hooks too
pseudo-device agr # IEEE 802.3ad link aggregation
#pseudo-device pf # PF packet filter
#pseudo-device pflog # PF log if
#pseudo-device pfsync # PF sync if
#pseudo-device npf # NPF packet filter
#
# accept filters
pseudo-device accf_data # "dataready" accept filter
pseudo-device accf_http # "httpready" accept filter
# miscellaneous pseudo-devices
pseudo-device pty # pseudo-terminals
pseudo-device sequencer # MIDI sequencer
# rnd works; RND_COM does not on port i386 yet.
#options RND_COM # use "com" randomness as well (BROKEN)
pseudo-device clockctl # user control of clock subsystem
pseudo-device ksyms # /dev/ksyms
pseudo-device lockstat # lock profiling
pseudo-device bcsp # BlueCore Serial Protocol
pseudo-device btuart # Bluetooth HCI UART (H4)
# a pseudo device needed for Coda # also needs CODA (above)
pseudo-device vcoda # coda minicache <-> venus comm.
# a pseudo device needed for SMBFS
pseudo-device nsmb # experimental - SMB requester
# wscons pseudo-devices
pseudo-device wsmux # mouse & keyboard multiplexor
pseudo-device wsfont
# pseudo audio device driver
#pseudo-device pad
# userland interface to drivers, including autoconf and properties retrieval
pseudo-device drvctl
options FILEASSOC # fileassoc(9) - required for Veriexec
# Veriexec
#
# a pseudo device needed for veriexec
pseudo-device veriexec
#
# Uncomment the fingerprint methods below that are desired. Note that
# removing fingerprint methods will have almost no impact on the kernel
# code size.
#
options VERIFIED_EXEC_FP_RMD160
options VERIFIED_EXEC_FP_SHA256
options VERIFIED_EXEC_FP_SHA384
options VERIFIED_EXEC_FP_SHA512
options VERIFIED_EXEC_FP_SHA1
options VERIFIED_EXEC_FP_MD5
options PAX_MPROTECT=0 # PaX mprotect(2) restrictions
options PAX_ASLR=0 # PaX Address Space Layout Randomization

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# $NetBSD: files.nitrogen6,v 1.1 2014/09/25 05:05:28 ryo Exp $
#
# Nitrogen6X
#
file arch/evbarm/nitrogen6/nitrogen6_machdep.c
# Kernel boot arguments
defparam opt_machdep.h BOOT_ARGS
# CPU support and integrated peripherals
include "arch/arm/imx/files.imx6"
device imxusbc_axi
attach imxusbc at axi with imxusbc_axi
file arch/evbarm/nitrogen6/nitrogen6_usb.c imxusbc_axi

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# $NetBSD: mk.nitrogen6,v 1.1 2014/09/25 05:05:28 ryo Exp $
SYSTEM_FIRST_OBJ= nitrogen6_start.o
SYSTEM_FIRST_SFILE= ${THISARM}/nitrogen6/nitrogen6_start.S
GENASSYM_EXTRAS+= ${THISARM}/nitrogen6/genassym.cf
_OSRELEASE!= ${HOST_SH} $S/conf/osrelease.sh
KERNEL_BASE_PHYS?=$(LOADADDRESS)
KERNEL_BASE_VIRT?=$(LOADADDRESS)
MKUBOOTIMAGEARGS= -A arm -T kernel
MKUBOOTIMAGEARGS+= -a $(KERNEL_BASE_PHYS) -e $(KERNEL_BASE_PHYS)
MKUBOOTIMAGEARGS+= -n "NetBSD/$(BOARDTYPE) ${_OSRELEASE}"
MKUBOOTIMAGEARGS_NONE= ${MKUBOOTIMAGEARGS} -C none
MKUBOOTIMAGEARGS_GZ= ${MKUBOOTIMAGEARGS} -C gz
SYSTEM_LD_TAIL_EXTRA+=; \
echo ${OBJCOPY} -S -O binary $@ $@.bin; \
${OBJCOPY} -S -O binary $@ $@.bin; \
EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.bin@}

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# $NetBSD: std.nitrogen6,v 1.1 2014/09/25 05:05:28 ryo Exp $
#
# standard NetBSD/evbarm options for Nitrogen6X
machine evbarm arm
include "arch/evbarm/conf/std.evbarm"
# Pull in nitrogen6 config definitions.
include "arch/evbarm/conf/files.nitrogen6"
options NITROGEN6
options ARM_HAS_VBAR
options PMAP_NEED_ALLOC_POOLPAGE
options __HAVE_CPU_COUNTER
options __HAVE_FAST_SOFTINTS # should be in types.h
options __HAVE_MM_MD_DIRECT_MAPPED_PHYS
options TPIDRPRW_IS_CURCPU
makeoptions CPUFLAGS="-mcpu=cortex-a9"
# To support easy transit to ../arch/arm/arm32
options FPU_VFP
options CORTEX_PMC
options CORTEX_PMC_CCNT_HZ=792000000
options EVBARM_BOARDTYPE="nitrogen6"
options KERNEL_BASE_EXT=0x80000000
makeoptions KERNEL_BASE_PHYS="0x10800000"
makeoptions KERNEL_BASE_VIRT="0x80800000"
makeoptions BOARDMKFRAG="${THISARM}/conf/mk.nitrogen6"
makeoptions CPPFLAGS+="-I$S/../../../include"
options ARM_INTR_IMPL="<arch/arm/imx/imx6_intr.h>"
options ARM_GENERIC_TODR

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# $NetBSD: genassym.cf,v 1.1 2014/09/25 05:05:28 ryo Exp $
#-
# Copyright (c) 2012 The NetBSD Foundation, Inc.
# All rights reserved.
#
# This code is derived from software contributed to The NetBSD Foundation
# by Nick Hudson
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
# ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
include <evbarm/nitrogen6/platform.h>
include <arm/imx/imx6_reg.h>
include <arm/imx/imx6_srcreg.h>
include <arm/imx/imxuartreg.h>
define IMX6_IOREG_PBASE IMX6_IOREG_PBASE
define IMX6_IOREG_SIZE IMX6_IOREG_SIZE
define IMX6_ARMCORE_PBASE IMX6_MPCORE_BASE
define IMX6_ARMCORE_SIZE IMX6_MPCORE_SIZE
define KERNEL_IO_IOREG_VBASE KERNEL_IO_IOREG_VBASE
define KERNEL_IO_ARMCORE_VBASE KERNEL_IO_ARMCORE_VBASE
define LSR_TXRDY IMX_USR2_TXDC
define LSR_TSRE IMX_USR2_TXDC
define COM_DATA IMX_UTXD
define COM_LSR (IMX_USR2/4)
define IMX6_AIPS1_BASE IMX6_AIPS1_BASE
define AIPS1_SRC_BASE AIPS1_SRC_BASE
define SRC_SCR SRC_SCR
define SRC_SCR_CORE1_ENABLE SRC_SCR_CORE1_ENABLE
define SRC_SCR_CORE2_ENABLE SRC_SCR_CORE2_ENABLE
define SRC_SCR_CORE3_ENABLE SRC_SCR_CORE3_ENABLE
define SRC_SCR_CORE1_RST SRC_SCR_CORE1_RST
define SRC_SCR_CORE2_RST SRC_SCR_CORE2_RST
define SRC_SCR_CORE3_RST SRC_SCR_CORE3_RST
define SRC_GPR3 SRC_GPR3
define SRC_GPR5 SRC_GPR5
define SRC_GPR7 SRC_GPR7

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/* $NetBSD: nitrogen6_machdep.c,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Matt Thomas of 3am Software Foundry.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: nitrogen6_machdep.c,v 1.1 2014/09/25 05:05:28 ryo Exp $");
#include "opt_evbarm_boardtype.h"
#include "opt_arm_debug.h"
#include "opt_kgdb.h"
#include "com.h"
#include "opt_machdep.h"
#include "opt_imxuart.h"
#include "imxuart.h"
#include "opt_imx.h"
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/atomic.h>
#include <sys/device.h>
#include <sys/kernel.h>
#include <sys/msgbuf.h>
#include <sys/reboot.h>
#include <sys/termios.h>
#include <dev/cons.h>
#include <uvm/uvm_extern.h>
#include <arm/db_machdep.h>
#include <arm/arm32/machdep.h>
#include <machine/autoconf.h>
#include <machine/bootconfig.h>
#include <arm/cortex/scu_reg.h>
#include <arm/imx/imx6var.h>
#include <arm/imx/imxuartvar.h>
#include <evbarm/nitrogen6/platform.h>
extern int _end[];
extern int KERNEL_BASE_phys[];
extern int KERNEL_BASE_virt[];
BootConfig bootconfig;
static char bootargs[MAX_BOOT_STRING];
char *boot_args = NULL;
u_int uboot_args[4] = { 0 };
/*
* Macros to translate between physical and virtual for a subset of the
* kernel address space. *Not* for general use.
*/
#define KERN_VTOPDIFF ((vaddr_t)KERNEL_BASE_phys - (vaddr_t)KERNEL_BASE_virt)
#define KERN_VTOPHYS(va) ((paddr_t)((vaddr_t)va + (vaddr_t)KERN_VTOPDIFF))
#define KERN_PHYSTOV(pa) ((vaddr_t)((paddr_t)pa - (vaddr_t)KERN_VTOPDIFF))
#ifndef CONADDR
#define CONADDR (IMX6_AIPS2_BASE + AIPS2_UART1_BASE)
#endif
#ifndef CONSPEED
#define CONSPEED B115200
#endif
#ifndef CONMODE
#define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */
#endif
static const bus_addr_t comcnaddr = (bus_addr_t)CONADDR;
static const int comcnspeed = CONSPEED;
static const int comcnmode = CONMODE | CLOCAL;
#ifdef KGDB
#include <sys/kgdb.h>
#endif
/*
* Static device mappings. These peripheral registers are mapped at
* fixed virtual addresses very early in initarm() so that we can use
* them while booting the kernel, and stay at the same address
* throughout whole kernel's life time.
*
* We use this table twice; once with bootstrap page table, and once
* with kernel's page table which we build up in initarm().
*
* Since we map these registers into the bootstrap page table using
* pmap_devmap_bootstrap() which calls pmap_map_chunk(), we map
* registers segment-aligned and segment-rounded in order to avoid
* using the 2nd page tables.
*/
static const struct pmap_devmap devmap[] = {
{
KERNEL_IO_IOREG_VBASE,
IMX6_IOREG_PBASE, /* 0x02000000 */
IMX6_IOREG_SIZE,
VM_PROT_READ | VM_PROT_WRITE,
PTE_NOCACHE,
},
{
KERNEL_IO_ARMCORE_VBASE,
IMX6_ARMCORE_PBASE, /* 0x00a00000 */
IMX6_ARMCORE_SIZE,
VM_PROT_READ | VM_PROT_WRITE,
PTE_NOCACHE,
},
{ 0, 0, 0, 0, 0 }
};
/*
* u_int initarm(...)
*
* Initial entry point on startup. This gets called before main() is
* entered.
* It should be responsible for setting up everything that must be
* in place when main is called.
* This includes
* Taking a copy of the boot configuration structure.
* Initialising the physical console so characters can be printed.
* Setting up page tables for the kernel
*/
u_int
initarm(void *arg)
{
psize_t memsize;
pmap_devmap_register(devmap);
imx6_bootstrap(KERNEL_IO_IOREG_VBASE);
#ifdef MULTIPROCESSOR
uint32_t scu_cfg = bus_space_read_4(imx6_armcore_bst, imx6_armcore_bsh,
ARMCORE_SCU_BASE + SCU_CFG);
arm_cpu_max = (scu_cfg & SCU_CFG_CPUMAX) + 1;
membar_producer();
#endif /* MULTIPROCESSOR */
consinit();
/*
* Heads up ... Setup the CPU / MMU / TLB functions
*/
if (set_cpufuncs()) // starts PMC counter
panic("cpu not recognized!");
cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
#ifdef NO_POWERSAVE
cpu_do_powersave = 0;
#endif
cortex_pmc_ccnt_init();
printf("\nuboot arg = %#x, %#x, %#x, %#x\n",
uboot_args[0], uboot_args[1], uboot_args[2], uboot_args[3]);
cpu_reset_address = imx6_reset;
/* Talk to the user */
printf("\nNetBSD/evbarm (" ___STRING(EVBARM_BOARDTYPE) ") booting ...\n");
#ifdef BOOT_ARGS
char mi_bootargs[] = BOOT_ARGS;
parse_mi_bootargs(mi_bootargs);
#endif /* BOOT_ARGS */
bootargs[0] = '\0';
#ifdef VERBOSE_INIT_ARM
printf("initarm: Configuring system");
#ifdef MULTIPROCESSOR
printf(" (%u cpu%s, hatched %#x)",
arm_cpu_max, arm_cpu_max ? "s" : "",
arm_cpu_hatched);
#endif /* MULTIPROCESSOR */
printf(", CLIDR=%010o CTR=%#x",
armreg_clidr_read(), armreg_ctr_read());
printf("\n");
#endif /* VERBOSE_INIT_ARM */
#ifdef MEMSIZE
memsize = MEMSIZE * 1024 * 1024;
#else
memsize = imx6_memprobe();
#endif
bootconfig.dramblocks = 1;
bootconfig.dram[0].address = KERN_VTOPHYS(KERNEL_BASE);
bootconfig.dram[0].pages = memsize / PAGE_SIZE;
arm32_bootmem_init(bootconfig.dram[0].address,
bootconfig.dram[0].pages * PAGE_SIZE, (paddr_t)KERNEL_BASE_phys);
/*
* This is going to do all the hard work of setting up the first and
* and second level page tables. Pages of memory will be allocated
* and mapped for other structures that are required for system
* operation. When it returns, physical_freestart and free_pages will
* have been updated to reflect the allocations that were made. In
* addition, kernel_l1pt, kernel_pt_table[], systempage, irqstack,
* abtstack, undstack, kernelstack, msgbufphys will be set to point to
* the memory that was allocated for them.
*/
arm32_kernel_vm_init(KERNEL_VM_BASE, ARM_VECTORS_HIGH, 0, devmap, true);
/* we've a specific device_register routine */
evbarm_device_register = imx6_device_register;
return initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0);
}
#ifdef CONSDEVNAME
const char consdevname[] = CONSDEVNAME;
#ifndef CONMODE
#define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */
#endif
#ifndef CONSPEED
#define CONSPEED 115200
#endif
int consmode = CONMODE;
int consrate = CONSPEED;
#endif /* CONSDEVNAME */
#ifndef IMXUART_FREQ
#define IMXUART_FREQ 80000000
#endif
void
consinit(void)
{
static int consinit_called = 0;
if (consinit_called)
return;
consinit_called = 1;
#ifdef CONSDEVNAME
# if NIMXUART > 0
imxuart_set_frequency(IMXUART_FREQ, 2);
# endif
# if (NIMXUART > 0) && defined(IMXUARTCONSOLE)
if (strcmp(consdevname, CONSDEVNAME) == 0) {
paddr_t consaddr;
consaddr = CONADDR;
imxuart_cons_attach(&imx_bs_tag, consaddr, consrate, consmode);
return;
}
# endif /* (NIMXUART > 0) && defined(IMXUARTCONSOLE) */
#endif /* CONSDEVNAME */
}

355
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/* $NetBSD: nitrogen6_start.S,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*-
* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include "opt_imx.h"
#include "opt_cpuoptions.h"
#include "opt_cputypes.h"
#include "opt_multiprocessor.h"
#include "opt_arm_debug.h"
#include <arm/asm.h>
#include <arm/armreg.h>
#include <arm/cortex/scu_reg.h>
#include "assym.h"
RCSID("$NetBSD: nitrogen6_start.S,v 1.1 2014/09/25 05:05:28 ryo Exp $")
#ifndef CONADDR
#define CONADDR 0x021e8000
#endif
#define COM_MULT 4
#define BOOT_MEMSIZE 256 /* temporary for boot up kernel */
#define TEMP_L1_TABLE (KERNEL_BASE - KERNEL_BASE_VOFFSET + \
BOOT_MEMSIZE * 0x100000 - L1_TABLE_SIZE)
#define MD_CPU_HATCH _C_LABEL(imx6_cpu_hatch)
#ifdef VERBOSE_INIT_ARM
# define XPUTC_COM 1
# define XPUTC(n) mov r0, n; bl xputc
# define XPUTC2(n) mov r0, n; blx r11
# define PRINT(str) bl xprint; .ascii str, "\0"; .align 2
# define PRINT_R0 bl print_r0
#else
# define XPUTC(n)
# define XPUTC2(n)
# define PRINT(str)
# define PRINT_R0
#endif /* VERBOSE_INIT_ARM */
/*
* Kernel start routine for NITROGEN6X boards.
* At this point, this code has been loaded into SDRAM
* and the MMU is off
*/
.section .start,"ax",%progbits
.global _C_LABEL(nitrogen6_start)
_C_LABEL(nitrogen6_start):
/*
* Save any arguments u-boot passed us.
*/
movw r4, #:lower16:uboot_args
movt r4, #:upper16:uboot_args
#if KERNEL_BASE_VOFFSET != 0
sub r4, r4, #KERNEL_BASE_VOFFSET
#endif
stmia r4, {r0-r3}
#ifdef VERBOSE_INIT_ARM
PRINT(" PC=")
mov r0, pc
PRINT_R0
PRINT(" SP=")
mov r0, sp
PRINT_R0
PRINT("CPSR=")
mrs r0, cpsr
PRINT_R0
#endif /* VERBOSE_INIT_ARM */
/* set temporary stack */
movw sp, #:lower16:tmpstack
movt sp, #:upper16:tmpstack
PRINT("<cortex_init>")
bl cortex_init
PRINT("</cortex_init>\r\n")
/*
* Set up a preliminary mapping in the MMU to allow us to run
* at KERNEL_BASE with caches on.
*/
PRINT("<mmu_init_table>")
movw r1, #:lower16:mmu_init_table
movt r1, #:upper16:mmu_init_table
movw r0, #:lower16:TEMP_L1_TABLE
movt r0, #:upper16:TEMP_L1_TABLE
bl arm_boot_l1pt_init
PRINT("</mmu_init_table>\r\n")
/*
* init the CPU TLB, Cache, MMU.
*/
PRINT("<arm_cpuinit>")
#ifdef VERBOSE_INIT_ARM
adr r11, xputc
#endif
movw r0, #:lower16:TEMP_L1_TABLE
movt r0, #:upper16:TEMP_L1_TABLE
bl arm_cpuinit
PRINT("</arm_cpuinit>\r\n")
#ifdef MULTIPROCESSOR
movw r1, #:lower16:IMX6_AIPS1_BASE+AIPS1_SRC_BASE
movt r1, #:upper16:IMX6_AIPS1_BASE+AIPS1_SRC_BASE
/* disable core1,2,3 */
ldr r2, [r1, #SRC_SCR]
and r2, r2, #~(SRC_SCR_CORE1_ENABLE| \
SRC_SCR_CORE2_ENABLE| \
SRC_SCR_CORE3_ENABLE)
str r2, [r1, #SRC_SCR]
/* get number of CPU core */
mrc p15, 4, r0, c15, c0, 0 /* read SCU base addr */
#ifdef __ARMEB__
setend le
#endif
ldr r0, [r0, #SCU_CFG]
#ifdef __ARMEB__
setend be
#endif
and r0, r0, #3 /* r0 = (num of core) - 1 */
mov r3, #0 /* flags for arm_cpu_hatched */
cmp r0, #0
ble 9f
#ifdef VERBOSE_INIT_ARM
/* wait to prevent the mixing of console output */
mov r2, #0x400000
1: subs r2, r2, #1
bne 1b
#endif
/* enable core1 */
adr r2, nitrogen6_mpstart
str r2, [r1, #SRC_GPR3] /* set core1 entry address */
ldr r2, [r1, #SRC_SCR]
orr r2, r2, #SRC_SCR_CORE1_ENABLE /* enable core1 */
orr r2, r2, #SRC_SCR_CORE1_RST /* reset core1 */
str r2, [r1, #SRC_SCR]
orr r3, r3, #(1<<1) /* cpu1 bit for arm_cpu_hatched */
cmp r0, #1
ble 9f
#ifdef VERBOSE_INIT_ARM
/* wait to prevent the mixing of console output */
mov r2, #0x400000
1: subs r2, r2, #1
bne 1b
#endif
/* enable core2 */
adr r2, nitrogen6_mpstart
str r2, [r1, #SRC_GPR5] /* set core2 entry address */
ldr r2, [r1, #SRC_SCR]
orr r2, r2, #SRC_SCR_CORE2_ENABLE /* enable core2 */
orr r2, r2, #SRC_SCR_CORE2_RST /* reset core2 */
str r2, [r1, #SRC_SCR]
orr r3, r3, #(1<<2) /* cpu2 bit for arm_cpu_hatched */
cmp r0, #2
ble 9f
#ifdef VERBOSE_INIT_ARM
/* wait to prevent the mixing of console output */
mov r2, #0x400000
1: subs r2, r2, #1
bne 1b
#endif
/* enable core3 */
adr r2, nitrogen6_mpstart
str r2, [r1, #SRC_GPR7] /* set core3 entry address */
ldr r2, [r1, #SRC_SCR]
orr r2, r2, #SRC_SCR_CORE3_ENABLE /* enable core3 */
orr r2, r2, #SRC_SCR_CORE3_RST /* reset core3 */
str r2, [r1, #SRC_SCR]
orr r3, r3, #(1<<3) /* cpu3 bit for arm_cpu_hatched */
9:
/* wait hatched */
movw r2, #:lower16:arm_cpu_hatched
movt r2, #:upper16:arm_cpu_hatched
mov r1, #0x10000000 /* i = 0x10000000; do { */
1: dmb /* memory barrier */
ldr r0, [r2]
cmp r0, r3 /* if (arm_cpu_hatched == r3) */
beq .hatched /* goto .hatched; */
subs r1, r1, #1
bne 1b /* } while (--i != 0); */
.not_hatched:
PRINT("\r\nnot hatched. arm_cpu_hatched=")
PRINT_R0
b 9f
.hatched:
PRINT("\r\nMULTIPROCESSOR hatched!\r\n")
9:
#endif
PRINT("jump to start()\r\n")
movw lr, #:lower16:start
movt lr, #:upper16:start
bx lr
/* NOTREACHED */
nitrogen6_mpstart:
/* invalidate cache */
movw ip, #:lower16:_C_LABEL(armv7_dcache_inv_all)
movt ip, #:upper16:_C_LABEL(armv7_dcache_inv_all)
#ifndef KERNEL_BASES_EQUAL
sub ip, ip, #KERNEL_BASE_VOFFSET
#endif
blx ip
b _C_LABEL(cortex_mpstart)
#include <arm/cortex/a9_mpsubr.S>
mmu_init_table:
/* map VA==PA for IO+MEM (0x00000000-0x4fffffff) */
MMU_INIT(0x00000000, 0x00000000,
0x50000000 / L1_S_SIZE,
L1_S_PROTO_armv7 | L1_S_APv7_KRW)
#if KERNEL_BASE_VOFFSET != 0
MMU_INIT(KERNEL_BASE, KERNEL_BASE - KERNEL_BASE_VOFFSET,
(BOOT_MEMSIZE * L1_S_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_CACHEABLE)
#endif
/* Map the 2MB of primary peripherals (AIPS1 + AIPS2) */
MMU_INIT(KERNEL_IO_IOREG_VBASE, IMX6_IOREG_PBASE,
(IMX6_IOREG_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
L1_S_PROTO_armv7 | L1_S_APv7_KRW)
/* Map the 1MB of armcore peripherals */
MMU_INIT(KERNEL_IO_ARMCORE_VBASE, IMX6_ARMCORE_PBASE,
(IMX6_ARMCORE_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
L1_S_PROTO_armv7 | L1_S_APv7_KRW)
/* end of table */
MMU_INIT(0, 0, 0, 0)
#ifdef VERBOSE_INIT_ARM
/*
* xprint - print strings pointed by $PC(LR)
* and return to the end of string.
* all registers are saved.
* e.g.)
* bl xprint <- call
* .ascii "Hello\r\n\0" <- don't return here
* .align 2
* nop <- return to here
*/
xprint:
stmfd sp!, {r0, r1}
mov r1, lr
1:
ldrb r0, [r1], #1
stmfd sp!, {r0, r1, r2, r3}
bl xputc
ldmfd sp!, {r0, r1, r2, r3}
cmp r0, #0
bne 1b
add r1, r1, #3
bic lr, r1, #3 /* lr = 4byte-aligned end of string */
ldmfd sp!, {r0, r1}
bx lr
/*
* print_r0 - show r0 hexadecimal with CR/LF.
* all registers are saved.
*/
print_r0:
stmfd sp!, {r0, r3, lr}
mov r3, r0
mov r0, #'0'
bl debugputc
mov r0, #'x'
bl debugputc
bl print_r3
mov r0, #'\r'
bl debugputc
mov r0, #'\n'
bl debugputc
ldmfd sp!, {r0, r3, pc}
/*
* print_r3 - show r3 hexadecimal without CR/LF nor prefix(0x).
* all registers are saved.
*/
print_r3:
stmfd sp!, {r0, r3-r6, lr}
mov r4, #28 /* num of shift. 28,24,20...8,4,0 */
mov r5, #0xf /* mask */
1:
and r6, r5, r3, ROR r4
cmp r6, #10
addlt r0, r6, #'0'
addge r0, r6, #('a' - 0x0a)
bl debugputc
subs r4, r4, #4
bge 1b
ldmfd sp!, {r0, r3-r6, pc}
/*
* debugputc - putc r0. xputc() is defined in arm/cortex/a9_mpsubr.S
* all registers are saved.
*/
debugputc:
stmfd sp!, {r0, r1, r2, r3, lr}
bl xputc
ldmfd sp!, {r0, r1, r2, r3, pc}
#endif /* VERBOSE_INIT_ARM */
/*
* temporary local stack
*/
.align 8
.space 1024
tmpstack:
END(_C_LABEL(nitrogen6_start))

215
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/* $NetBSD: nitrogen6_usb.c,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*
* Copyright (c) 2013 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: nitrogen6_usb.c,v 1.1 2014/09/25 05:05:28 ryo Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/conf.h>
#include <sys/kernel.h>
#include <sys/device.h>
#include <sys/intr.h>
#include <sys/bus.h>
#include <dev/usb/usb.h>
#include <dev/usb/usbdi.h>
#include <dev/usb/usbdivar.h>
#include <dev/usb/usb_mem.h>
#include <dev/usb/ehcireg.h>
#include <dev/usb/ehcivar.h>
#include <arm/imx/imx6_reg.h>
#include <arm/imx/imx6var.h>
#include <arm/imx/imx6_usbreg.h>
#include <arm/imx/imx6_ccmreg.h>
#include <arm/imx/imx6_ccmvar.h>
#include <arm/imx/imx6_iomuxreg.h>
#include <arm/imx/imxusbreg.h>
#include <arm/imx/imxusbvar.h>
#include <arm/imx/imxgpiovar.h>
#include "locators.h"
struct nitrogen6_usbc_softc {
struct imxusbc_softc sc_imxusbc;
};
static int nitrogen6_usbc_match(device_t, cfdata_t, void *);
static void nitrogen6_usbc_attach(device_t, device_t, void *);
static void nitrogen6_usb_init(struct imxehci_softc *);
static void init_otg(struct imxehci_softc *);
static void init_h1(struct imxehci_softc *);
/* attach structures */
CFATTACH_DECL_NEW(imxusbc_axi, sizeof(struct nitrogen6_usbc_softc),
nitrogen6_usbc_match, nitrogen6_usbc_attach, NULL, NULL);
static int
nitrogen6_usbc_match(device_t parent, cfdata_t cf, void *aux)
{
struct axi_attach_args *aa = aux;
if (aa->aa_addr == IMX6_AIPS2_BASE + AIPS2_USBOH_BASE)
return 1;
return 0;
}
static void
nitrogen6_usbc_attach(device_t parent, device_t self, void *aux)
{
struct axi_attach_args *aa = aux;
struct imxusbc_softc *sc = device_private(self);
sc->sc_init_md_hook = nitrogen6_usb_init;
sc->sc_setup_md_hook = NULL;
aprint_naive("\n");
aprint_normal(": Universal Serial Bus Controller\n");
imxusbc_attach_common(parent, self, aa->aa_iot);
}
static void
nitrogen6_usb_init(struct imxehci_softc *sc)
{
switch (sc->sc_unit) {
case 0: /* OTG controller */
init_otg(sc);
break;
case 1: /* EHCI Host 1 */
init_h1(sc);
break;
case 2: /* EHCI Host 2 */
case 3: /* EHCI Host 3 */
default:
aprint_error_dev(sc->sc_hsc.sc_dev, "unit %d not supported\n",
sc->sc_unit);
}
}
static void
init_otg(struct imxehci_softc *sc)
{
struct imxusbc_softc *usbc = sc->sc_usbc;
uint32_t v;
sc->sc_iftype = IMXUSBC_IF_UTMI_WIDE;
/* USB1 power */
imx6_ccm_write(USB_ANALOG_USB1_CHRG_DETECT,
USB_ANALOG_USB_CHRG_DETECT_EN_B |
USB_ANALOG_USB_CHRG_DETECT_CHK_CHRG_B);
imx6_pll_power(CCM_ANALOG_PLL_USB1, 1);
imx6_ccm_write(CCM_ANALOG_PLL_USB1_CLR,
CCM_ANALOG_PLL_USBn_BYPASS);
imx6_ccm_write(CCM_ANALOG_PLL_USB1_SET,
CCM_ANALOG_PLL_USBn_ENABLE |
CCM_ANALOG_PLL_USBn_POWER |
CCM_ANALOG_PLL_USBn_EN_USB_CLK);
/* USBPHY enable */
/* PHY1 */
imx6_ccm_write(USBPHY1_CTRL, USBPHY_CTRL_CLKGATE);
imxehci_reset(sc);
v = imx6_ccm_read(USBPHY1_CTRL);
v |= USBPHY_CTRL_SFTRST;
imx6_ccm_write(USBPHY1_CTRL, v);
delay(100);
v = imx6_ccm_read(USBPHY1_CTRL);
v &= ~(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE);
imx6_ccm_write(USBPHY1_CTRL, v);
delay(100);
imx6_ccm_write(USBPHY1_PWD, 0);
v = imx6_ccm_read(USBPHY1_CTRL);
v |= USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3;
imx6_ccm_write(USBPHY1_CTRL, v);
v = bus_space_read_4(usbc->sc_iot, usbc->sc_ioh, USBNC_USB_OTG_CTRL);
v |= USBNC_USB_OTG_CTRL_WKUP_VBUS_EN;
v |= USBNC_USB_OTG_CTRL_OVER_CUR_DIS;
v |= USBNC_USB_OTG_CTRL_PWR_POL;
v &= ~USBNC_USB_OTG_CTRL_UTMI_ON_CLOCK;
bus_space_write_4(usbc->sc_iot, usbc->sc_ioh, USBNC_USB_OTG_CTRL, v);
}
static void
init_h1(struct imxehci_softc *sc)
{
struct imxusbc_softc *usbc = sc->sc_usbc;
uint32_t v;
sc->sc_iftype = IMXUSBC_IF_UTMI_WIDE;
imx6_ccm_write(USB_ANALOG_USB2_CHRG_DETECT,
USB_ANALOG_USB_CHRG_DETECT_EN_B |
USB_ANALOG_USB_CHRG_DETECT_CHK_CHRG_B);
imx6_ccm_write(CCM_ANALOG_PLL_USB2_CLR,
CCM_ANALOG_PLL_USBn_BYPASS);
imx6_ccm_write(CCM_ANALOG_PLL_USB2_SET,
CCM_ANALOG_PLL_USBn_ENABLE |
CCM_ANALOG_PLL_USBn_POWER |
CCM_ANALOG_PLL_USBn_EN_USB_CLK);
v = bus_space_read_4(usbc->sc_iot, usbc->sc_ioh, USBNC_USB_UH1_CTRL);
v |= USBNC_USB_UH1_CTRL_OVER_CUR_POL;
v |= USBNC_USB_UH1_CTRL_OVER_CUR_DIS;
bus_space_write_4(usbc->sc_iot, usbc->sc_ioh, USBNC_USB_UH1_CTRL, v);
/* gate clocks */
imx6_ccm_write(USBPHY2_CTRL_CLR, USBPHY_CTRL_CLKGATE);
/* do reset */
imxehci_reset(sc);
imx6_ccm_write(USBPHY2_CTRL_SET, USBPHY_CTRL_SFTRST);
delay(100);
/* clear reset, and run clocks */
imx6_ccm_write(USBPHY2_CTRL_CLR, USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE);
delay(100);
/* power on */
imx6_ccm_write(USBPHY2_PWD, 0);
/* UTMI+Level2, Level3 */
imx6_ccm_write(USBPHY2_CTRL_SET,
USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
/* set mode */
v = bus_space_read_4(usbc->sc_iot, usbc->sc_ioh, USBC_UH1_USBMODE);
v &= ~__SHIFTIN(USBC_UH_USBMODE_CM, 3);
v |= __SHIFTIN(USBC_UH_USBMODE_CM, USBC_UH_USBMODE_CM_HOST_CONTROLLER);
bus_space_write_4(usbc->sc_iot, usbc->sc_ioh, USBC_UH1_USBMODE, v);
}

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/* $NetBSD: platform.h,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Nick Hudson
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _EVBARM_NITROGEN_PLATFORM_H
#define _EVBARM_NITROGEN_PLATFORM_H
#include <arm/imx/imx6_reg.h>
/*
* Memory will be mapped starting at 0x80000000 through 0xbfffffff
* Kernel VM space: KERNEL_VM_BASE to 0xc0000000
*/
#define KERNEL_VM_BASE (KERNEL_BASE + 0x40000000)
#define KERNEL_VM_TOP ((0xfff00000 - IMX6_IOREG_SIZE) & -L1_SS_SIZE)
#define KERNEL_VM_SIZE (KERNEL_VM_TOP - KERNEL_VM_BASE)
/*
* NITROGEN6X ARM Peripherals. Their physical address would live in the user
* address space, so we can't map 1:1 VA:PA. So shove them just after the
* top of the kernel VM.
*/
#define KERNEL_IO_VBASE KERNEL_VM_TOP
#define KERNEL_IO_IOREG_VBASE KERNEL_IO_VBASE
#define KERNEL_IO_ARMCORE_VBASE (KERNEL_IO_IOREG_VBASE + IMX6_IOREG_SIZE)
#define KERNEL_IO_END_VBASE (KERNEL_IO_ARMCORE_VBASE + IMX6_ARMCORE_SIZE)
#endif /* _EVBARM_NITROGEN_PLATFORM_H */