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Update for current PCI device class/subclass and capability codes. 

(also, tweak the I2O subclass string to be "standard" -- the removal
of version info didn't extend that far.)
This commit is contained in:
cgd 2000-10-07 18:58:13 +00:00
parent 6029888a3a
commit a3dbabc67b
2 changed files with 68 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

43
sys/dev/pci/pci_subr.c
View File

@ -1,8 +1,8 @@
/* $NetBSD: pci_subr.c,v 1.39 2000/10/02 14:48:13 ad Exp $ */ /* $NetBSD: pci_subr.c,v 1.40 2000/10/07 18:58:13 cgd Exp $ */
/* /*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved. * Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
* Copyright (c) 1995, 1996, 1998 * Copyright (c) 1995, 1996, 1998, 2000
* Christopher G. Demetriou. All rights reserved. * Christopher G. Demetriou. All rights reserved.
* Copyright (c) 1994 Charles M. Hannum. All rights reserved. * Copyright (c) 1994 Charles M. Hannum. All rights reserved.
* *
@ -87,6 +87,7 @@ struct pci_class pci_subclass_mass_storage[] = {
{ "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, }, { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, },
{ "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, }, { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, },
{ "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, }, { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, },
{ "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, },
{ "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, }, { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, },
{ 0 }, { 0 },
}; };
@ -97,6 +98,8 @@ struct pci_class pci_subclass_network[] = {
{ "FDDI", PCI_SUBCLASS_NETWORK_FDDI, }, { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, },
{ "ATM", PCI_SUBCLASS_NETWORK_ATM, }, { "ATM", PCI_SUBCLASS_NETWORK_ATM, },
{ "ISDN", PCI_SUBCLASS_NETWORK_ISDN, }, { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, },
{ "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, },
{ "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, },
{ "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, }, { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, },
{ 0 }, { 0 },
}; };
@ -134,6 +137,8 @@ struct pci_class pci_subclass_bridge[] = {
{ "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, }, { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, },
{ "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, }, { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, },
{ "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, }, { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, },
{ "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, },
{ "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, },
{ "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, }, { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, },
{ 0 }, { 0 },
}; };
@ -192,6 +197,10 @@ struct pci_class pci_subclass_serialbus[] = {
/* XXX Fiber Channel/_FIBRECHANNEL */ /* XXX Fiber Channel/_FIBRECHANNEL */
{ "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, }, { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, },
{ "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, }, { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, },
{ "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, },
{ "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, },
{ "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, },
{ "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, },
{ 0 }, { 0 },
}; };
@ -204,7 +213,7 @@ struct pci_class pci_subclass_wireless[] = {
}; };
struct pci_class pci_subclass_i2o[] = { struct pci_class pci_subclass_i2o[] = {
{ "1.0", PCI_SUBCLASS_I2O_STANDARD, }, { "standard", PCI_SUBCLASS_I2O_STANDARD, },
{ 0 }, { 0 },
}; };
@ -225,6 +234,7 @@ struct pci_class pci_subclass_crypto[] = {
struct pci_class pci_subclass_dasp[] = { struct pci_class pci_subclass_dasp[] = {
{ "DPIO", PCI_SUBCLASS_DASP_DPIO, }, { "DPIO", PCI_SUBCLASS_DASP_DPIO, },
{ "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, },
{ "miscellaneous", PCI_SUBCLASS_DASP_MISC, }, { "miscellaneous", PCI_SUBCLASS_DASP_MISC, },
{ 0 }, { 0 },
}; };
@ -744,6 +754,9 @@ pci_conf_print_type0(pc, tag, regs, sizebars)
printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval));
switch (PCI_CAPLIST_CAP(rval)) { switch (PCI_CAPLIST_CAP(rval)) {
case PCI_CAP_RESERVED0:
printf("reserved");
break;
case PCI_CAP_PWRMGMT: case PCI_CAP_PWRMGMT:
printf("Power Management, rev. %d.0", printf("Power Management, rev. %d.0",
(rval >> 0) & 0x07); /* XXX not clear */ (rval >> 0) & 0x07); /* XXX not clear */
@ -762,11 +775,29 @@ pci_conf_print_type0(pc, tag, regs, sizebars)
case PCI_CAP_MBI: case PCI_CAP_MBI:
printf("MBI"); printf("MBI");
break; break;
case PCI_CAP_HOTSWAP: case PCI_CAP_CPCI_HOTSWAP:
printf("Hot-swapping"); printf("CompactPCI Hot-swapping");
break;
case PCI_CAP_PCIX:
printf("PCI-X");
break;
case PCI_CAP_LDT:
printf("LDT");
break;
case PCI_CAP_VENDSPEC:
printf("Vendor-specific");
break;
case PCI_CAP_DEBUGPORT:
printf("Debug Port");
break;
case PCI_CAP_CPCI_RSRCCTL:
printf("CompactPCI Resource Control");
break;
case PCI_CAP_HOTPLUG:
printf("Hot-Plug");
break; break;
default: default:
printf("unknown/reserved"); printf("unknown");
} }
printf(")\n"); printf(")\n");
} }

34
sys/dev/pci/pcireg.h
View File

@ -1,7 +1,7 @@
/* $NetBSD: pcireg.h,v 1.31 2000/10/02 14:48:13 ad Exp $ */ /* $NetBSD: pcireg.h,v 1.32 2000/10/07 18:58:14 cgd Exp $ */
/* /*
* Copyright (c) 1995, 1996, 1999 * Copyright (c) 1995, 1996, 1999, 2000
* Christopher G. Demetriou. All rights reserved. * Christopher G. Demetriou. All rights reserved.
* Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved.
* *
@ -167,6 +167,7 @@ typedef u_int8_t pci_revision_t;
#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 #define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02
#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 #define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03
#define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 #define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04
#define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05
#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 #define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80
/* 0x02 network subclasses */ /* 0x02 network subclasses */
@ -175,6 +176,8 @@ typedef u_int8_t pci_revision_t;
#define PCI_SUBCLASS_NETWORK_FDDI 0x02 #define PCI_SUBCLASS_NETWORK_FDDI 0x02
#define PCI_SUBCLASS_NETWORK_ATM 0x03 #define PCI_SUBCLASS_NETWORK_ATM 0x03
#define PCI_SUBCLASS_NETWORK_ISDN 0x04 #define PCI_SUBCLASS_NETWORK_ISDN 0x04
#define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05
#define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06
#define PCI_SUBCLASS_NETWORK_MISC 0x80 #define PCI_SUBCLASS_NETWORK_MISC 0x80
/* 0x03 display subclasses */ /* 0x03 display subclasses */
@ -204,6 +207,8 @@ typedef u_int8_t pci_revision_t;
#define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 #define PCI_SUBCLASS_BRIDGE_NUBUS 0x06
#define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 #define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07
#define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 #define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08
#define PCI_SUBCLASS_BRIDGE_STPCI 0x09
#define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a
#define PCI_SUBCLASS_BRIDGE_MISC 0x80 #define PCI_SUBCLASS_BRIDGE_MISC 0x80
/* 0x07 communications subclasses */ /* 0x07 communications subclasses */
@ -249,6 +254,10 @@ typedef u_int8_t pci_revision_t;
#define PCI_SUBCLASS_SERIALBUS_USB 0x03 #define PCI_SUBCLASS_SERIALBUS_USB 0x03
#define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 /* XXX _FIBRECHANNEL */ #define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 /* XXX _FIBRECHANNEL */
#define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05 #define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05
#define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06
#define PCI_SUBCLASS_SERIALBUS_IPMI 0x07
#define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08
#define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09
/* 0x0d wireless subclasses */ /* 0x0d wireless subclasses */
#define PCI_SUBCLASS_WIRELESS_IRDA 0x00 #define PCI_SUBCLASS_WIRELESS_IRDA 0x00
@ -273,6 +282,7 @@ typedef u_int8_t pci_revision_t;
/* 0x11 data acquisition and signal processing subclasses */ /* 0x11 data acquisition and signal processing subclasses */
#define PCI_SUBCLASS_DASP_DPIO 0x00 #define PCI_SUBCLASS_DASP_DPIO 0x00
#define PCI_SUBCLASS_DASP_TIMEFREQ 0x01
#define PCI_SUBCLASS_DASP_MISC 0x80 #define PCI_SUBCLASS_DASP_MISC 0x80
/* /*
@ -384,12 +394,20 @@ typedef u_int8_t pci_revision_t;
#define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) #define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff)
#define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) #define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff)
#define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) #define PCI_CAPLIST_CAP(cr) ((cr) & 0xff)
#define PCI_CAP_PWRMGMT 1
#define PCI_CAP_AGP 2 #define PCI_CAP_RESERVED0 0x00
#define PCI_CAP_VPD 3 #define PCI_CAP_PWRMGMT 0x01
#define PCI_CAP_SLOTID 4 #define PCI_CAP_AGP 0x02
#define PCI_CAP_MBI 5 #define PCI_CAP_VPD 0x03
#define PCI_CAP_HOTSWAP 6 #define PCI_CAP_SLOTID 0x04
#define PCI_CAP_MBI 0x05
#define PCI_CAP_CPCI_HOTSWAP 0x06
#define PCI_CAP_PCIX 0x07
#define PCI_CAP_LDT 0x08
#define PCI_CAP_VENDSPEC 0x09
#define PCI_CAP_DEBUGPORT 0x0a
#define PCI_CAP_CPCI_RSRCCTL 0x0b
#define PCI_CAP_HOTPLUG 0x0c
/* /*
* Power Management Control Status Register; access via capability pointer. * Power Management Control Status Register; access via capability pointer.