Support omap3 SDHC driver. tested on OVERO only.
This commit is contained in:
kiyohara
parent
bfba6f2a6d
commit
a29e7e5640
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@ -1,4 +1,4 @@
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/* $NetBSD: omap3_sdhc.c,v 1.1 2012/07/12 03:08:26 matt Exp $ */
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/* $NetBSD: omap3_sdhc.c,v 1.2 2012/10/29 13:30:25 kiyohara Exp $ */
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/*-
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* Copyright (c) 2011 The NetBSD Foundation, Inc.
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* All rights reserved.
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@ -29,7 +29,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: omap3_sdhc.c,v 1.1 2012/07/12 03:08:26 matt Exp $");
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__KERNEL_RCSID(0, "$NetBSD: omap3_sdhc.c,v 1.2 2012/10/29 13:30:25 kiyohara Exp $");
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#include "opt_omap.h"
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@ -48,8 +48,20 @@ __KERNEL_RCSID(0, "$NetBSD: omap3_sdhc.c,v 1.1 2012/07/12 03:08:26 matt Exp $");
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#include <dev/sdmmc/sdhcreg.h>
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#include <dev/sdmmc/sdhcvar.h>
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#define CLKD(kz) (sc->sc.sc_clkbase / (kz))
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#define SDHC_READ(sc, reg) \
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bus_space_read_4((sc)->sc_bst, (sc)->sc_sdhc_bsh, (reg))
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#define SDHC_WRITE(sc, reg, val) \
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bus_space_write_4((sc)->sc_bst, (sc)->sc_sdhc_bsh, (reg), (val))
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static int obiosdhc_match(device_t, cfdata_t, void *);
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static void obiosdhc_attach(device_t, device_t, void *);
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static int obiosdhc_detach(device_t, int);
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static int obiosdhc_rod(struct sdhc_softc *, int);
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static int obiosdhc_write_protect(struct sdhc_softc *);
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static int obiosdhc_card_detect(struct sdhc_softc *);
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struct obiosdhc_softc {
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struct sdhc_softc sc;
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@ -61,7 +73,7 @@ struct obiosdhc_softc {
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};
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CFATTACH_DECL_NEW(obiosdhc, sizeof(struct obiosdhc_softc),
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obiosdhc_match, obiosdhc_attach, NULL, NULL);
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obiosdhc_match, obiosdhc_attach, obiosdhc_detach, NULL);
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static int
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obiosdhc_match(device_t parent, cfdata_t cf, void *aux)
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@ -85,18 +97,26 @@ obiosdhc_attach(device_t parent, device_t self, void *aux)
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{
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struct obiosdhc_softc * const sc = device_private(self);
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struct obio_attach_args * const oa = aux;
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int error;
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uint32_t clkd, stat;
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int error, timo, clksft, n;
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sc->sc.sc_dmat = oa->obio_dmat;
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sc->sc.sc_dev = self;
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//sc->sc.sc_flags |= SDHC_FLAG_USE_DMA;
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sc->sc.sc_flags |= SDHC_FLAG_32BIT_ACCESS;
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sc->sc.sc_flags |= SDHC_FLAG_HAVE_CGM;
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sc->sc.sc_flags |= SDHC_FLAG_NO_LED_ON;
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sc->sc.sc_flags |= SDHC_FLAG_RSP136_CRC;
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sc->sc.sc_flags |= SDHC_FLAG_SINGLE_ONLY;
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sc->sc.sc_host = sc->sc_hosts;
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sc->sc.sc_clkbase = 96000; /* 96MHZ */
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sc->sc.sc_clkmsk = 0x0000ffc0;
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sc->sc.sc_vendor_rod = obiosdhc_rod;
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sc->sc.sc_vendor_write_protect = obiosdhc_write_protect;
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sc->sc.sc_vendor_card_detect = obiosdhc_card_detect;
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sc->sc_bst = oa->obio_iot;
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clksft = ffs(sc->sc.sc_clkmsk) - 1;
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error = bus_space_map(sc->sc_bst, oa->obio_addr, oa->obio_size, 0,
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&sc->sc_bsh);
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if (error) {
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@ -111,7 +131,25 @@ obiosdhc_attach(device_t parent, device_t self, void *aux)
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aprint_naive(": SDHC controller\n");
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aprint_normal(": SDHC controller\n");
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sc->sc_ih = intr_establish(oa->obio_intr, IPL_VM, IST_LEVEL,
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/* XXXXXX: Turn-on regurator via I2C. */
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/* XXXXXX: And enable ICLOCK/FCLOCK. */
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/* MMCHS Soft reset */
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_SYSCONFIG,
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SYSCONFIG_SOFTRESET);
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timo = 3000000; /* XXXX 3 sec. */
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while (timo--) {
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if (bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_SYSSTATUS) &
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SYSSTATUS_RESETDONE)
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break;
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delay(1);
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}
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if (timo == 0)
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aprint_error_dev(self, "Soft reset timeout\n");
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_SYSCONFIG,
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SYSCONFIG_ENAWAKEUP | SYSCONFIG_AUTOIDLE);
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sc->sc_ih = intr_establish(oa->obio_intr, IPL_VM, IST_LEVEL,
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sdhc_intr, &sc->sc);
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if (sc->sc_ih == NULL) {
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aprint_error_dev(self, "failed to establish interrupt %d\n",
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@ -128,6 +166,74 @@ obiosdhc_attach(device_t parent, device_t self, void *aux)
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error);
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goto fail;
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}
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/* Set SDVS 1.8v and DTW 1bit mode */
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SDHC_WRITE(sc, SDHC_HOST_CTL,
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SDHC_VOLTAGE_1_8V << (SDHC_VOLTAGE_SHIFT + 8));
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON,
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bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON) | CON_OD);
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SDHC_WRITE(sc, SDHC_CLOCK_CTL,
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SDHC_READ(sc, SDHC_CLOCK_CTL) | SDHC_INTCLK_ENABLE |
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SDHC_SDCLK_ENABLE);
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SDHC_WRITE(sc, SDHC_HOST_CTL,
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SDHC_READ(sc, SDHC_HOST_CTL) | SDHC_BUS_POWER << 8);
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SDHC_WRITE(sc, SDHC_CLOCK_CTL,
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SDHC_READ(sc, SDHC_CLOCK_CTL) | CLKD(150) << clksft);
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/*
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* 22.6.1.3.1.5 MMCHS Controller INIT Procedure Start
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* from 'OMAP35x Applications Processor Technical Reference Manual'.
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*
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* During the INIT procedure, the MMCHS controller generates 80 clock
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* periods. In order to keep the 1ms gap, the MMCHS controller should
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* be configured to generate a clock whose frequency is smaller or
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* equal to 80 KHz.
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*/
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SDHC_WRITE(sc, SDHC_CLOCK_CTL,
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SDHC_READ(sc, SDHC_CLOCK_CTL) & ~SDHC_SDCLK_ENABLE);
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SDHC_WRITE(sc, SDHC_CLOCK_CTL,
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SDHC_READ(sc, SDHC_CLOCK_CTL) & ~sc->sc.sc_clkmsk);
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clkd = CLKD(80);
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n = 1;
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while (clkd & ~(sc->sc.sc_clkmsk >> clksft)) {
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clkd >>= 1;
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n <<= 1;
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}
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SDHC_WRITE(sc, SDHC_CLOCK_CTL,
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SDHC_READ(sc, SDHC_CLOCK_CTL) | (clkd << clksft));
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SDHC_WRITE(sc, SDHC_CLOCK_CTL,
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SDHC_READ(sc, SDHC_CLOCK_CTL) | SDHC_SDCLK_ENABLE);
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON,
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bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON) | CON_INIT);
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for (; n > 0; n--) {
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SDHC_WRITE(sc, SDHC_TRANSFER_MODE, 0x00000000);
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timo = 3000000; /* XXXX 3 sec. */
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stat = 0;
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while (!(stat & SDHC_COMMAND_COMPLETE)) {
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stat = SDHC_READ(sc, SDHC_NINTR_STATUS);
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if (--timo == 0)
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break;
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delay(1);
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}
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if (timo == 0) {
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aprint_error_dev(self, "INIT Procedure timeout\n");
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break;
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}
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SDHC_WRITE(sc, SDHC_NINTR_STATUS, stat);
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}
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON,
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bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON) & ~CON_INIT);
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SDHC_WRITE(sc, SDHC_CLOCK_CTL,
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SDHC_READ(sc, SDHC_CLOCK_CTL) & ~SDHC_SDCLK_ENABLE);
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SDHC_WRITE(sc, SDHC_CLOCK_CTL,
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SDHC_READ(sc, SDHC_CLOCK_CTL) & ~sc->sc.sc_clkmsk);
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SDHC_WRITE(sc, SDHC_CLOCK_CTL,
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SDHC_READ(sc, SDHC_CLOCK_CTL) | CLKD(150) << clksft);
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SDHC_WRITE(sc, SDHC_CLOCK_CTL,
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SDHC_READ(sc, SDHC_CLOCK_CTL) | SDHC_SDCLK_ENABLE);
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return;
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fail:
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@ -137,3 +243,49 @@ fail:
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}
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bus_space_unmap(sc->sc_bst, sc->sc_bsh, oa->obio_size);
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}
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static int
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obiosdhc_detach(device_t self, int flags)
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{
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// struct obiosdhc_softc *sc = device_private(self);
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int error;
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error = config_detach_children(self, flags);
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/* XXXXXX: Regurator turn-off via I2C. */
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/* XXXXXX: And disable ICLOCK/FCLOCK. */
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return error;
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}
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static int
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obiosdhc_rod(struct sdhc_softc *sc, int on)
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{
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struct obiosdhc_softc *osc = (struct obiosdhc_softc *)sc;
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uint32_t con;
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con = bus_space_read_4(osc->sc_bst, osc->sc_bsh, MMCHS_CON);
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if (on)
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con |= CON_OD;
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else
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con &= ~CON_OD;
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bus_space_write_4(osc->sc_bst, osc->sc_bsh, MMCHS_CON, con);
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return 0;
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}
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static int
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obiosdhc_write_protect(struct sdhc_softc *sc)
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{
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/* Maybe board dependent, using GPIO. Get GPIO-pin from prop? */
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return 0; /* XXXXXXX */
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}
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static int
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obiosdhc_card_detect(struct sdhc_softc *sc)
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{
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/* Maybe board dependent, using GPIO. Get GPIO-pin from prop? */
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return 1; /* XXXXXXXX */
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: omap3_sdmmcreg.h,v 1.1 2012/07/12 03:08:26 matt Exp $ */
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/* $NetBSD: omap3_sdmmcreg.h,v 1.2 2012/10/29 13:30:25 kiyohara Exp $ */
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/*-
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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@ -37,4 +37,38 @@
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#define OMAP3_SDMMC_SDHC_OFFSET 0x100
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#define OMAP3_SDMMC_SDHC_SIZE 0x100
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#define MMCHS_SYSCONFIG 0x010 /* System Configuration */
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# define SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8)
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# define SYSCONFIG_CLOCKACTIVITY_FCLK (2 << 8)
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# define SYSCONFIG_CLOCKACTIVITY_ICLK (1 << 8)
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# define SYSCONFIG_ENAWAKEUP (1 << 2)
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# define SYSCONFIG_SOFTRESET (1 << 1)
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# define SYSCONFIG_AUTOIDLE (1 << 0)
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#define MMCHS_SYSSTATUS 0x014 /* System Status */
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# define SYSSTATUS_RESETDONE (1 << 0)
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#define MMCHS_CSRE 0x024 /* Card status response error */
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#define MMCHS_SYSTEST 0x028 /* System Test */
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#define MMCHS_CON 0x02c /* Configuration */
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# define CON_CLKEXTFREE (1 << 16)
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# define CON_PADEN (1 << 15) /* Ctrl Pow for MMC */
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# define CON_OBIE (1 << 14) /* Out-of-Band Intr */
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# define CON_OBIP (1 << 13) /*O-of-B Intr Polarity*/
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# define CON_CEATA (1 << 12) /* CE-ATA */
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# define CON_CTPL (1 << 11) /* Ctrl Power dat[1] */
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# define CON_DVAL_33US (0 << 9) /* debounce filter val*/
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# define CON_DVAL_231US (1 << 9) /* debounce filter val*/
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# define CON_DVAL_1MS (2 << 9) /* debounce filter val*/
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# define CON_DVAL_8_4MS (3 << 9) /* 8.4ms */
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# define CON_WPP (1 << 8) /* Write protect pol */
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# define CON_CDP (1 << 7) /*Card detect polarity*/
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# define CON_MIT (1 << 6) /* MMC interrupt cmd */
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# define CON_DW8 (1 << 5) /* 8-bit mode */
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# define CON_MODE (1 << 4) /* SYSTEST mode */
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# define CON_STR (1 << 3) /* Stream command */
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# define CON_HR (1 << 2) /* Broadcast host rsp */
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# define CON_INIT (1 << 1) /* Send init stream */
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# define CON_OD (1 << 0) /* Card open drain */
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#define MMCHS_PWCNT 0x030 /* Power counter */
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#endif
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@ -1,4 +1,4 @@
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/* $NetBSD: sdhc.c,v 1.31 2012/09/13 21:44:50 joerg Exp $ */
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/* $NetBSD: sdhc.c,v 1.32 2012/10/29 13:30:25 kiyohara Exp $ */
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/* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */
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/*
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@ -23,7 +23,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.31 2012/09/13 21:44:50 joerg Exp $");
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__KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.32 2012/10/29 13:30:25 kiyohara Exp $");
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#ifdef _KERNEL_OPT
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#include "opt_sdmmc.h"
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@ -413,6 +413,8 @@ sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot,
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saa.saa_caps |= SMC_CAPS_MULTI_SEG_DMA;
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}
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}
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if (ISSET(sc->sc_flags, SDHC_FLAG_SINGLE_ONLY))
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saa.saa_caps |= SMC_CAPS_SINGLE_ONLY;
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hp->sdmmc = config_found(sc->sc_dev, &saa, sdhc_cfprint);
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return 0;
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@ -625,6 +627,9 @@ sdhc_card_detect(sdmmc_chipset_handle_t sch)
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struct sdhc_host *hp = (struct sdhc_host *)sch;
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int r;
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if (hp->sc->sc_vendor_card_detect)
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return (*hp->sc->sc_vendor_card_detect)(hp->sc);
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mutex_enter(&hp->host_mtx);
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r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED);
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mutex_exit(&hp->host_mtx);
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@ -641,6 +646,9 @@ sdhc_write_protect(sdmmc_chipset_handle_t sch)
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struct sdhc_host *hp = (struct sdhc_host *)sch;
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int r;
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if (hp->sc->sc_vendor_write_protect)
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return (*hp->sc->sc_vendor_write_protect)(hp->sc);
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mutex_enter(&hp->host_mtx);
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r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH);
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mutex_exit(&hp->host_mtx);
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@ -658,6 +666,8 @@ sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr)
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struct sdhc_host *hp = (struct sdhc_host *)sch;
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uint8_t vdd;
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int error = 0;
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const uint32_t pcmask =
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~(SDHC_BUS_POWER | (SDHC_VOLTAGE_MASK << SDHC_VOLTAGE_SHIFT));
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mutex_enter(&hp->host_mtx);
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@ -696,7 +706,11 @@ sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr)
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* voltage ramp until power rises.
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*/
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HWRITE1(hp, SDHC_POWER_CTL,
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(vdd << SDHC_VOLTAGE_SHIFT) | SDHC_BUS_POWER);
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HREAD1(hp, SDHC_POWER_CTL) & pcmask);
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sdmmc_delay(1);
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HWRITE1(hp, SDHC_POWER_CTL, (vdd << SDHC_VOLTAGE_SHIFT));
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sdmmc_delay(1);
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HSET1(hp, SDHC_POWER_CTL, SDHC_BUS_POWER);
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sdmmc_delay(10000);
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/*
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@ -760,13 +774,12 @@ sdhc_clock_divisor(struct sdhc_host *hp, u_int freq, u_int *divp)
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/* No divisor found. */
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return false;
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} else {
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for (div = 1; div <= 256; div *= 2) {
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if ((hp->clkbase / div) <= freq) {
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*divp = (div / 2) << SDHC_SDCLK_DIV_SHIFT;
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//freq = hp->clkbase / div;
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return true;
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}
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}
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if (hp->sc->sc_clkmsk != 0)
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*divp = (hp->clkbase / freq) <<
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(ffs(hp->sc->sc_clkmsk) - 1);
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else
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*divp = (hp->clkbase / freq) << SDHC_SDCLK_DIV_SHIFT;
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return true;
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}
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/* No divisor found. */
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return false;
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@ -782,6 +795,7 @@ sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq)
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struct sdhc_host *hp = (struct sdhc_host *)sch;
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u_int div;
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u_int timo;
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int16_t reg;
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int error = 0;
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#ifdef DIAGNOSTIC
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bool present;
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@ -809,7 +823,7 @@ sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq)
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goto out;
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}
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} else {
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HWRITE2(hp, SDHC_CLOCK_CTL, 0);
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HCLR2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE);
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if (freq == SDMMC_SDCLK_OFF)
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goto out;
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}
|
||||
|
|
@ -826,7 +840,9 @@ sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq)
|
|||
HWRITE4(hp, SDHC_CLOCK_CTL,
|
||||
div | (SDHC_TIMEOUT_MAX << 16));
|
||||
} else {
|
||||
HWRITE2(hp, SDHC_CLOCK_CTL, div);
|
||||
reg = HREAD2(hp, SDHC_CLOCK_CTL);
|
||||
reg &= (SDHC_INTCLK_STABLE | SDHC_INTCLK_ENABLE);
|
||||
HWRITE2(hp, SDHC_CLOCK_CTL, reg | div);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -931,8 +947,11 @@ sdhc_bus_width(sdmmc_chipset_handle_t sch, int width)
|
|||
static int
|
||||
sdhc_bus_rod(sdmmc_chipset_handle_t sch, int on)
|
||||
{
|
||||
struct sdhc_host *hp = (struct sdhc_host *)sch;
|
||||
|
||||
if (hp->sc->sc_vendor_rod)
|
||||
return (*hp->sc->sc_vendor_rod)(hp->sc, on);
|
||||
|
||||
/* Nothing ?? */
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1031,6 +1050,15 @@ sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd)
|
|||
cmd->c_resp[1] = HREAD4(hp, SDHC_RESPONSE + 4);
|
||||
cmd->c_resp[2] = HREAD4(hp, SDHC_RESPONSE + 8);
|
||||
cmd->c_resp[3] = HREAD4(hp, SDHC_RESPONSE + 12);
|
||||
if (ISSET(hp->sc->sc_flags, SDHC_FLAG_RSP136_CRC)) {
|
||||
cmd->c_resp[0] = (cmd->c_resp[0] >> 8) |
|
||||
(cmd->c_resp[1] << 24);
|
||||
cmd->c_resp[1] = (cmd->c_resp[1] >> 8) |
|
||||
(cmd->c_resp[2] << 24);
|
||||
cmd->c_resp[2] = (cmd->c_resp[2] >> 8) |
|
||||
(cmd->c_resp[3] << 24);
|
||||
cmd->c_resp[3] = (cmd->c_resp[3] >> 8);
|
||||
}
|
||||
}
|
||||
}
|
||||
mutex_exit(&hp->host_mtx);
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: sdhcvar.h,v 1.8 2012/07/21 16:14:05 skrll Exp $ */
|
||||
/* $NetBSD: sdhcvar.h,v 1.9 2012/10/29 13:30:25 kiyohara Exp $ */
|
||||
/* $OpenBSD: sdhcvar.h,v 1.3 2007/09/06 08:01:01 jsg Exp $ */
|
||||
|
||||
/*
|
||||
|
|
@ -45,9 +45,16 @@ struct sdhc_softc {
|
|||
#define SDHC_FLAG_HAVE_CGM 0x0080 /* Netlogic XLP */
|
||||
#define SDHC_FLAG_NO_LED_ON 0x0100 /* LED_ON unsupported in HOST_CTL */
|
||||
#define SDHC_FLAG_HOSTCAPS 0x0200 /* No device provided capabilities */
|
||||
#define SDHC_FLAG_RSP136_CRC 0x0400 /* Resp 136 with CRC and end-bit */
|
||||
#define SDHC_FLAG_SINGLE_ONLY 0x0800 /* Single transfer only */
|
||||
|
||||
uint32_t sc_clkbase;
|
||||
int sc_clkmsk; /* Mask for SDCLK */
|
||||
uint32_t sc_caps;/* attachment provided capabilities */
|
||||
|
||||
int (*sc_vendor_rod)(struct sdhc_softc *, int);
|
||||
int (*sc_vendor_write_protect)(struct sdhc_softc *);
|
||||
int (*sc_vendor_card_detect)(struct sdhc_softc *);
|
||||
};
|
||||
|
||||
/* Host controller functions called by the attachment driver. */
|
||||
|
|
|
|||
Loading…
Reference in New Issue