KNF and cosmetics.
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@ -1,4 +1,4 @@
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/* $NetBSD: arc_trap.c,v 1.23 2003/04/27 17:05:55 tsutsui Exp $ */
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/* $NetBSD: arc_trap.c,v 1.24 2003/04/27 17:13:01 tsutsui Exp $ */
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/* $OpenBSD: trap.c,v 1.22 1999/05/24 23:08:59 jason Exp $ */
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/*
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@ -63,8 +63,8 @@ int arc_hardware_intr __P((u_int32_t, u_int32_t, u_int32_t, u_int32_t));
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#define MIPS_INT_LEVELS 8
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struct {
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int int_mask;
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int (*int_hand)(u_int, struct clockframe *);
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int int_mask;
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int (*int_hand)(u_int, struct clockframe *);
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} cpu_int_tab[MIPS_INT_LEVELS];
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int cpu_int_mask; /* External cpu interrupt mask */
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@ -86,8 +86,8 @@ arc_hardware_intr(status, cause, pc, ipending)
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* Check off all enabled interrupts. Called interrupt routine
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* returns mask of interrupts to reenable.
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*/
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for(i = 0; i < MIPS_INT_LEVELS; i++) {
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if(cpu_int_tab[i].int_mask & ipending) {
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for (i = 0; i < MIPS_INT_LEVELS; i++) {
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if (cpu_int_tab[i].int_mask & ipending) {
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cause &= (*cpu_int_tab[i].int_hand)(ipending, &cf);
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}
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}
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@ -95,7 +95,7 @@ arc_hardware_intr(status, cause, pc, ipending)
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/*
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* Reenable all non served hardware levels.
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*/
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return ((status & ~cause & MIPS3_HARD_INT_MASK) | MIPS_SR_INT_IE);
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return (status & ~cause & MIPS3_HARD_INT_MASK) | MIPS_SR_INT_IE;
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}
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/*
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@ -104,16 +104,16 @@ arc_hardware_intr(status, cause, pc, ipending)
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*/
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void
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arc_set_intr(mask, int_hand, prio)
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int mask;
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int (*int_hand)(u_int, struct clockframe *);
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int prio;
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int mask;
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int (*int_hand)(u_int, struct clockframe *);
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int prio;
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{
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if(prio > MIPS_INT_LEVELS)
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if (prio > MIPS_INT_LEVELS)
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panic("set_intr: to high priority");
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if(cpu_int_tab[prio].int_mask != 0 &&
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(cpu_int_tab[prio].int_mask != mask ||
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cpu_int_tab[prio].int_hand != int_hand)) {
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if (cpu_int_tab[prio].int_mask != 0 &&
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(cpu_int_tab[prio].int_mask != mask ||
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cpu_int_tab[prio].int_hand != int_hand)) {
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panic("set_intr: int already set");
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}
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