MachForceCacheUpdate and cacheflush_bug have never been used in NetBSD,
so remove references them, and do a little other cleanup.
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soren
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9f00930ace
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a255740671
@ -1,9 +1,11 @@
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# $NetBSD: files.mips,v 1.25 2000/05/21 03:31:35 soren Exp $
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# $NetBSD: files.mips,v 1.26 2000/05/23 04:21:39 soren Exp $
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#
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defopt opt_cputype.h NOTYET # MIPS1 MIPS3 MIPS4 NOFPU
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# MIPS3_4100 MIPS3_5200
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# ENABLE_MIPS_TX3900
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# ENABLE_MIPS_R4700
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# ENABLE_MIPS_R3NKK
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defopt opt_mips_cache.h MIPS3_L2CACHE_ABSENT
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MIPS3_L2CACHE_PRESENT
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file arch/mips/mips/db_disasm.c ddb
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@ -1,4 +1,4 @@
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/* $NetBSD: cpuregs.h,v 1.31 2000/05/21 04:03:35 soren Exp $ */
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/* $NetBSD: cpuregs.h,v 1.32 2000/05/23 04:21:39 soren Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -576,9 +576,6 @@
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/*
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* Patch codes to hide CPU design differences between MIPS1 and MIPS3.
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*
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* XXX INT_MASK and HARD_INT_MASK are here only because we dont
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* support the mips3 on-chip timer which is tied to INT_5.
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*/
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#if !defined(MIPS3) && defined(MIPS1)
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.h,v 1.32 2000/05/21 03:23:15 soren Exp $ */
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/* $NetBSD: locore.h,v 1.33 2000/05/23 04:21:40 soren Exp $ */
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/*
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* Copyright 1996 The Board of Trustees of The Leland Stanford
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@ -23,15 +23,11 @@
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* MachFlushCache
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* MachFlushDCache
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* MachFlushICache
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* MachForceCacheUpdate
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* wbflush
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* proc_trampoline()
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* cpu_switch_resume()
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*
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* We currently provide support for:
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*
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* r2000 and r3000 (mips ISA-I)
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* r4000 and r4400 in 32-bit mode (mips ISA-III?)
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* We currently provide support for MIPS I and MIPS III.
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*/
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#ifndef _MIPS_LOCORE_H
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@ -54,7 +50,6 @@ void mips1_ConfigCache __P((void));
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void mips1_FlushCache __P((void));
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void mips1_FlushDCache __P((vaddr_t addr, vsize_t len));
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void mips1_FlushICache __P((vaddr_t addr, vsize_t len));
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void mips1_ForceCacheUpdate __P((void));
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void mips1_SetPID __P((int pid));
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void mips1_TBIA __P((int));
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@ -71,7 +66,6 @@ void mips3_ConfigCache __P((void));
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void mips3_FlushCache __P((void));
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void mips3_FlushDCache __P((vaddr_t addr, vaddr_t len));
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void mips3_FlushICache __P((vaddr_t addr, vaddr_t len));
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void mips3_ForceCacheUpdate __P((void));
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void mips3_HitFlushDCache __P((vaddr_t, int));
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void mips3_SetPID __P((int pid));
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@ -115,7 +109,6 @@ typedef struct {
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void (*flushCache) __P((void));
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void (*flushDCache) __P((vaddr_t addr, vsize_t len));
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void (*flushICache) __P((vaddr_t addr, vsize_t len));
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void (*forceCacheUpdate) __P((void));
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void (*setTLBpid) __P((int pid));
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void (*TBIAP) __P((int));
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void (*TBIS) __P((vaddr_t));
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@ -160,7 +153,6 @@ extern long *mips_locoresw[];
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#define MachHitFlushDCache mips3_HitFlushDCache
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#define MachFlushICache mips3_FlushICache
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#endif
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#define MachForceCacheUpdate mips3_ForceCacheUpdate
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#define MachSetPID mips3_SetPID
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#define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries)
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#define MIPS_TBIS mips3_TBIS
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@ -174,7 +166,6 @@ extern long *mips_locoresw[];
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#define MachFlushCache mips1_FlushCache
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#define MachFlushDCache mips1_FlushDCache
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#define MachFlushICache mips1_FlushICache
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#define MachForceCacheUpdate mips1_ForceCacheUpdate
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#define MachSetPID mips1_SetPID
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#define MIPS_TBIAP() mips1_TBIAP(mips_num_tlb_entries)
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#define MIPS_TBIS mips1_TBIS
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@ -190,7 +181,6 @@ extern long *mips_locoresw[];
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#define MachFlushCache (*(mips_locore_jumpvec.flushCache))
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#define MachFlushDCache (*(mips_locore_jumpvec.flushDCache))
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#define MachFlushICache (*(mips_locore_jumpvec.flushICache))
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#define MachForceCacheUpdate (*(mips_locore_jumpvec.forceCacheUpdate))
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#define MachSetPID (*(mips_locore_jumpvec.setTLBpid))
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#define MIPS_TBIAP() (*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries)
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#define MIPS_TBIS (*(mips_locore_jumpvec.TBIS))
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@ -1,4 +1,4 @@
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/* $NetBSD: r3900regs.h,v 1.1 1999/11/29 11:13:11 uch Exp $ */
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/* $NetBSD: r3900regs.h,v 1.2 2000/05/23 04:21:40 soren Exp $ */
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/*
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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@ -138,5 +138,3 @@
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#define CPUREG_A0 4
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#define CPUREG_T0 8
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@ -1,4 +1,4 @@
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/* $NetBSD: locore_mips3.S,v 1.29 2000/05/21 03:23:16 soren Exp $ */
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/* $NetBSD: locore_mips3.S,v 1.30 2000/05/23 04:21:40 soren Exp $ */
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/*
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* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
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@ -1447,18 +1447,6 @@ LEAF(mips3_TLBRead)
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sw t5, 12(a1)
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END(mips3_TLBRead)
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/*----------------------------------------------------------------------------
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*
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* R4000 cache flushing code.
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*
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*----------------------------------------------------------------------------
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*/
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/*
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* XXX need to handle two-way caches for r4600 and mips ISA-IV.
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*/
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/*----------------------------------------------------------------------------
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*
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* mips3_FlushCache --
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@ -2002,7 +1990,7 @@ END(mips5200_InvalidateDCache)
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* mips3_VCED --
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*
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* Handle virtual coherency exceptions.
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* Called directly from the mips3 execption-table code.
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* Called directly from the mips3 execption-table code.
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* only k0, k1 are avaiable on entry
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*
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* Results:
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@ -2516,7 +2504,7 @@ END(mips3_write_count)
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* each time the COUNT register increments past the COMPARE register.
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*
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* (The mips interrupt mask defintions currently leaves this interrupt
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* unconditionally masked out on mips3 CPUs.)
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* unconditionally masked out on mips3 CPUs.)
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*/
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LEAF(mips3_read_compare)
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mfc0 v0, MIPS_COP_0_COMPARE
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@ -2607,7 +2595,7 @@ END(mips3_FetchDcache)
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/*
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* The variables below are used to communicate the cache handling
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* to higher-level software.
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* to higher-level software.
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*/
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.sdata
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@ -2615,11 +2603,8 @@ END(mips3_FetchDcache)
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_C_LABEL(mips3_L1TwoWayCache):
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.word 0
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.globl _C_LABEL(mips3_cacheflush_bug)
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_C_LABEL(mips3_cacheflush_bug):
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.word 0
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.data
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.globl _C_LABEL(mips3_locoresw)
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_C_LABEL(mips3_locoresw):
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.word _C_LABEL(mips3_cpu_switch_resume)
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@ -1,4 +1,4 @@
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/* $NetBSD: mem.c,v 1.20 2000/03/03 02:33:21 castor Exp $ */
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/* $NetBSD: mem.c,v 1.21 2000/05/23 04:21:40 soren Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -114,6 +114,9 @@ mmrw(dev, uio, flags)
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case 0:
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v = uio->uio_offset;
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c = iov->iov_len;
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/*
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* XXX Broken; assumes contiguous physical memory.
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*/
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if (v + c > ctob(physmem))
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return (EFAULT);
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v += MIPS_KSEG0_START;
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@ -1,4 +1,4 @@
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/* $NetBSD: mips_machdep.c,v 1.80 2000/05/21 04:25:57 soren Exp $ */
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/* $NetBSD: mips_machdep.c,v 1.81 2000/05/23 04:21:40 soren Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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@ -52,7 +52,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.80 2000/05/21 04:25:57 soren Exp $");
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__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.81 2000/05/23 04:21:40 soren Exp $");
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#include "opt_compat_netbsd.h"
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#include "opt_compat_ultrix.h"
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@ -129,14 +129,13 @@ int default_pg_mask = 0x00001800;
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int r3900_icache_direct;
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#endif
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/*
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* MIPS-I (r2000 and r3000) locore-function vector.
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* MIPS-I locore function vector
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*/
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mips_locore_jumpvec_t mips1_locore_vec =
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{
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mips1_FlushCache,
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mips1_FlushDCache,
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mips1_FlushICache,
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/*mips1_FlushICache*/ mips1_FlushCache,
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mips1_SetPID,
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mips1_TBIAP,
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mips1_TBIS,
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@ -178,21 +177,13 @@ mips1_vector_init()
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#ifdef MIPS3
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/*
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* MIPS-III (r4000) locore-function vector.
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* MIPS III locore function vector
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*/
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mips_locore_jumpvec_t mips3_locore_vec =
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{
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mips3_FlushCache,
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mips3_FlushDCache,
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mips3_FlushICache,
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#if 0
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/*
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* No such vector exists, perhaps it was meant to be HitFlushDCache?
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*/
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mips3_ForceCacheUpdate,
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#else
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mips3_FlushCache,
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#endif
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mips3_SetPID,
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mips3_TBIAP,
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mips3_TBIS,
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@ -331,7 +322,7 @@ mips3_vector_init()
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* variable cpu_id, into which the kernel locore start code
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* writes the cpu ID register, and to then copy appropriate
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* cod into the CPU exception-vector entries and the jump tables
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* used to hide the differences in cache and TLB handling in
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* used to hide the differences in cache and TLB handling in
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* different MIPS CPUs.
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*
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* This should be the very first thing called by each port's
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@ -388,36 +379,28 @@ mips_vector_init()
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cpu_arch = 3;
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mips_num_tlb_entries = MIPS3_TLB_NUM_TLB_ENTRIES;
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mips3_L1TwoWayCache = 0;
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mips3_cacheflush_bug = 0;
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#if 1 /* XXX FIXME: avoid hangs in mips3_vector_init() */
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mips3_cacheflush_bug = 1;
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#endif
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break;
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case MIPS_R4100:
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cpu_arch = 3;
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mips_num_tlb_entries = 32;
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mips3_L1TwoWayCache = 0;
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mips3_cacheflush_bug = 0;
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break;
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case MIPS_R4300:
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cpu_arch = 3;
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mips_num_tlb_entries = MIPS_R4300_TLB_NUM_TLB_ENTRIES;
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mips3_L1TwoWayCache = 0;
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mips3_cacheflush_bug = 0;
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break;
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case MIPS_R4600:
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cpu_arch = 3;
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mips_num_tlb_entries = MIPS3_TLB_NUM_TLB_ENTRIES;
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mips3_L1TwoWayCache = 1;
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/* disable interrupt while cacheflush to workaround the bug */
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mips3_cacheflush_bug = 1; /* R4600 only??? */
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break;
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#ifdef ENABLE_MIPS_R4700 /* ID conflict */
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case MIPS_R4700:
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cpu_arch = 3;
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mips_num_tlb_entries = MIPS3_TLB_NUM_TLB_ENTRIES;
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mips3_L1TwoWayCache = 1;
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mips3_cacheflush_bug = 0;
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break;
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#endif
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#ifndef ENABLE_MIPS_R3NKK /* ID conflict */
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@ -428,14 +411,12 @@ mips_vector_init()
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cpu_arch = 4;
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mips_num_tlb_entries = MIPS3_TLB_NUM_TLB_ENTRIES;
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mips3_L1TwoWayCache = 1;
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mips3_cacheflush_bug = 0;
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break;
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case MIPS_R10000:
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cpu_arch = 4;
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mips_num_tlb_entries = 64;
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mips3_L1TwoWayCache = 1;
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mips3_cacheflush_bug = 0;
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break;
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#endif /* MIPS3 */
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