Enable cache on the 4000/VLC.
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@ -101,33 +101,22 @@ void
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ka48_cache_enable()
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{
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int i, *tmp;
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return; /*** not yet MK-990306 ***/
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long *par_ctl = (long *)KA48_PARCTL;
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/* Disable caches */
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*(int *)KA48_CCR &= ~CCR_SPECIO;/* secondary */
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mtpr(PCSTS_FLUSH, PR_PCSTS); /* primary */
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*(int *)KA48_BWF0 &= ~BWF0_FEN; /* invalidate filter */
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/* Disable cache */
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mtpr(0, PR_CADR); /* disable */
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*par_ctl &= ~KA48_PARCTL_INVENA; /* clear ? invalid enable */
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mtpr(2, PR_CADR); /* flush */
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/* Clear caches */
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tmp = (void *)KA48_INVFLT; /* inv filter */
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for (i = 0; i < 32768; i++)
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for (i = 0; i < KA48_INVFLTSZ / sizeof(int); i++)
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tmp[i] = 0;
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/* Write valid parity to all primary cache entries */
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for (i = 0; i < 256; i++) {
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mtpr(i << 3, PR_PCIDX);
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mtpr(PCTAG_PARITY, PR_PCTAG);
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}
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/* Secondary cache */
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tmp = (void *)KA48_TAGST;
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for (i = 0; i < KA48_TAGSZ*2; i+=2)
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tmp[i] = 0;
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/* Enable cache */
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*(int *)KA48_BWF0 |= BWF0_FEN; /* invalidate filter */
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mtpr(PCSTS_ENABLE, PR_PCSTS);
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*(int *)KA48_CCR = CCR_SPECIO | CCR_CENA;
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*par_ctl |= KA48_PARCTL_INVENA; /* Enable ???? */
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mtpr(4, PR_CADR); /* enable cache */
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*par_ctl |= (KA48_PARCTL_AGS | /* AGS? */
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KA48_PARCTL_NPEN | /* N? Parity Enable */
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KA48_PARCTL_CPEN); /* Cpu parity enable */
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}
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void
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