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Second try to sort out the dangling elses. Just use {} markers. 

Produces identical on amd64.
This commit is contained in:
joerg 2012-01-12 14:10:56 +00:00
parent b56977fe32
commit a1968c686d
1 changed files with 9 additions and 5 deletions
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14
gnu/usr.bin/rcs/lib/rcsbase.h
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@ -1,4 +1,4 @@
/* $NetBSD: rcsbase.h,v 1.11 2012/01/08 13:57:31 tron Exp $ */
/* $NetBSD: rcsbase.h,v 1.12 2012/01/12 14:10:56 joerg Exp $ */
/* RCS common definitions and data structures */
@ -33,6 +33,10 @@ Report problems and direct all questions to:
/*
* $Log: rcsbase.h,v $
* Revision 1.12 2012/01/12 14:10:56 joerg
* Second try to sort out the dangling elses. Just use {} markers.
* Produces identical on amd64.
*
* Revision 1.11 2012/01/08 13:57:31 tron
* Revert last change. The extra while loop intruced by the macro changes
* causes an end-less loop in ci(1) which uses "break" inside one of the
@ -291,14 +295,14 @@ Report problems and direct all questions to:
# if maps_memory
# define declarecache register Iptr_type ptr, lim
# define setupcache(f) (lim = (f)->lim)
# define Igeteof_(f,c,s) if ((f)->ptr==(f)->lim) s else (c)= *(f)->ptr++;
# define cachegeteof_(c,s) if (ptr==lim) s else (c)= *ptr++;
# define Igeteof_(f,c,s) { if ((f)->ptr==(f)->lim) s else (c)= *(f)->ptr++; }
# define cachegeteof_(c,s) { if (ptr==lim) s else (c)= *ptr++; }
# else
int Igetmore P((RILE*));
# define declarecache register Iptr_type ptr; register RILE *rRILE
# define setupcache(f) (rRILE = (f))
# define Igeteof_(f,c,s) if ((f)->ptr==(f)->readlim && !Igetmore(f)) s else (c)= *(f)->ptr++;
# define cachegeteof_(c,s) if (ptr==rRILE->readlim && !Igetmore(rRILE)) s else (c)= *ptr++;
# define Igeteof_(f,c,s) { if ((f)->ptr==(f)->readlim && !Igetmore(f)) s else (c)= *(f)->ptr++; }
# define cachegeteof_(c,s) { if (ptr==rRILE->readlim && !Igetmore(rRILE)) s else (c)= *ptr++; }
# endif
# define uncache(f) ((f)->ptr = ptr)
# define cache(f) (ptr = (f)->ptr)