Aren/NetBSD
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Alas, Cortex-A8 can't TLB walk out of their caches so they need to sync each PTE.

Browse Source
This commit is contained in:
matt 2012-09-06 04:42:39 +00:00
parent 8d4dcb44cb
commit a137d3a037
1 changed files with 10 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
sys/arch/arm/include/arm32/pmap.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: pmap.h,v 1.108 2012/09/06 02:07:25 matt Exp $ */
/* $NetBSD: pmap.h,v 1.109 2012/09/06 04:42:39 matt Exp $ */
/*
* Copyright (c) 2002, 2003 Wasabi Systems, Inc.
@ -405,7 +405,16 @@ extern int pmap_needs_pte_sync;
#if (ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7 != 0) && (ARM_NMMUS == 1)
#define PMAP_INCLUDE_PTE_SYNC
#if (ARM_MMU_V7 > 0)
#if defined(CPU_CORTEXA8)
#if defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7) || defined(CPU_CORTEXA9) \
|| defined(CPU_CORTEXA15)
#define PMAP_NEEDS_PTE_SYNC CPU_ID_IS_CORTEX_A8(curcpu()->ci_arm_cpuid)
#else
#define PMAP_NEEDS_PTE_SYNC 1
#endif
#else
#define PMAP_NEEDS_PTE_SYNC 0
#endif
#else
#define PMAP_NEEDS_PTE_SYNC 1
#endif