FW_DEBUG: split debug printf in fwohci_intr() and fwohci_phy_input() into
fwohci_show_intr() and fwohci_show_phypkt() respectively.
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onoe
parent
2a68310bea
commit
a0eef76f35
@ -1,4 +1,4 @@
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/* $NetBSD: fwohci.c,v 1.32 2001/06/25 04:52:26 onoe Exp $ */
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/* $NetBSD: fwohci.c,v 1.33 2001/06/28 14:37:56 onoe Exp $ */
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/*-
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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@ -157,6 +157,8 @@ static int fwohci_parse_input(struct fwohci_softc *, void *,
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static int fwohci_submatch(struct device *, struct cfdata *, void *);
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#ifdef FW_DEBUG
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static void fwohci_show_intr(struct fwohci_softc *, u_int32_t);
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static void fwohci_show_phypkt(struct fwohci_softc *, u_int32_t);
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/* 1 is normal debug, 2 is verbose debug, 3 is complete (packet dumps). */
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@ -284,54 +286,9 @@ fwohci_intr(void *arg)
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OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear,
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intmask & ~OHCI_Int_BusReset);
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#ifdef FW_DEBUG
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DPRINTFN(1, ("%s: intmask=0x%08x:",
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sc->sc_sc1394.sc1394_dev.dv_xname, intmask));
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if (intmask & OHCI_Int_CycleTooLong)
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DPRINTFN(1, (" CycleTooLong"));
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if (intmask & OHCI_Int_UnrecoverableError)
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DPRINTFN(1, (" UnrecoverableError"));
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if (intmask & OHCI_Int_CycleInconsistent)
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DPRINTFN(1, (" CycleInconsistent"));
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if (intmask & OHCI_Int_BusReset)
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DPRINTFN(1, (" BusReset"));
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if (intmask & OHCI_Int_SelfIDComplete)
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DPRINTFN(1, (" SelfIDComplete"));
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if (intmask & OHCI_Int_LockRespErr)
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DPRINTFN(1, (" LockRespErr"));
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if (intmask & OHCI_Int_PostedWriteErr)
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DPRINTFN(1, (" PostedWriteErr"));
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if (intmask & OHCI_Int_ReqTxComplete)
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DPRINTFN(1, (" ReqTxComplete(0x%04x)",
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OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST,
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OHCI_SUBREG_ContextControlClear)));
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if (intmask & OHCI_Int_RespTxComplete)
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DPRINTFN(1, (" RespTxComplete(0x%04x)",
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OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE,
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OHCI_SUBREG_ContextControlClear)));
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if (intmask & OHCI_Int_ARRS)
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DPRINTFN(1, (" ARRS(0x%04x)",
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OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE,
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OHCI_SUBREG_ContextControlClear)));
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if (intmask & OHCI_Int_ARRQ)
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DPRINTFN(1, (" ARRQ(0x%04x)",
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OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST,
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OHCI_SUBREG_ContextControlClear)));
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if (intmask & OHCI_Int_IsochRx)
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DPRINTFN(1, (" IsochRx(0x%08x)",
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OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear)));
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if (intmask & OHCI_Int_IsochTx)
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DPRINTFN(1, (" IsochTx(0x%08x)",
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OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear)));
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if (intmask & OHCI_Int_RQPkt)
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DPRINTFN(1, (" RQPkt(0x%04x)",
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OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST,
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OHCI_SUBREG_ContextControlClear)));
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if (intmask & OHCI_Int_RSPkt)
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DPRINTFN(1, (" RSPkt(0x%04x)",
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OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE,
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OHCI_SUBREG_ContextControlClear)));
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DPRINTFN(1, ("\n"));
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#endif /* FW_DEBUG */
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if (fwdebug > 1)
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fwohci_show_intr(sc, intmask);
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#endif
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if (intmask & OHCI_Int_BusReset) {
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/*
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@ -815,7 +772,6 @@ static void
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fwohci_phy_input(struct fwohci_softc *sc, struct fwohci_pkt *pkt)
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{
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u_int32_t val;
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u_int8_t key, phyid;
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val = pkt->fp_hdr[1];
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if (val != ~pkt->fp_hdr[2]) {
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@ -830,48 +786,10 @@ fwohci_phy_input(struct fwohci_softc *sc, struct fwohci_pkt *pkt)
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}
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return;
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}
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key = (val & 0xc0000000) >> 30;
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phyid = (val & 0x3f000000) >> 24;
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switch (key) {
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case 0:
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#ifdef FW_DEBUG
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DPRINTFN(1, ("fwohci_phy_input: PHY Config from %d:", phyid));
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if (val & 0x00800000)
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DPRINTFN(1, (" ForceRoot"));
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if (val & 0x00400000)
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DPRINTFN(1, (" Gap=%x", (val & 0x003f0000) >> 16));
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DPRINTFN(1, ("\n"));
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if (fwdebug > 1)
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fwohci_show_phypkt(sc, val);
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#endif
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break;
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case 1:
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DPRINTFN(1, ("fwohci_phy_input: Link-on from %d\n", phyid));
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break;
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case 2:
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#ifdef FW_DEBUG
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DPRINTFN(1, ("fwohci_phy_input: SelfID from %d:", phyid));
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if (val & 0x00800000) {
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DPRINTFN(1, (" #%d", (val & 0x00700000) >> 20));
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} else {
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if (val & 0x00400000)
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DPRINTFN(1, (" LinkActive"));
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DPRINTFN(1, (" Gap=%x", (val & 0x003f0000) >> 16));
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DPRINTFN(1, (" Spd=S%d",
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100 << ((val & 0x0000c000) >> 14)));
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if (val & 0x00000800)
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DPRINTFN(1, (" Cont"));
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if (val & 0x00000002)
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DPRINTFN(1, (" InitiateBusReset"));
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}
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if (val & 0x00000001)
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DPRINTFN(1, (" +"));
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DPRINTFN(1, ("\n"));
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#endif
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break;
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default:
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printf("%s: unknown PHY packet: 0x%08x\n",
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sc->sc_sc1394.sc1394_dev.dv_xname, val);
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break;
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}
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}
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/*
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@ -3349,3 +3267,103 @@ fwohci_submatch(struct device *parent, struct cfdata *cf, void *aux)
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return ((*cf->cf_attach->ca_match)(parent, cf, aux));
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return 0;
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}
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#ifdef FW_DEBUG
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static void
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fwohci_show_intr(struct fwohci_softc *sc, u_int32_t intmask)
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{
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printf("%s: intmask=0x%08x:", sc->sc_sc1394.sc1394_dev.dv_xname,
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intmask);
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if (intmask & OHCI_Int_CycleTooLong)
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printf(" CycleTooLong");
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if (intmask & OHCI_Int_UnrecoverableError)
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printf(" UnrecoverableError");
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if (intmask & OHCI_Int_CycleInconsistent)
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printf(" CycleInconsistent");
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if (intmask & OHCI_Int_BusReset)
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printf(" BusReset");
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if (intmask & OHCI_Int_SelfIDComplete)
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printf(" SelfIDComplete");
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if (intmask & OHCI_Int_LockRespErr)
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printf(" LockRespErr");
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if (intmask & OHCI_Int_PostedWriteErr)
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printf(" PostedWriteErr");
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if (intmask & OHCI_Int_ReqTxComplete)
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printf(" ReqTxComplete(0x%04x)",
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OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST,
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OHCI_SUBREG_ContextControlClear));
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if (intmask & OHCI_Int_RespTxComplete)
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printf(" RespTxComplete(0x%04x)",
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OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE,
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OHCI_SUBREG_ContextControlClear));
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if (intmask & OHCI_Int_ARRS)
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printf(" ARRS(0x%04x)",
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OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE,
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OHCI_SUBREG_ContextControlClear));
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if (intmask & OHCI_Int_ARRQ)
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printf(" ARRQ(0x%04x)",
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OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST,
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OHCI_SUBREG_ContextControlClear));
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if (intmask & OHCI_Int_IsochRx)
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printf(" IsochRx(0x%08x)",
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OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear));
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if (intmask & OHCI_Int_IsochTx)
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printf(" IsochTx(0x%08x)",
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OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear));
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if (intmask & OHCI_Int_RQPkt)
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printf(" RQPkt(0x%04x)",
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OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST,
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OHCI_SUBREG_ContextControlClear));
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if (intmask & OHCI_Int_RSPkt)
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printf(" RSPkt(0x%04x)",
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OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE,
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OHCI_SUBREG_ContextControlClear));
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printf("\n");
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}
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static void
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fwohci_show_phypkt(struct fwohci_softc *sc, u_int32_t val)
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{
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u_int8_t key, phyid;
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key = (val & 0xc0000000) >> 30;
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phyid = (val & 0x3f000000) >> 24;
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printf("%s: PHY packet from %d: ",
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sc->sc_sc1394.sc1394_dev.dv_xname, phyid);
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switch (key) {
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case 0:
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printf("PHY Config:");
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if (val & 0x00800000)
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printf(" ForceRoot");
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if (val & 0x00400000)
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printf(" Gap=%x", (val & 0x003f0000) >> 16);
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printf("\n");
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break;
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case 1:
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printf("Link-on\n");
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break;
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case 2:
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printf("SelfID:");
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if (val & 0x00800000) {
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printf(" #%d", (val & 0x00700000) >> 20);
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} else {
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if (val & 0x00400000)
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printf(" LinkActive");
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printf(" Gap=%x", (val & 0x003f0000) >> 16);
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printf(" Spd=S%d", 100 << ((val & 0x0000c000) >> 14));
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if (val & 0x00000800)
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printf(" Cont");
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if (val & 0x00000002)
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printf(" InitiateBusReset");
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}
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if (val & 0x00000001)
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printf(" +");
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printf("\n");
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break;
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default:
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printf("unknown: 0x%08x\n", val);
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break;
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}
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}
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#endif /* FW_DEBUG */
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