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Oops. Add the atw(4) sources, too.

This commit is contained in:
dyoung 2003-07-06 22:57:23 +00:00
parent 46a27517aa
commit a036b1536b
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474
sys/dev/cardbus/if_atw_cardbus.c Normal file
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/* $NetBSD: if_atw_cardbus.c,v 1.1 2003/07/06 22:57:23 dyoung Exp $ */
/*-
* Copyright (c) 1999, 2000, 2003 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
* NASA Ames Research Center. This code was adapted for the ADMtek ADM8211
* by David Young.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* CardBus bus front-end for the ADMtek ADM8211 802.11 MAC/BBP driver.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: if_atw_cardbus.c,v 1.1 2003/07/06 22:57:23 dyoung Exp $");
#include "opt_inet.h"
#include "opt_ns.h"
#include "bpfilter.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/mbuf.h>
#include <sys/malloc.h>
#include <sys/kernel.h>
#include <sys/socket.h>
#include <sys/ioctl.h>
#include <sys/errno.h>
#include <sys/device.h>
#include <machine/endian.h>
#include <net/if.h>
#include <net/if_dl.h>
#include <net/if_media.h>
#include <net/if_ether.h>
#include <net/if_ieee80211.h>
#if NBPFILTER > 0
#include <net/bpf.h>
#endif
#ifdef INET
#include <netinet/in.h>
#include <netinet/if_inarp.h>
#endif
#ifdef NS
#include <netns/ns.h>
#include <netns/ns_if.h>
#endif
#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/mii/miivar.h>
#include <dev/mii/mii_bitbang.h>
#include <dev/ic/atwreg.h>
#include <dev/ic/atwvar.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcidevs.h>
#include <dev/cardbus/cardbusvar.h>
#include <dev/cardbus/cardbusdevs.h>
/*
* PCI configuration space registers used by the ADM8211.
*/
#define ATW_PCI_IOBA 0x10 /* i/o mapped base */
#define ATW_PCI_MMBA 0x14 /* memory mapped base */
struct atw_cardbus_softc {
struct atw_softc sc_atw; /* real ADM8211 softc */
/* CardBus-specific goo. */
void *sc_ih; /* interrupt handle */
cardbus_devfunc_t sc_ct; /* our CardBus devfuncs */
cardbustag_t sc_tag; /* our CardBus tag */
int sc_csr; /* CSR bits */
bus_size_t sc_mapsize; /* the size of mapped bus space
region */
int sc_cben; /* CardBus enables */
int sc_bar_reg; /* which BAR to use */
pcireg_t sc_bar_val; /* value of the BAR */
int sc_intrline; /* interrupt line */
};
int atw_cardbus_match __P((struct device *, struct cfdata *, void *));
void atw_cardbus_attach __P((struct device *, struct device *, void *));
int atw_cardbus_detach __P((struct device *, int));
CFATTACH_DECL(atw_cardbus, sizeof(struct atw_cardbus_softc),
atw_cardbus_match, atw_cardbus_attach, atw_cardbus_detach, atw_activate);
void atw_cardbus_setup __P((struct atw_cardbus_softc *));
int atw_cardbus_enable __P((struct atw_softc *));
void atw_cardbus_disable __P((struct atw_softc *));
void atw_cardbus_power __P((struct atw_softc *, int));
static void atw_cardbus_intr_ack(struct atw_softc *);
const struct atw_cardbus_product *atw_cardbus_lookup
__P((const struct cardbus_attach_args *));
const struct atw_cardbus_product {
u_int32_t acp_vendor; /* PCI vendor ID */
u_int32_t acp_product; /* PCI product ID */
const char *acp_product_name;
} atw_cardbus_products[] = {
{ PCI_VENDOR_ADMTEK, PCI_PRODUCT_ADMTEK_ADM8211,
"ADMtek ADM8211 802.11 MAC/BBP" },
{ 0, 0, NULL },
};
const struct atw_cardbus_product *
atw_cardbus_lookup(ca)
const struct cardbus_attach_args *ca;
{
const struct atw_cardbus_product *acp;
for (acp = atw_cardbus_products;
acp->acp_product_name != NULL;
acp++) {
if (PCI_VENDOR(ca->ca_id) == acp->acp_vendor &&
PCI_PRODUCT(ca->ca_id) == acp->acp_product)
return (acp);
}
return (NULL);
}
int
atw_cardbus_match(parent, match, aux)
struct device *parent;
struct cfdata *match;
void *aux;
{
struct cardbus_attach_args *ca = aux;
if (atw_cardbus_lookup(ca) != NULL)
return (1);
return (0);
}
void
atw_cardbus_attach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct atw_cardbus_softc *csc = (void *)self;
struct atw_softc *sc = &csc->sc_atw;
struct cardbus_attach_args *ca = aux;
cardbus_devfunc_t ct = ca->ca_ct;
const struct atw_cardbus_product *acp;
bus_addr_t adr;
int rev;
sc->sc_dmat = ca->ca_dmat;
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
acp = atw_cardbus_lookup(ca);
if (acp == NULL) {
printf("\n");
panic("atw_cardbus_attach: impossible");
}
/*
* Power management hooks.
*/
sc->sc_enable = atw_cardbus_enable;
sc->sc_disable = atw_cardbus_disable;
sc->sc_power = atw_cardbus_power;
sc->sc_intr_ack = atw_cardbus_intr_ack;
/* Get revision info. */
rev = PCI_REVISION(ca->ca_class);
printf(": %s\n", acp->acp_product_name);
#if 0
printf("%s: pass %d.%d signature %08x\n", sc->sc_dev.dv_xname,
(rev >> 4) & 0xf, rev & 0xf,
cardbus_conf_read(ct->ct_cc, ct->ct_cf, csc->sc_tag, 0x80));
#endif
/*
* Map the device.
*/
csc->sc_csr = CARDBUS_COMMAND_MASTER_ENABLE;
if (Cardbus_mapreg_map(ct, ATW_PCI_MMBA,
CARDBUS_MAPREG_TYPE_MEM, 0, &sc->sc_st, &sc->sc_sh, &adr,
&csc->sc_mapsize) == 0) {
#if 0
printf("%s: atw_cardbus_attach mapped %d bytes mem space\n",
sc->sc_dev.dv_xname, csc->sc_mapsize);
#endif
#if rbus
#else
(*ct->ct_cf->cardbus_mem_open)(cc, 0, adr, adr+csc->sc_mapsize);
#endif
csc->sc_cben = CARDBUS_MEM_ENABLE;
csc->sc_csr |= CARDBUS_COMMAND_MEM_ENABLE;
csc->sc_bar_reg = ATW_PCI_MMBA;
csc->sc_bar_val = adr | CARDBUS_MAPREG_TYPE_MEM;
} else if (Cardbus_mapreg_map(ct, ATW_PCI_IOBA,
CARDBUS_MAPREG_TYPE_IO, 0, &sc->sc_st, &sc->sc_sh, &adr,
&csc->sc_mapsize) == 0) {
#if 0
printf("%s: atw_cardbus_attach mapped %d bytes I/O space\n",
sc->sc_dev.dv_xname, csc->sc_mapsize);
#endif
#if rbus
#else
(*ct->ct_cf->cardbus_io_open)(cc, 0, adr, adr+csc->sc_mapsize);
#endif
csc->sc_cben = CARDBUS_IO_ENABLE;
csc->sc_csr |= CARDBUS_COMMAND_IO_ENABLE;
csc->sc_bar_reg = ATW_PCI_IOBA;
csc->sc_bar_val = adr | CARDBUS_MAPREG_TYPE_IO;
} else {
printf("%s: unable to map device registers\n",
sc->sc_dev.dv_xname);
return;
}
/*
* Bring the chip out of powersave mode and initialize the
* configuration registers.
*/
atw_cardbus_setup(csc);
/* Remember which interrupt line. */
csc->sc_intrline = ca->ca_intrline;
printf("%s: interrupting at %d\n", sc->sc_dev.dv_xname,
csc->sc_intrline);
#if 0
/*
* The CardBus cards will make it to store-and-forward mode as
* soon as you put them under any kind of load, so just start
* out there.
*/
sc->sc_txthresh = 3; /* TBD name constant */
#endif
/*
* Finish off the attach.
*/
atw_attach(sc);
ATW_WRITE(sc, ATW_FER, ATW_FER_INTR);
/*
* Power down the socket.
*/
Cardbus_function_disable(csc->sc_ct);
}
static void
atw_cardbus_intr_ack(sc)
struct atw_softc *sc;
{
ATW_WRITE(sc, ATW_FER, ATW_FER_INTR);
}
int
atw_cardbus_detach(self, flags)
struct device *self;
int flags;
{
struct atw_cardbus_softc *csc = (void *)self;
struct atw_softc *sc = &csc->sc_atw;
struct cardbus_devfunc *ct = csc->sc_ct;
int rv;
#if defined(DIAGNOSTIC)
if (ct == NULL)
panic("%s: data structure lacks", sc->sc_dev.dv_xname);
#endif
rv = atw_detach(sc);
if (rv)
return (rv);
/*
* Unhook the interrupt handler.
*/
if (csc->sc_ih != NULL)
cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih);
/*
* Release bus space and close window.
*/
if (csc->sc_bar_reg != 0)
Cardbus_mapreg_unmap(ct, csc->sc_bar_reg,
sc->sc_st, sc->sc_sh, csc->sc_mapsize);
return (0);
}
int
atw_cardbus_enable(sc)
struct atw_softc *sc;
{
struct atw_cardbus_softc *csc = (void *) sc;
cardbus_devfunc_t ct = csc->sc_ct;
cardbus_chipset_tag_t cc = ct->ct_cc;
cardbus_function_tag_t cf = ct->ct_cf;
/*
* Power on the socket.
*/
Cardbus_function_enable(ct);
/*
* Set up the PCI configuration registers.
*/
atw_cardbus_setup(csc);
/*
* Map and establish the interrupt.
*/
csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, IPL_NET,
atw_intr, sc);
if (csc->sc_ih == NULL) {
printf("%s: unable to establish interrupt at %d\n",
sc->sc_dev.dv_xname, csc->sc_intrline);
Cardbus_function_disable(csc->sc_ct);
return (1);
}
return (0);
}
void
atw_cardbus_disable(sc)
struct atw_softc *sc;
{
struct atw_cardbus_softc *csc = (void *) sc;
cardbus_devfunc_t ct = csc->sc_ct;
cardbus_chipset_tag_t cc = ct->ct_cc;
cardbus_function_tag_t cf = ct->ct_cf;
/* Unhook the interrupt handler. */
cardbus_intr_disestablish(cc, cf, csc->sc_ih);
csc->sc_ih = NULL;
/* Power down the socket. */
Cardbus_function_disable(ct);
}
void
atw_cardbus_power(sc, why)
struct atw_softc *sc;
int why;
{
struct atw_cardbus_softc *csc = (void *) sc;
printf("%s: atw_cardbus_power\n", sc->sc_dev.dv_xname);
if (why == PWR_RESUME) {
/*
* Give the PCI configuration registers a kick
* in the head.
*/
#ifdef DIAGNOSTIC
if (ATW_IS_ENABLED(sc) == 0)
panic("atw_cardbus_power");
#endif
atw_cardbus_setup(csc);
}
}
void
atw_cardbus_setup(csc)
struct atw_cardbus_softc *csc;
{
struct atw_softc *sc = &csc->sc_atw;
cardbus_devfunc_t ct = csc->sc_ct;
cardbus_chipset_tag_t cc = ct->ct_cc;
cardbus_function_tag_t cf = ct->ct_cf;
pcireg_t reg;
int pmreg;
if (cardbus_get_capability(cc, cf, csc->sc_tag,
PCI_CAP_PWRMGMT, &pmreg, 0)) {
reg = cardbus_conf_read(cc, cf, csc->sc_tag, pmreg + 4) & 0x03;
#if 1 /* XXX Probably not right for CardBus. */
if (reg == 3) {
/*
* The card has lost all configuration data in
* this state, so punt.
*/
printf("%s: unable to wake up from power state D3\n",
sc->sc_dev.dv_xname);
return;
}
#endif
if (reg != 0) {
printf("%s: waking up from power state D%d\n",
sc->sc_dev.dv_xname, reg);
cardbus_conf_write(cc, cf, csc->sc_tag,
pmreg + 4, 0);
}
}
/* Make sure the right access type is on the CardBus bridge. */
(*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_cben);
(*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
/* Program the BAR. */
cardbus_conf_write(cc, cf, csc->sc_tag, csc->sc_bar_reg,
csc->sc_bar_val);
/* Enable the appropriate bits in the PCI CSR. */
reg = cardbus_conf_read(cc, cf, csc->sc_tag,
CARDBUS_COMMAND_STATUS_REG);
reg &= ~(CARDBUS_COMMAND_IO_ENABLE|CARDBUS_COMMAND_MEM_ENABLE);
reg |= csc->sc_csr;
cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_COMMAND_STATUS_REG,
reg);
/*
* Make sure the latency timer is set to some reasonable
* value.
*/
reg = cardbus_conf_read(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG);
if (CARDBUS_LATTIMER(reg) < 0x20) {
reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT);
reg |= (0x20 << CARDBUS_LATTIMER_SHIFT);
cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG, reg);
}
}

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/* $NetBSD: atwreg.h,v 1.1 2003/07/06 22:58:09 dyoung Exp $ */
/*
* Copyright (c) 2003 The NetBSD Foundation, Inc. All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by David Young.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY David Young AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL David Young
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/* glossary */
/* DTIM Delivery Traffic Indication Map, sent by AP
* ATIM Ad Hoc Traffic Indication Map
* TU 1024 microseconds
* TSF time synchronization function
* TBTT target beacon transmission time
* DIFS distributed inter-frame space
* SIFS short inter-frame space
* EIFS extended inter-frame space
*/
/* Macros for bit twiddling. */
/* nth bit, BIT(0) == 0x1. */
#define BIT(n) (((n) == 32) ? 0 : ((u_int32_t) 1 << (n)))
/* bits m through n, m < n. */
#define BITS(m, n) ((BIT(MAX((m), (n)) + 1) - 1) ^ (BIT(MIN((m), (n))) - 1))
/* find least significant bit that is set */
#define LOWEST_SET_BIT(x) ((((x) - 1) & (x)) ^ (x))
/* for x a power of two and p a non-negative integer, is x a greater power than 2**p? */
#define GTEQ_POWER(x, p) (((u_long)(x) >> (p)) != 0)
#define MASK_TO_SHIFT(m) ((GTEQ_POWER(LOWEST_SET_BIT((m)), 31) ? 31 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 30) ? 30 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 29) ? 29 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 28) ? 28 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 27) ? 27 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 26) ? 26 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 25) ? 25 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 24) ? 24 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 23) ? 23 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 22) ? 22 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 21) ? 21 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 20) ? 20 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 19) ? 19 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 18) ? 18 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 17) ? 17 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 16) ? 16 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 15) ? 15 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 14) ? 14 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 13) ? 13 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 12) ? 12 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 11) ? 11 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 10) ? 10 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 9) ? 9 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 8) ? 8 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 7) ? 7 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 6) ? 6 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 5) ? 5 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 4) ? 4 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 3) ? 3 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 2) ? 2 : \
(GTEQ_POWER(LOWEST_SET_BIT((m)), 1) ? 1 : 0))))))))))))))))))))))))))))))))
#define MASK_AND_RSHIFT(x, mask) (((x) & (mask)) >> MASK_TO_SHIFT(mask))
#define LSHIFT(x, mask) ((x) << MASK_TO_SHIFT(mask))
#define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask))
/* ADM8211 Host Control and Status Registers */
#define ATW_PAR 0x00 /* PCI access */
#define ATW_FRCTL 0x04 /* Frame control */
#define ATW_TDR 0x08 /* Transmit demand */
#define ATW_WTDP 0x0C /* Current transmit descriptor pointer */
#define ATW_RDR 0x10 /* Receive demand */
#define ATW_WRDP 0x14 /* Current receive descriptor pointer */
#define ATW_RDB 0x18 /* Receive descriptor base address */
#define ATW_CSR3A 0x1C /* Unused */
#define ATW_TDBD 0x20 /* Transmit descriptor base address, DCF */
#define ATW_TDBP 0x24 /* Transmit descriptor base address, PCF */
#define ATW_STSR 0x28 /* Status */
#define ATW_CSR5A 0x2C /* Unused */
#define ATW_NAR 0x30 /* Network access */
#define ATW_CSR6A 0x34 /* Unused */
#define ATW_IER 0x38 /* Interrupt enable */
#define ATW_CSR7A 0x3C
#define ATW_LPC 0x40 /* Lost packet counter */
#define ATW_TEST1 0x44 /* Test register 1 */
#define ATW_SPR 0x48 /* Serial port */
#define ATW_TEST0 0x4C /* Test register 0 */
#define ATW_WCSR 0x50 /* Wake-up control/status */
#define ATW_WPDR 0x54 /* Wake-up pattern data */
#define ATW_GPTMR 0x58 /* General purpose timer */
#define ATW_GPIO 0x5C /* GPIO[5:0] configuration and control */
#define ATW_BBPCTL 0x60 /* BBP control port */
#define ATW_SYNCTL 0x64 /* synthesizer control port */
#define ATW_PLCPHD 0x68 /* PLCP header setting */
#define ATW_MMIWADDR 0x6C /* MMI write address */
#define ATW_MMIRADDR1 0x70 /* MMI read address 1 */
#define ATW_MMIRADDR2 0x74 /* MMI read address 2 */
#define ATW_TXBR 0x78 /* Transmit burst counter */
#define ATW_CSR15A 0x7C /* Unused */
#define ATW_ALCSTAT 0x80 /* ALC statistics */
#define ATW_TOFS2 0x84 /* Timing offset parameter 2, 16b */
#define ATW_CMDR 0x88 /* Command */
#define ATW_PCIC 0x8C /* PCI bus performance counter */
#define ATW_PMCSR 0x90 /* Power management command and status */
#define ATW_PAR0 0x94 /* Local MAC address register 0, 32b */
#define ATW_PAR1 0x98 /* Local MAC address register 1, 16b */
#define ATW_MAR0 0x9C /* Multicast address hash table register 0 */
#define ATW_MAR1 0xA0 /* Multicast address hash table register 1 */
#define ATW_ATIMDA0 0xA4 /* Ad Hoc Traffic Indication Map (ATIM)
* frame DA, byte[3:0]
*/
#define ATW_ABDA1 0xA8 /* BSSID address byte[5:4];
* ATIM frame DA byte[5:4]
*/
#define ATW_BSSID0 0xAC /* BSSID address byte[3:0] */
#define ATW_TXLMT 0xB0 /* WLAN retry limit, 8b;
* Max TX MSDU lifetime, 16b
*/
#define ATW_MIBCNT 0xB4 /* RTS/ACK/FCS MIB count, 32b */
#define ATW_BCNT 0xB8 /* Beacon transmission time, 32b */
#define ATW_TSFTH 0xBC /* TSFT[63:32], 32b */
#define ATW_TSC 0xC0 /* TSFT[39:32] down count value */
#define ATW_SYNRF 0xC4 /* SYN RF IF direct control */
#define ATW_BPLI 0xC8 /* Beacon interval, 16b.
* STA listen interval, 16b.
*/
#define ATW_CAP0 0xCC /* Current channel, 4b. RCVDTIM, 1b. */
#define ATW_CAP1 0xD0 /* Capability information, 16b.
* ATIM window, 1b.
*/
#define ATW_RMD 0xD4 /* RX max reception duration, 16b */
#define ATW_CFPP 0xD8 /* CFP parameter, 32b */
#define ATW_TOFS0 0xDC /* Timing offset parameter 0, 28b */
#define ATW_TOFS1 0xE0 /* Timing offset parameter 1, 24b */
#define ATW_IFST 0xE4 /* IFS timing parameter 1, 32b */
#define ATW_RSPT 0xE8 /* Response time, 24b */
#define ATW_TSFTL 0xEC /* TSFT[31:0], 32b */
#define ATW_WEPCTL 0xF0 /* WEP control */
#define ATW_WESK 0xF4 /* Write entry for shared/individual key */
#define ATW_WEPCNT 0xF8 /* WEP count */
#define ATW_MACTEST 0xFC
#define ATW_FER 0x100 /* Function event */
#define ATW_FEMR 0x104 /* Function event mask */
#define ATW_FPSR 0x108 /* Function present state */
#define ATW_FFER 0x10C /* Function force event */
#define ATW_PAR_MWIE BIT(24) /* memory write and invalidate
* enable
*/
#define ATW_PAR_MRLE BIT(23) /* memory read line enable */
#define ATW_PAR_MRME BIT(21) /* memory read multiple
* enable
*/
#define ATW_PAR_RAP_MASK BITS(17, 18) /* receive auto-polling in
* receive suspended state
*/
#define ATW_PAR_CAL_MASK BITS(14, 15) /* cache alignment */
#define ATW_PAR_CAL_PBL 0x0
/* min(8 DW, PBL) */
#define ATW_PAR_CAL_8DW LSHIFT(0x1, ATW_PAR_CAL_MASK)
/* min(16 DW, PBL) */
#define ATW_PAR_CAL_16DW LSHIFT(0x2, ATW_PAR_CAL_MASK)
/* min(32 DW, PBL) */
#define ATW_PAR_CAL_32DW LSHIFT(0x3, ATW_PAR_CAL_MASK)
#define ATW_PAR_PBL_MASK BITS(8, 13) /* programmable burst length */
#define ATW_PAR_PBL_UNLIMITED 0x0
#define ATW_PAR_PBL_1DW LSHIFT(0x1, ATW_PAR_PBL_MASK)
#define ATW_PAR_PBL_2DW LSHIFT(0x2, ATW_PAR_PBL_MASK)
#define ATW_PAR_PBL_4DW LSHIFT(0x4, ATW_PAR_PBL_MASK)
#define ATW_PAR_PBL_8DW LSHIFT(0x8, ATW_PAR_PBL_MASK)
#define ATW_PAR_PBL_16DW LSHIFT(0x16, ATW_PAR_PBL_MASK)
#define ATW_PAR_PBL_32DW LSHIFT(0x32, ATW_PAR_PBL_MASK)
#define ATW_PAR_BLE BIT(7) /* big/little endian selection */
#define ATW_PAR_DSL_MASK BITS(2, 6) /* descriptor skip length */
#define ATW_PAR_BAR BIT(1) /* bus arbitration */
#define ATW_PAR_SWR BIT(0) /* software reset */
#define ATW_FRCTL_PWRMGMT BIT(31) /* power management */
#define ATW_FRCTL_VER_MASK BITS(29, 30) /* protocol version */
#define ATW_FRCTL_ORDER BIT(28) /* order bit */
#define ATW_FRCTL_MAXPSP BIT(27) /* maximum power saving */
#define ATW_FRCTL_DOZEFRM BIT(18) /* select pre-sleep frame */
#define ATW_FRCTL_PSAWAKE BIT(17) /* MAC is awake (?) */
#define ATW_FRCTL_PSMODE BIT(16) /* MAC is power-saving (?) */
#define ATW_FRCTL_AID_MASK BITS(0, 15) /* STA Association ID */
#define ATW_INTR_PCF BIT(31) /* started/ended CFP */
#define ATW_INTR_BCNTC BIT(30) /* transmitted IBSS beacon */
#define ATW_INTR_GPINT BIT(29) /* GPIO interrupt */
#define ATW_INTR_LINKOFF BIT(28) /* lost ATW_WCSR_BLN beacons */
#define ATW_INTR_ATIMTC BIT(27) /* transmitted ATIM */
#define ATW_INTR_TSFTF BIT(26) /* TSFT out of range */
#define ATW_INTR_TSCZ BIT(25) /* TSC countdown expired */
#define ATW_INTR_LINKON BIT(24) /* matched SSID, BSSID */
#define ATW_INTR_SQL BIT(23) /* Marvel signal quality */
#define ATW_INTR_WEPTD BIT(22) /* switched WEP table */
#define ATW_INTR_ATIME BIT(21) /* ended ATIM window */
#define ATW_INTR_TBTT BIT(20) /* (TBTT) Target Beacon TX Time
* passed
*/
#define ATW_INTR_NISS BIT(16) /* normal interrupt status
* summary: any of 31, 30, 27,
* 24, 14, 12, 6, 2, 0.
*/
#define ATW_INTR_AISS BIT(15) /* abnormal interrupt status
* summary: any of 29, 28, 26,
* 25, 23, 22, 13, 11, 8, 7, 5,
* 4, 3, 1.
*/
#define ATW_INTR_TEIS BIT(14) /* transmit early interrupt
* status: moved TX packet to
* FIFO
*/
#define ATW_INTR_FBE BIT(13) /* fatal bus error */
#define ATW_INTR_REIS BIT(12) /* receive early interrupt
* status: RX packet filled
* its first descriptor
*/
#define ATW_INTR_GPTT BIT(11) /* general purpose timer expired */
#define ATW_INTR_RPS BIT(8) /* stopped receive process */
#define ATW_INTR_RDU BIT(7) /* receive descriptor
* unavailable
*/
#define ATW_INTR_RCI BIT(6) /* completed packet reception */
#define ATW_INTR_TUF BIT(5) /* transmit underflow */
#define ATW_INTR_TRT BIT(4) /* transmit retry count
* expired
*/
#define ATW_INTR_TLT BIT(3) /* transmit lifetime exceeded */
#define ATW_INTR_TDU BIT(2) /* transmit descriptor
* unavailable
*/
#define ATW_INTR_TPS BIT(1) /* stopped transmit process */
#define ATW_INTR_TCI BIT(0) /* completed transmit */
#define ATW_NAR_TXCF BIT(31) /* stop process on TX failure */
#define ATW_NAR_HF BIT(30) /* flush TX FIFO to host (?) */
#define ATW_NAR_UTR BIT(29) /* select retry count source */
#define ATW_NAR_PCF BIT(28) /* use one/both transmit
* descriptor base addresses
*/
#define ATW_NAR_CFP BIT(27) /* indicate more TX data to
* point coordinator
*/
#define ATW_NAR_SF BIT(21) /* store and forward: ignore
* TX threshold
*/
#define ATW_NAR_TR_MASK BITS(14, 15) /* TX threshold */
#define ATW_NAR_TR_L64 LSHIFT(0x0, ATW_NAR_TR_MASK)
#define ATW_NAR_TR_L160 LSHIFT(0x2, ATW_NAR_TR_MASK)
#define ATW_NAR_TR_L192 LSHIFT(0x3, ATW_NAR_TR_MASK)
#define ATW_NAR_TR_H96 LSHIFT(0x0, ATW_NAR_TR_MASK)
#define ATW_NAR_TR_H288 LSHIFT(0x2, ATW_NAR_TR_MASK)
#define ATW_NAR_TR_H544 LSHIFT(0x3, ATW_NAR_TR_MASK)
#define ATW_NAR_ST BIT(13) /* start/stop transmit */
#define ATW_NAR_OM_MASK BITS(10, 11) /* operating mode */
#define ATW_NAR_OM_NORMAL 0x0
#define ATW_NAR_OM_LOOPBACK LSHIFT(0x1, ATW_NAR_OM_MASK)
#define ATW_NAR_MM BIT(7) /* RX any multicast */
#define ATW_NAR_PR BIT(6) /* promiscuous mode */
#define ATW_NAR_EA BIT(5) /* match ad hoc packets (?) */
#define ATW_NAR_PB BIT(3) /* pass bad packets */
#define ATW_NAR_STPDMA BIT(2) /* stop DMA, abort packet */
#define ATW_NAR_SR BIT(1) /* start/stop receive */
#define ATW_NAR_CTX BIT(0) /* continuous TX mode */
/* IER bits are identical to STSR bits. Use ATW_INTR_*. */
#if 0
#define ATW_IER_NIE BIT(16) /* normal interrupt enable */
#define ATW_IER_AIE BIT(15) /* abnormal interrupt enable */
/* normal interrupts: combine with ATW_IER_NIE */
#define ATW_IER_PCFIE BIT(31) /* STA entered CFP */
#define ATW_IER_BCNTCIE BIT(30) /* STA TX'd beacon */
#define ATW_IER_ATIMTCIE BIT(27) /* transmitted ATIM */
#define ATW_IER_LINKONIE BIT(24) /* matched beacon */
#define ATW_IER_ATIMIE BIT(21) /* ended ATIM window */
#define ATW_IER_TBTTIE BIT(20) /* TBTT */
#define ATW_IER_TEIE BIT(14) /* moved TX packet to FIFO */
#define ATW_IER_REIE BIT(12) /* RX packet filled its first
* descriptor
*/
#define ATW_IER_RCIE BIT(6) /* completed RX */
#define ATW_IER_TDUIE BIT(2) /* transmit descriptor
* unavailable
*/
#define ATW_IER_TCIE BIT(0) /* completed TX */
/* abnormal interrupts: combine with ATW_IER_AIE */
#define ATW_IER_GPIE BIT(29) /* GPIO interrupt */
#define ATW_IER_LINKOFFIE BIT(28) /* lost beacon */
#define ATW_IER_TSFTFIE BIT(26) /* TSFT out of range */
#define ATW_IER_TSCIE BIT(25) /* TSC countdown expired */
#define ATW_IER_SQLIE BIT(23) /* signal quality */
#define ATW_IER_WEPIE BIT(22) /* finished WEP table switch */
#define ATW_IER_FBEIE BIT(13) /* fatal bus error */
#define ATW_IER_GPTIE BIT(11) /* general purpose timer expired */
#define ATW_IER_RPSIE BIT(8) /* stopped receive process */
#define ATW_IER_RUIE BIT(7) /* receive descriptor unavailable */
#define ATW_IER_TUIE BIT(5) /* transmit underflow */
#define ATW_IER_TRTIE BIT(4) /* exceeded transmit retry count */
#define ATW_IER_TLTTIE BIT(3) /* transmit lifetime exceeded */
#define ATW_IER_TPSIE BIT(1) /* stopped transmit process */
#endif
#define ATW_LPC_LPCO BIT(16) /* lost packet counter overflow */
#define ATW_LPC_LPC_MASK BITS(0, 15) /* lost packet counter */
#define ATW_SPR_SRS BIT(11) /* activate SEEPROM access */
#define ATW_SPR_SDO BIT(3) /* data out of SEEPROM */
#define ATW_SPR_SDI BIT(2) /* data into SEEPROM */
#define ATW_SPR_SCLK BIT(1) /* SEEPROM clock */
#define ATW_SPR_SCS BIT(0) /* SEEPROM chip select */
/* TBD CSR_TEST0 */
#define ATW_TEST0_BE_MASK BITS(31, 29) /* Bus error state */
#define ATW_TEST0_TS_MASK BITS(28, 26) /* Transmit process state */
/* Stopped */
#define ATW_TEST0_TS_STOPPED LSHIFT(0, ATW_TEST0_TS_MASK)
/* Running - fetch transmit descriptor */
#define ATW_TEST0_TS_FETCH LSHIFT(1, ATW_TEST0_TS_MASK)
/* Running - wait for end of transmission */
#define ATW_TEST0_TS_WAIT LSHIFT(2, ATW_TEST0_TS_MASK)
/* Running - read buffer from memory and queue into FIFO */
#define ATW_TEST0_TS_READING LSHIFT(3, ATW_TEST0_TS_MASK)
#define ATW_TEST0_TS_RESERVED1 LSHIFT(4, ATW_TEST0_TS_MASK)
#define ATW_TEST0_TS_RESERVED2 LSHIFT(5, ATW_TEST0_TS_MASK)
/* Suspended */
#define ATW_TEST0_TS_SUSPENDED LSHIFT(6, ATW_TEST0_TS_MASK)
/* Running - close transmit descriptor */
#define ATW_TEST0_TS_CLOSE LSHIFT(7, ATW_TEST0_TS_MASK)
#define ATW_TEST0_RS_MASK BITS(25, 23) /* Receive process state */
/* Stopped */
#define ATW_TEST0_RS_STOPPED LSHIFT(0, ATW_TEST0_RS_MASK)
/* Running - fetch receive descriptor */
#define ATW_TEST0_RS_FETCH LSHIFT(1, ATW_TEST0_RS_MASK)
/* Running - check for end of receive */
#define ATW_TEST0_RS_CHECK LSHIFT(2, ATW_TEST0_RS_MASK)
/* Running - wait for packet */
#define ATW_TEST0_RS_WAIT LSHIFT(3, ATW_TEST0_RS_MASK)
/* Suspended */
#define ATW_TEST0_RS_SUSPENDED LSHIFT(4, ATW_TEST0_RS_MASK)
/* Running - close receive descriptor */
#define ATW_TEST0_RS_CLOSE LSHIFT(5, ATW_TEST0_RS_MASK)
/* Running - flush current frame from FIFO */
#define ATW_TEST0_RS_FLUSH LSHIFT(6, ATW_TEST0_RS_MASK)
/* Running - queue current frame from FIFO into buffer */
#define ATW_TEST0_RS_QUEUE LSHIFT(7, ATW_TEST0_RS_MASK)
#define ATW_TEST0_EPNE BIT(18) /* SEEPROM not detected */
#define ATW_TEST0_EPSNM BIT(17) /* SEEPROM bad signature */
#define ATW_TEST0_EPTYP_MASK BIT(16) /* SEEPROM type
* 1: 93c66,
* 0: 93c46
*/
#define ATW_TEST0_EPTYP_93c66 ATW_TEST0_EPTYP_MASK
#define ATW_TEST0_EPTYP_93c46 0
#define ATW_TEST0_EPRLD BIT(15) /* recall SEEPROM (write 1) */
#define ATW_WCSR_CRCT BIT(30) /* CRC-16 type */
#define ATW_WCSR_WP1E BIT(29) /* match wake-up pattern 1 */
#define ATW_WCSR_WP2E BIT(28) /* match wake-up pattern 2 */
#define ATW_WCSR_WP3E BIT(27) /* match wake-up pattern 3 */
#define ATW_WCSR_WP4E BIT(26) /* match wake-up pattern 4 */
#define ATW_WCSR_WP5E BIT(25) /* match wake-up pattern 5 */
#define ATW_WCSR_BLN_MASK BITS(21, 23) /* lose link after BLN lost
* beacons
*/
#define ATW_WCSR_TSFTWE BIT(20) /* wake up on TSFT out of
* range
*/
#define ATW_WCSR_TIMWE BIT(19) /* wake up on TIM */
#define ATW_WCSR_ATIMWE BIT(18) /* wake up on ATIM */
#define ATW_WCSR_KEYWE BIT(17) /* wake up on key update */
#define ATW_WCSR_WFRE BIT(10) /* wake up on wake-up frame */
#define ATW_WCSR_MPRE BIT(9) /* wake up on magic packet */
#define ATW_WCSR_LSOE BIT(8) /* wake up on link loss */
/* wake-up reasons correspond to enable bits */
#define ATW_WCSR_KEYUP BIT(6) /* */
#define ATW_WCSR_TSFTW BIT(5) /* */
#define ATW_WCSR_TIMW BIT(4) /* */
#define ATW_WCSR_ATIMW BIT(3) /* */
#define ATW_WCSR_WFR BIT(2) /* */
#define ATW_WCSR_MPR BIT(1) /* */
#define ATW_WCSR_LSO BIT(0) /* */
#define ATW_GPTMR_COM_MASK BIT(16) /* continuous operation mode */
#define ATW_GPTMR_GTV_MASK BITS(0, 15) /* set countdown in 204us ticks */
#define ATW_GPIO_EC1_MASK BITS(25, 24) /* GPIO1 event configuration */
#define ATW_GPIO_LAT_MASK BITS(21, 20) /* input latch */
#define ATW_GPIO_INTEN_MASK BITS(19, 18) /* interrupt enable */
#define ATW_GPIO_EN_MASK BITS(17, 12) /* output enable */
#define ATW_GPIO_O_MASK BITS(11, 6) /* output value */
#define ATW_GPIO_I_MASK BITS(5, 0) /* pin static input */
#define ATW_BBPCTL_TWI BIT(31) /* Intersil 3-wire interface */
#define ATW_BBPCTL_RF3KADDR_MASK BITS(30, 24) /* Address for RF3000 */
#define ATW_BBPCTL_RF3KADDR_ADDR LSHIFT(0x20, ATW_BBPCTL_RF3KADDR_MASK)
#define ATW_BBPCTL_NEGEDGE_DO BIT(23) /* data-out on negative edge */
#define ATW_BBPCTL_NEGEDGE_DI BIT(22) /* data-in on negative edge */
#define ATW_BBPCTL_CCA_ACTLO BIT(21) /* CCA low when busy */
#define ATW_BBPCTL_TYPE_MASK BITS(20, 18) /* BBP type */
#define ATW_BBPCTL_WR BIT(17) /* start write; reset on
* completion
*/
#define ATW_BBPCTL_RD BIT(16) /* start read; reset on
* completion
*/
#define ATW_BBPCTL_ADDR_MASK BITS(15, 8) /* BBP address */
#define ATW_BBPCTL_DATA_MASK BITS(7, 0) /* BBP data */
#define ATW_SYNCTL_WR BIT(31) /* start write; reset on
* completion
*/
#define ATW_SYNCTL_RD BIT(30) /* start read; reset on
* completion
*/
#define ATW_SYNCTL_CS0 BIT(29) /* chip select */
#define ATW_SYNCTL_CS1 BIT(28)
#define ATW_SYNCTL_CAL BIT(27) /* generate RF CAL pulse after
* Rx
*/
#define ATW_SYNCTL_SELCAL BIT(26) /* RF CAL source, 0: CAL bit,
* 1: MAC; needed by Intersil
* BBP
*/
#define ATW_SYNCTL_RFTYPE_MASK BITS(24, 22) /* RF type */
#define ATW_SYNCTL_DATA_MASK BITS(21, 0) /* synthesizer setting */
#define ATW_PLCPHD_SIGNAL_MASK BITS(31, 24) /* signal field in PLCP header,
* only for beacon, ATIM, and
* RTS.
*/
#define ATW_PLCPHD_SERVICE_MASK BITS(23, 16) /* service field in PLCP
* header
*/
#define ATW_PLCPHD_PMBL BIT(15) /* 0: long preamble, 1: short */
#define ATW_MMIWADDR_INTERSIL 0x100E0C0A
#define ATW_MMIWADDR_RFMD 0x00009101
#define ATW_MMIRADDR1_INTERSIL 0x00007c7e
#define ATW_MMIRADDR1_RFMD 0x00000301
#define ATW_MMIRADDR2_INTERSIL 0x00100000
#define ATW_MMIRADDR2_RFMD 0x7e100000
#define ATW_TXBR_ALCUPDATE_MASK BIT(31) /* auto-update BBP with ALCSET */
#define ATW_TXBR_TBCNT_MASK BITS(16, 20) /* transmit burst count */
#define ATW_TXBR_ALCSET_MASK BITS(8, 15) /* TX power level set point */
#define ATW_TXBR_ALCREF_MASK BITS(0, 7) /* TX power level reference point */
#define ATW_ALCSTAT_MCOV_MASK BIT(27) /* MPDU count overflow */
#define ATW_ALCSTAT_ESOV_MASK BIT(26) /* error sum overflow */
#define ATW_ALCSTAT_MCNT_MASK BITS(16, 25) /* MPDU count, unsigned integer */
#define ATW_ALCSTAT_ERSUM_MASK BITS(0, 15) /* power error sum,
* 2's complement signed integer
*/
#define ATW_TOFS2_PWR1UP_MASK BITS(31, 28) /* delay of Tx/Rx from PE1,
* Radio, PHYRST change after
* power-up, in 2ms units
*/
#define ATW_TOFS2_PWR0PAPE_MASK BITS(27, 24) /* delay of PAPE going low
* after internal data
* transmit end, in us
*/
#define ATW_TOFS2_PWR1PAPE_MASK BITS(23, 20) /* delay of PAPE going high
* after TXPE asserted, in us
*/
#define ATW_TOFS2_PWR0TRSW_MASK BITS(19, 16) /* delay of TRSW going low
* after internal data transmit
* end, in us
*/
#define ATW_TOFS2_PWR1TRSW_MASK BITS(15, 12) /* delay of TRSW going high
* after TXPE asserted, in us
*/
#define ATW_TOFS2_PWR0PE2_MASK BITS(11, 8) /* delay of PE2 going low
* after internal data transmit
* end, in us
*/
#define ATW_TOFS2_PWR1PE2_MASK BITS(7, 4) /* delay of PE2 going high
* after TXPE asserted, in us
*/
#define ATW_TOFS2_PWR0TXPE_MASK BITS(3, 0) /* delay of TXPE going low
* after internal data transmit
* end, in us
*/
#define ATW_CMDR_PM BIT(19) /* enables power mgmt
* capabilities.
*/
#define ATW_CMDR_APM BIT(18) /* APM mode, effective when
* PM = 1.
*/
#define ATW_CMDR_RTE BIT(4) /* enable Rx FIFO threshold */
#define ATW_CMDR_DRT_MASK BITS(3, 2) /* drain Rx FIFO threshold */
#define ATW_CMDR_SINT_MASK BIT(1) /* software interrupt---huh? */
/* TBD PCIC */
/* TBD PMCSR */
#define ATW_PAR0_PAB0_MASK BITS(0, 7) /* MAC address byte 0 */
#define ATW_PAR0_PAB1_MASK BITS(8, 15) /* MAC address byte 1 */
#define ATW_PAR0_PAB2_MASK BITS(16, 23) /* MAC address byte 2 */
#define ATW_PAR0_PAB3_MASK BITS(24, 31) /* MAC address byte 3 */
#define ATW_PAR1_PAB5_MASK BITS(8, 15) /* MAC address byte 5 */
#define ATW_PAR1_PAB4_MASK BITS(0, 7) /* MAC address byte 4 */
#define ATW_MAR0_MAB3_MASK BITS(31, 24) /* multicast table bits 31:24 */
#define ATW_MAR0_MAB2_MASK BITS(23, 16) /* multicast table bits 23:16 */
#define ATW_MAR0_MAB1_MASK BITS(15, 8) /* multicast table bits 15:8 */
#define ATW_MAR0_MAB0_MASK BITS(7, 0) /* multicast table bits 7:0 */
#define ATW_MAR1_MAB7_MASK BITS(31, 24) /* multicast table bits 63:56 */
#define ATW_MAR1_MAB6_MASK BITS(23, 16) /* multicast table bits 55:48 */
#define ATW_MAR1_MAB5_MASK BITS(15, 8) /* multicast table bits 47:40 */
#define ATW_MAR1_MAB4_MASK BITS(7, 0) /* multicast table bits 39:32 */
/* ATIM destination address */
#define ATW_ATIMDA0_ATIMB3_MASK BITS(31,24)
#define ATW_ATIMDA0_ATIMB2_MASK BITS(23,16)
#define ATW_ATIMDA0_ATIMB1_MASK BITS(15,8)
#define ATW_ATIMDA0_ATIMB0_MASK BITS(7,0)
/* ATIM destination address, BSSID */
#define ATW_ABDA1_BSSIDB5_MASK BITS(31,24)
#define ATW_ABDA1_BSSIDB4_MASK BITS(23,16)
#define ATW_ABDA1_ATIMB5_MASK BITS(15,8)
#define ATW_ABDA1_ATIMB4_MASK BITS(7,0)
/* BSSID */
#define ATW_BSSID0_BSSIDB3_MASK BITS(31,24)
#define ATW_BSSID0_BSSIDB2_MASK BITS(23,16)
#define ATW_BSSID0_BSSIDB1_MASK BITS(15,8)
#define ATW_BSSID0_BSSIDB0_MASK BITS(7,0)
#define ATW_TXLMT_MTMLT_MASK BITS(31,16) /* max TX MSDU lifetime in TU */
#define ATW_TXLMT_SRTYLIM_MASK BITS(7,0) /* short retry limit */
#define ATW_MIBCNT_FFCNT_MASK BITS(31,24) /* FCS failure count */
#define ATW_MIBCNT_AFCNT_MASK BITS(23,16) /* ACK failure count */
#define ATW_MIBCNT_RSCNT_MASK BITS(15,8) /* RTS success count */
#define ATW_MIBCNT_RFCNT_MASK BITS(7,0) /* RTS failure count */
#define ATW_BCNT_PLCPH_MASK BITS(23,16) /* 11M PLCP length (us) */
#define ATW_BCNT_PLCPL_MASK BITS(15,8) /* 5.5M PLCP length (us) */
#define ATW_BCNT_BCNT_MASK BITS(7,0) /* byte count of beacon frame */
#define ATW_TSC_TSC_MASK BITS(3,0) /* TSFT countdown value */
#define ATW_SYNRF_SELSYN BIT(31) /* 0: MAC controls SYN IF pins,
* 1: ATW_SYNRF controls SYN IF pins.
*/
#define ATW_SYNRF_SELRF BIT(30) /* 0: MAC controls RF IF pins,
* 1: ATW_SYNRF controls RF IF pins.
*/
#define ATW_SYNRF_LERF BIT(29) /* if SELSYN = 1, direct control of
* LERF# pin
*/
#define ATW_SYNRF_LEIF BIT(28) /* if SELSYN = 1, direct control of
* LEIF# pin
*/
#define ATW_SYNRF_SYNCLK BIT(27) /* if SELSYN = 1, direct control of
* SYNCLK pin
*/
#define ATW_SYNRF_SYNDATA BIT(26) /* if SELSYN = 1, direct control of
* SYNDATA pin
*/
#define ATW_SYNRF_PE1 BIT(25) /* if SELRF = 1, direct control of
* PE1 pin
*/
#define ATW_SYNRF_PE2 BIT(24) /* if SELRF = 1, direct control of
* PE2 pin
*/
#define ATW_SYNRF_PAPE BIT(23) /* if SELRF = 1, direct control of
* PAPE pin
*/
#define ATW_SYNRF_INTERSIL_EN BIT(20) /* if SELRF = 1, enables
* some signal used by the
* Intersil RF front-end?
* Undocumented.
*/
#define ATW_SYNRF_PHYRST BIT(18) /* if SELRF = 1, direct control of
* PHYRST# pin
*/
#define ATW_BPLI_BP_MASK BITS(31,16) /* beacon interval in TU */
#define ATW_BPLI_LI_MASK BITS(15,0) /* STA listen interval in
* beacon intervals
*/
#define ATW_CAP0_RCVDTIM BIT(4) /* receive every DTIM */
#define ATW_CAP0_CHN_MASK BITS(3,0) /* current DSSS channel */
#define ATW_CAP1_CAPI_MASK BITS(31,16) /* capability information */
#define ATW_CAP1_ATIMW_MASK BITS(15,0) /* ATIM window in TU */
#define ATW_RMD_ATIMST BIT(31) /* ATIM frame TX status */
#define ATW_RMD_CFP BIT(30) /* CFP indicator */
#define ATW_RMD_PCNT BITS(27,16) /* idle time between
* awake/ps mode
*/
#define ATW_RMD_RMRD BITS(15,0) /* max RX reception duration
* in us
*/
#define ATW_CFPP_CFPP BITS(31,24) /* CFP unit DTIM */
#define ATW_CFPP_CFPMD BITS(23,8) /* CFP max duration in TU */
#define ATW_CFPP_DTIMP BITS(7,0) /* DTIM period in beacon
* intervals
*/
#define ATW_TOFS0_USCNT_MASK BITS(29,24) /* number of system clocks
* in 1 microsecond.
* Depends PCI bus speed?
*/
#define ATW_TOFS0_TUCNT_MASK BITS(9,0) /* TU counter in microseconds */
/* TBD TOFS1 */
#define ATW_TOFS1_TSFTOFSR_MASK BITS(31,24) /* RX TSFT offset in
* microseconds: RF+BBP
* latency
*/
#define ATW_TOFS1_TBTTPRE_MASK BITS(23,8) /* prediction time, (next
* Nth TBTT - TBTTOFS) in
* microseconds (huh?). To
* match TSFT[25:10] (huh?).
*/
#define ATW_TOFS1_TBTTOFS_MASK BITS(7,0) /* wake-up time offset before
* TBTT in TU
*/
#define ATW_IFST_SLOT_MASK BITS(27,23) /* SLOT time in us */
#define ATW_IFST_SIFS_MASK BITS(22,15) /* SIFS time in us */
#define ATW_IFST_DIFS_MASK BITS(14,9) /* DIFS time in us */
#define ATW_IFST_EIFS_MASK BITS(8,0) /* EIFS time in us */
#define ATW_RSPT_MART_MASK BITS(31,16) /* max response time in us */
#define ATW_RSPT_MIRT_MASK BITS(15,8) /* min response time in us */
#define ATW_RSPT_TSFTOFST_MASK BITS(7,0) /* TX TSFT offset in us */
#define ATW_WEPCTL_WEPENABLE BIT(31) /* enable WEP engine */
#define ATW_WEPCTL_AUTOSWITCH BIT(30) /* auto-switch enable (huh?) */
#define ATW_WEPCTL_CURTBL BIT(29) /* current table in use */
#define ATW_WEPCTL_WR BIT(28) /* */
#define ATW_WEPCTL_RD BIT(27) /* */
#define ATW_WEPCTL_WEPRXBYP BIT(25) /* bypass WEP on RX */
#define ATW_WEPCTL_UNKNOWN0 BIT(23) /* has something to do with
* revision 0x20. Possibly
* selects a different WEP
* table.
*/
#define ATW_WEPCTL_TBLADD_MASK BITS(8,0) /* add to table */
/* set these bits in the second byte of a SRAM shared key record to affect
* the use and interpretation of the key in the record.
*/
#define ATW_WEP_ENABLED BIT(7)
#define ATW_WEP_104BIT BIT(6)
#define ATW_WESK_DATA_MASK BITS(15,0) /* data */
#define ATW_WEPCNT_WIEC_MASK BITS(15,0) /* WEP ICV error count */
#define ATW_MACTEST_FORCE_IV BIT(23)
#define ATW_MACTEST_FORCE_KEYID BIT(22)
#define ATW_MACTEST_KEYID_MASK BITS(21,20)
#define ATW_MACTEST_MMI_USETXCLK BIT(11)
/* Function Event/Status registers */
#define ATW_FER_INTR BIT(15) /* interrupt: set regardless of mask */
#define ATW_FER_GWAKE BIT(4) /* general wake-up: set regardless of mask */
#define ATW_FEMR_INTR_EN BIT(15) /* enable INTA# */
#define ATW_FEMR_WAKEUP_EN BIT(14) /* enable wake-up */
#define ATW_FEMR_GWAKE_EN BIT(4) /* enable general wake-up */
#define ATW_FPSR_INTR_STATUS BIT(15) /* interrupt status */
#define ATW_FPSR_WAKEUP_STATUS BIT(4) /* CSTSCHG state */
#define ATW_FFER_INTA_FORCE BIT(15) /* activate INTA (if not masked) */
#define ATW_FFER_GWAKE_FORCE BIT(4) /* activate CSTSCHG (if not masked) */
/* Serial EEPROM offsets */
#define ATW_SR_CLASS_CODE (0x00/2)
#define ATW_SR_FORMAT_VERSION (0x02/2)
#define ATW_SR_MAC00 (0x08/2) /* CSR21 */
#define ATW_SR_MAC01 (0x0A/2) /* CSR21/22 */
#define ATW_SR_MAC10 (0x0C/2) /* CSR22 */
#define ATW_SR_CSR20 (0x16/2)
#define ATW_SR_ANT_MASK BITS(12, 10)
#define ATW_SR_PWRSCALE_MASK BITS(9, 8)
#define ATW_SR_CLKSAVE_MASK BITS(7, 6)
#define ATW_SR_RFTYPE_MASK BITS(5, 3)
#define ATW_SR_BBPTYPE_MASK BITS(2, 0)
#define ATW_SR_CR28_CR03 (0x18/2)
#define ATW_SR_CTRY_CR29 (0x1A/2)
#define ATW_SR_CTRY_MASK BITS(15,8) /* country code */
#define COUNTRY_FCC LSHIFT(0, ATW_SR_CTRY_MASK)
#define COUNTRY_IC LSHIFT(1, ATW_SR_CTRY_MASK)
#define COUNTRY_ETSI LSHIFT(2, ATW_SR_CTRY_MASK)
#define COUNTRY_SPAIN LSHIFT(3, ATW_SR_CTRY_MASK)
#define COUNTRY_FRANCE LSHIFT(4, ATW_SR_CTRY_MASK)
#define COUNTRY_MMK LSHIFT(5, ATW_SR_CTRY_MASK)
#define COUNTRY_MMK2 LSHIFT(6, ATW_SR_CTRY_MASK)
#define ATW_SR_PCI_DEVICE (0x20/2) /* CR0 */
#define ATW_SR_PCI_VENDOR (0x22/2) /* CR0 */
#define ATW_SR_SUB_DEVICE (0x24/2) /* CR11 */
#define ATW_SR_SUB_VENDOR (0x26/2) /* CR11 */
#define ATW_SR_CR15 (0x28/2)
#define ATW_SR_LOCISPTR (0x2A/2) /* CR10 */
#define ATW_SR_HICISPTR (0x2C/2) /* CR10 */
#define ATW_SR_CSR18 (0x2E/2)
#define ATW_SR_D0_D1_PWR (0x40/2) /* CR49 */
#define ATW_SR_D2_D3_PWR (0x42/2) /* CR49 */
#define ATW_SR_CIS_WORDS (0x52/2)
/* CR17 of RFMD RF3000 BBP: returns TWO channels */
#define ATW_SR_TXPOWER(chnl) (0x54/2 + ((chnl) - 1)/2)
/* CR20 of RFMD RF3000 BBP: returns TWO channels */
#define ATW_SR_LPF_CUTOFF(chnl) (0x62/2 + ((chnl) - 1)/2)
/* CR21 of RFMD RF3000 BBP: returns TWO channels */
#define ATW_SR_LNA_GS_THRESH(chnl) (0x70/2 + ((chnl) - 1)/2)
#define ATW_SR_CHECKSUM (0x7e/2) /* for data 0x00-0x7d */
#define ATW_SR_CIS (0x80/2) /* Cardbus CIS */
/* Tx descriptor */
struct atw_txdesc {
u_int32_t at_ctl;
#define at_stat at_ctl
u_int32_t at_flags;
u_int32_t at_buf1;
u_int32_t at_buf2;
};
#define ATW_TXCTL_OWN BIT(31) /* 1: ready to transmit */
#define ATW_TXCTL_DONE BIT(30) /* 0: not processed */
#define ATW_TXCTL_TXDR_MASK BITS(27,20) /* TX data rate (?) */
#define ATW_TXCTL_TL_MASK BITS(19,0) /* retry limit, 0 - 255 */
#define ATW_TXSTAT_OWN ATW_TXCTL_OWN /* 0: not for transmission */
#define ATW_TXSTAT_DONE ATW_TXCTL_DONE /* 1: been processed */
#define ATW_TXSTAT_ES BIT(29) /* 0: TX successful */
#define ATW_TXSTAT_TLT BIT(28) /* TX lifetime expired */
#define ATW_TXSTAT_TRT BIT(27) /* TX retry limit expired */
#define ATW_TXSTAT_TUF BIT(26) /* TX under-run error */
#define ATW_TXSTAT_TRO BIT(25) /* TX over-run error */
#define ATW_TXSTAT_SOFBR BIT(24) /* packet size != buffer size
* (?)
*/
#define ATW_TXSTAT_ARC_MASK BITS(11,0) /* accumulated retry count */
#define ATW_TXFLAG_IC BIT(31) /* interrupt on completion */
#define ATW_TXFLAG_LS BIT(30) /* packet's last descriptor */
#define ATW_TXFLAG_FS BIT(29) /* packet's first descriptor */
#define ATW_TXFLAG_TER BIT(25) /* end of ring */
#define ATW_TXFLAG_TCH BIT(24) /* at_buf2 is 2nd chain */
#define ATW_TXFLAG_TBS2_MASK BITS(23,12) /* at_buf2 byte count */
#define ATW_TXFLAG_TBS1_MASK BITS(11,0) /* at_buf1 byte count */
/* Rx descriptor */
struct atw_rxdesc {
u_int32_t ar_stat;
u_int32_t ar_ctl;
u_int32_t ar_buf1;
u_int32_t ar_buf2;
};
#define ar_rssi ar_ctl
#define ATW_RXCTL_RER BIT(25) /* end of ring */
#define ATW_RXCTL_RCH BIT(24) /* ar_buf2 is 2nd chain */
#define ATW_RXCTL_RBS2_MASK BITS(23,12) /* ar_buf2 byte count */
#define ATW_RXCTL_RBS1_MASK BITS(11,0) /* ar_buf1 byte count */
#define ATW_RXSTAT_OWN BIT(31) /* 1: NIC may fill descriptor */
#define ATW_RXSTAT_ES BIT(30) /* error summary, 0 on
* success
*/
#define ATW_RXSTAT_SQL BIT(29) /* has signal quality (?) */
#define ATW_RXSTAT_DE BIT(28) /* descriptor error---packet is
* truncated. last descriptor
* only
*/
#define ATW_RXSTAT_FS BIT(27) /* packet's first descriptor */
#define ATW_RXSTAT_LS BIT(26) /* packet's last descriptor */
#define ATW_RXSTAT_PCF BIT(25) /* received during CFP */
#define ATW_RXSTAT_SFDE BIT(24) /* PLCP SFD error */
#define ATW_RXSTAT_SIGE BIT(23) /* PLCP signal error */
#define ATW_RXSTAT_CRC16E BIT(22) /* PLCP CRC16 error */
#define ATW_RXSTAT_RXTOE BIT(21) /* RX time-out, last descriptor
* only.
*/
#define ATW_RXSTAT_CRC32E BIT(20) /* CRC32 error */
#define ATW_RXSTAT_ICVE BIT(19) /* WEP ICV error */
#define ATW_RXSTAT_DA1 BIT(17) /* DA bit 1, admin'd address */
#define ATW_RXSTAT_DA0 BIT(16) /* DA bit 0, group address */
#define ATW_RXSTAT_RXDR_MASK BITS(15,12) /* RX data rate */
#define ATW_RXSTAT_FL_MASK BITS(11,0) /* RX frame length, last
* descriptor only
*/
/* Static RAM (contains WEP keys, beacon content). Addresses and size
* are in 16-bit words.
*/
#define ATW_SRAM_ADDR_INDIVL_KEY 0x0
#define ATW_SRAM_ADDR_SHARED_KEY (0x160 * 2)
#define ATW_SRAM_ADDR_SSID (0x180 * 2)
#define ATW_SRAM_ADDR_SUPRATES (0x191 * 2)
#define ATW_SRAM_SIZE (0x200 * 2)
/*
* Registers for Silicon Laboratories Si4126/Si4126 RF synthesizer.
*/
#define SI4126_MAIN 0 /* main configuration */
#define SI4126_MAIN_AUXSEL_MASK BITS(13, 12)
#define SI4126_MAIN_IFDIV_MASK BITS(11, 10)
#define SI4126_MAIN_XINDIV2 BIT(6)
#define SI4126_MAIN_LPWR BIT(5)
#define SI4126_MAIN_AUTOPDB BIT(3)
#define SI4126_GAIN 1 /* phase detector gain */
#define SI4126_GAIN_KPI_MASK BITS(5, 4)
#define SI4126_GAIN_KP2_MASK BITS(3, 2)
#define SI4126_GAIN_KP1_MASK BITS(1, 0)
#define SI4126_POWER 2 /* powerdown */
#define SI4126_POWER_PDIB BIT(1)
#define SI4126_POWER_PDRB BIT(0)
#define SI4126_RF1N 3 /* RF1 N divider */
#define SI4126_RF2N 4 /* RF2 N divider */
#define SI4126_IFN 5 /* IF N divider */
#define SI4126_RF1R 6 /* RF1 R divider */
#define SI4126_RF2R 7 /* RF2 R divider */
#define SI4126_IFR 8 /* IF R divider */
/*
* Registers for RF Microdevices RF3000 spread-spectrum baseband modem.
*/
#define RF3000_CTL 0x01 /* modem control */
#define RF3000_RXSTAT RF3000_CTL /* RX status */
#define RF3000_CTL_MODE_MASK BITS(7, 4)
#define RF3000_RXSTAT_ACQ BIT(2)
#define RF3000_RXSTAT_SFD BIT(1)
#define RF3000_RXSTAT_CRC BIT(0)
#define RF3000_CCACTL 0x02 /* CCA control */
/* CCA mode */
#define RF3000_CCACTL_MODE_MASK BITS(7, 6)
#define RF3000_CCACTL_MODE_RSSIT 0 /* RSSI threshold */
#define RF3000_CCACTL_MODE_ACQ 1 /* acquisition */
#define RF3000_CCACTL_MODE_BOTH 2 /* threshold or acq. */
/* RSSI threshold for CCA */
#define RF3000_CCACTL_RSSIT_MASK BITS(5, 0)
#define RF3000_DIVCTL 0x03 /* diversity control */
#define RF3000_DIVCTL_ENABLE BIT(7) /* enable diversity */
#define RF3000_DIVCTL_ANTSEL BIT(6) /* if ENABLE = 0, set
* ANT SEL
*/
#define RF3000_RSSI RF3000_DIVCTL /* RSSI value */
#define RF3000_RSSI_MASK BITS(5, 0)
#define RF3000_GAINCTL 0x11 /* TX variable gain control */
#define RF3000_GAINCTL_TXVGC_MASK BITS(7, 2)
#define RF3000_GAINCTL_SCRAMBLER BIT(1)
#define RF3000_LOGAINCAL 0x14 /* low gain calibration */
#define RF3000_LOGAINCAL_CAL_MASK BITS(5, 0)
#define RF3000_HIGAINCAL 0x15 /* high gain calibration */
#define RF3000_HIGAINCAL_CAL_MASK BITS(5, 0)
#define RF3000_HIGAINCAL_DSSSPAD BIT(6) /* 6dB gain pad for DSSS
* modes (meaning?)
*/
#define RF3000_MAGIC0 0x1C /* magic register derived from
* a binary-only driver
*/
#define RF3000_MAGIC0_VAL 0x00
#define RF3000_MAGIC1 0x1D /* magic register derived from
* a binary-only driver
*/
#define RF3000_MAGIC1_VAL 0x80

408
sys/dev/ic/atwvar.h Normal file
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@ -0,0 +1,408 @@
/* $NetBSD: atwvar.h,v 1.1 2003/07/06 22:58:09 dyoung Exp $ */
/*
* Copyright (c) 2003, 2004 The NetBSD Foundation, Inc. All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by David Young.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY David Young AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL David Young
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _DEV_IC_ATWVAR_H_
#define _DEV_IC_ATWVAR_H_
#include <sys/queue.h>
#include <sys/callout.h>
#include <sys/time.h>
#if 0
#endif
/*
* Some misc. statics, useful for debugging.
*/
struct atw_stats {
u_long ts_tx_tuf; /* transmit underflow errors */
u_long ts_tx_tro; /* transmit jabber timeouts */
u_long ts_tx_trt; /* retry count exceeded */
u_long ts_tx_tlt; /* lifetime exceeded */
u_long ts_tx_sofbr; /* packet size mismatch */
};
/*
* Transmit descriptor list size. This is arbitrary, but allocate
* enough descriptors for 64 pending transmissions and 16 segments
* per packet. Since a descriptor holds 2 buffer addresses, that's
* 8 descriptors per packet. This MUST work out to a power of 2.
*/
#define ATW_NTXSEGS 16
#define ATW_TXQUEUELEN 64
#define ATW_NTXDESC (ATW_TXQUEUELEN * ATW_NTXSEGS)
#define ATW_NTXDESC_MASK (ATW_NTXDESC - 1)
#define ATW_NEXTTX(x) ((x + 1) & ATW_NTXDESC_MASK)
/*
* Receive descriptor list size. We have one Rx buffer per incoming
* packet, so this logic is a little simpler.
*/
#define ATW_NRXDESC 64
#define ATW_NRXDESC_MASK (ATW_NRXDESC - 1)
#define ATW_NEXTRX(x) ((x + 1) & ATW_NRXDESC_MASK)
/*
* Control structures are DMA'd to the ADM8211 chip. We allocate them in
* a single clump that maps to a single DMA segment to make several things
* easier.
*/
struct atw_control_data {
/*
* The transmit descriptors.
*/
struct atw_txdesc acd_txdescs[ATW_NTXDESC];
/*
* The receive descriptors.
*/
struct atw_rxdesc acd_rxdescs[ATW_NRXDESC];
};
#define ATW_CDOFF(x) offsetof(struct atw_control_data, x)
#define ATW_CDTXOFF(x) ATW_CDOFF(acd_txdescs[(x)])
#define ATW_CDRXOFF(x) ATW_CDOFF(acd_rxdescs[(x)])
/*
* Software state for transmit jobs.
*/
struct atw_txsoft {
struct mbuf *txs_mbuf; /* head of our mbuf chain */
bus_dmamap_t txs_dmamap; /* our DMA map */
int txs_firstdesc; /* first descriptor in packet */
int txs_lastdesc; /* last descriptor in packet */
int txs_ndescs; /* number of descriptors */
SIMPLEQ_ENTRY(atw_txsoft) txs_q;
};
SIMPLEQ_HEAD(atw_txsq, atw_txsoft);
/*
* Software state for receive jobs.
*/
struct atw_rxsoft {
struct mbuf *rxs_mbuf; /* head of our mbuf chain */
bus_dmamap_t rxs_dmamap; /* our DMA map */
};
/*
* Table which describes the transmit threshold mode. We generally
* start at index 0. Whenever we get a transmit underrun, we increment
* our index, falling back if we encounter the NULL terminator.
*/
struct atw_txthresh_tab {
u_int32_t txth_opmode; /* OPMODE bits */
const char *txth_name; /* name of mode */
};
#define ATW_TXTHRESH_TAB_LO_RATE { \
{ ATW_NAR_TR_L64, "64 bytes" }, \
{ ATW_NAR_TR_L160, "160 bytes" }, \
{ ATW_NAR_TR_L192, "192 bytes" }, \
{ ATW_NAR_SF, "store and forward" }, \
{ 0, NULL }, \
}
#define ATW_TXTHRESH_TAB_HI_RATE { \
{ ATW_NAR_TR_H96, "96 bytes" }, \
{ ATW_NAR_TR_H288, "288 bytes" }, \
{ ATW_NAR_TR_H544, "544 bytes" }, \
{ ATW_NAR_SF, "store and forward" }, \
{ 0, NULL }, \
}
enum atw_rftype { ATW_RFTYPE_INTERSIL = 0, ATW_RFTYPE_RFMD = 1,
ATW_RFTYPE_MARVEL = 2 };
enum atw_bbptype { ATW_BBPTYPE_INTERSIL = 0, ATW_BBPTYPE_RFMD = 1,
ATW_BBPTYPE_MARVEL = 2 };
struct atw_softc {
struct device sc_dev;
struct ieee80211com sc_ic;
void *sc_ih; /* interrupt handler */
int (*sc_enable)(struct atw_softc *);
void (*sc_disable)(struct atw_softc *);
void (*sc_power)(struct atw_softc *, int);
int sc_pci; /* attach to PCI-Bus */
struct atw_stats sc_stats; /* debugging stats */
int sc_tx_timer;
int sc_rescan_timer;
bus_space_tag_t sc_st; /* bus space tag */
bus_space_handle_t sc_sh; /* bus space handle */
bus_dma_tag_t sc_dmat; /* bus dma tag */
void *sc_sdhook; /* shutdown hook */
void *sc_powerhook; /* power management hook */
u_int32_t sc_cacheline; /* cache line size */
u_int32_t sc_maxburst; /* maximum burst length */
const struct atw_txthresh_tab *sc_txth;
int sc_txthresh; /* current tx threshold */
u_int sc_cur_chan; /* current channel */
int sc_flags;
u_int16_t *sc_srom;
u_int16_t sc_sromsz;
caddr_t sc_radiobpf;
bus_dma_segment_t sc_cdseg; /* control data memory */
int sc_cdnseg; /* number of segments */
bus_dmamap_t sc_cddmamap; /* control data DMA map */
#define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
/*
* Software state for transmit and receive descriptors.
*/
struct atw_txsoft sc_txsoft[ATW_TXQUEUELEN];
struct atw_rxsoft sc_rxsoft[ATW_NRXDESC];
/*
* Control data structures.
*/
struct atw_control_data *sc_control_data;
#define sc_txdescs sc_control_data->acd_txdescs
#define sc_rxdescs sc_control_data->acd_rxdescs
#define sc_setup_desc sc_control_data->acd_setup_desc
int sc_txfree; /* number of free Tx descriptors */
int sc_txnext; /* next ready Tx descriptor */
int sc_ntxsegs; /* number of transmit segs per pkt */
struct atw_txsq sc_txfreeq; /* free Tx descsofts */
struct atw_txsq sc_txdirtyq; /* dirty Tx descsofts */
int sc_rxptr; /* next ready RX descriptor/descsoft */
u_int32_t sc_busmode; /* copy of ATW_PAR */
u_int32_t sc_opmode; /* copy of ATW_NAR */
u_int32_t sc_inten; /* copy of ATW_IER */
u_int32_t sc_wepctl; /* copy of ATW_WEPCTL */
u_int32_t sc_rxint_mask; /* mask of Rx interrupts we want */
u_int32_t sc_txint_mask; /* mask of Tx interrupts we want */
u_int32_t sc_linkint_mask;/* link-state interrupts mask */
/* interrupt acknowledge hook */
void (*sc_intr_ack) __P((struct atw_softc *));
enum atw_rftype sc_rftype;
enum atw_bbptype sc_bbptype;
u_int32_t sc_synctl_rd;
u_int32_t sc_synctl_wr;
u_int32_t sc_bbpctl_rd;
u_int32_t sc_bbpctl_wr;
void (*sc_recv_beacon)(struct ieee80211com *, struct mbuf *,
int, u_int32_t);
void (*sc_recv_prresp)(struct ieee80211com *, struct mbuf *,
int, u_int32_t);
/* ADM8211 state variables. */
u_int8_t sc_sram[ATW_SRAM_SIZE];
u_int8_t sc_bssid[IEEE80211_ADDR_LEN];
u_int8_t sc_lost_bcn_thresh;
struct timeval sc_last_beacon;
struct callout sc_scan_timer;
};
#define sc_if sc_ic.ic_if
/* XXX this is fragile. try not to introduce any u_int32_t's. */
struct atw_frame {
/*00*/ u_int8_t atw_dst[IEEE80211_ADDR_LEN];
/*06*/ u_int8_t atw_rate; /* TX rate in 100Kbps */
/*07*/ u_int8_t atw_service; /* 0 */
/*08*/ u_int16_t atw_paylen; /* payload length */
/*0a*/ u_int8_t atw_fc[2]; /* 802.11 Frame
* Control
*/
/* 802.11 PLCP Length for first & last fragment */
/*0c*/ u_int16_t atw_tail_plcplen;
/*0e*/ u_int16_t atw_head_plcplen;
/* 802.11 Duration for first & last fragment */
/*10*/ u_int16_t atw_tail_dur;
/*12*/ u_int16_t atw_head_dur;
/*14*/ u_int8_t atw_addr4[IEEE80211_ADDR_LEN];
union {
struct {
/*1a*/ u_int16_t hdrctl; /*transmission control*/
/*1c*/ u_int16_t fragthr;/* fragmentation threshold
* [0:11], zero [12:15].
*/
/*1e*/ u_int8_t fragnum;/* fragment number [4:7],
* zero [0:3].
*/
/*1f*/ u_int8_t rtylmt; /* retry limit */
/*20*/ u_int8_t wepkey0[4];/* ??? */
/*24*/ u_int8_t wepkey1[4];/* ??? */
/*28*/ u_int8_t wepkey2[4];/* ??? */
/*2c*/ u_int8_t wepkey3[4];/* ??? */
/*30*/ u_int8_t keyid;
/*31*/ u_int8_t reserved0[7];
} s;
struct ieee80211_frame_addr4 ihdr;
} u;
} __attribute__((__packed__));
#define atw_hdrctl u.s.hdrctl
#define atw_fragthr u.s.fragthr
#define atw_fragnum u.s.fragnum
#define atw_rtylmt u.s.rtylmt
#define atw_keyid u.s.keyid
#define atw_ihdr u.ihdr
#define ATW_HDRCTL_SHORT_PREAMBLE BIT(0) /* use short preamble */
#define ATW_HDRCTL_RTSCTS BIT(4) /* send RTS */
#define ATW_HDRCTL_WEP BIT(5)
#define ATW_HDRCTL_UNKNOWN1 BIT(15) /* MAC adds FCS? */
#define ATW_HDRCTL_UNKNOWN2 BIT(8)
#define ATW_FRAGTHR_FRAGTHR_MASK BITS(0, 11)
#define ATW_FRAGNUM_FRAGNUM_MASK BITS(4, 7)
/* Values for sc_flags. */
#define ATWF_MRL 0x00000010 /* memory read line okay */
#define ATWF_MRM 0x00000020 /* memory read multi okay */
#define ATWF_MWI 0x00000040 /* memory write inval okay */
#define ATWF_SHORT_PREAMBLE 0x00000080 /* short preamble enabled */
#define ATWF_RTSCTS 0x00000100 /* RTS/CTS enabled */
#define ATWF_ATTACHED 0x00000800 /* attach has succeeded */
#define ATWF_ENABLED 0x00001000 /* chip is enabled */
#define ATW_IS_ENABLED(sc) ((sc)->sc_flags & ATWF_ENABLED)
#define ATW_CDTXADDR(sc, x) ((sc)->sc_cddma + ATW_CDTXOFF((x)))
#define ATW_CDRXADDR(sc, x) ((sc)->sc_cddma + ATW_CDRXOFF((x)))
#define ATW_CDTXSYNC(sc, x, n, ops) \
do { \
int __x, __n; \
\
__x = (x); \
__n = (n); \
\
/* If it will wrap around, sync to the end of the ring. */ \
if ((__x + __n) > ATW_NTXDESC) { \
bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
ATW_CDTXOFF(__x), sizeof(struct atw_txdesc) * \
(ATW_NTXDESC - __x), (ops)); \
__n -= (ATW_NTXDESC - __x); \
__x = 0; \
} \
\
/* Now sync whatever is left. */ \
bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
ATW_CDTXOFF(__x), sizeof(struct atw_txdesc) * __n, (ops)); \
} while (0)
#define ATW_CDRXSYNC(sc, x, ops) \
bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
ATW_CDRXOFF((x)), sizeof(struct atw_rxdesc), (ops))
/*
* Note we rely on MCLBYTES being a power of two. Because the `length'
* field is only 11 bits, we must subtract 1 from the length to avoid
* having it truncated to 0!
*
* Apparently we have to set ATW_RXSTAT_SQL to make the ADM8211 tell
* us RSSI.
*/
#define ATW_INIT_RXDESC(sc, x) \
do { \
struct atw_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \
struct atw_rxdesc *__rxd = &sc->sc_rxdescs[(x)]; \
struct mbuf *__m = __rxs->rxs_mbuf; \
\
__m->m_data = __m->m_ext.ext_buf; \
__rxd->ar_buf1 = \
htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \
__rxd->ar_buf2 = /* for descriptor chaining */ \
htole32(ATW_CDRXADDR((sc), ATW_NEXTRX((x)))); \
__rxd->ar_ctl = \
htole32(LSHIFT(((__m->m_ext.ext_size - 1) & ~0x3U), \
ATW_RXCTL_RBS1_MASK) | \
0 /* ATW_RXCTL_RCH */ | \
((x) == (ATW_NRXDESC - 1) ? ATW_RXCTL_RER : 0)); \
__rxd->ar_stat = \
htole32(ATW_RXSTAT_OWN|ATW_RXSTAT_SQL|ATW_RXSTAT_FS| \
ATW_RXSTAT_LS); \
ATW_CDRXSYNC((sc), (x), \
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
} while (0)
/* country codes from ADM8211 SROM */
#define ATW_COUNTRY_FCC 0 /* USA 1-11 */
#define ATW_COUNTRY_IC 1 /* Canada 1-11 */
#define ATW_COUNTRY_ETSI 2 /* European Union (?) 1-13 */
#define ATW_COUNTRY_SPAIN 3 /* 10-11 */
#define ATW_COUNTRY_FRANCE 4 /* 10-13 */
#define ATW_COUNTRY_MKK 5 /* Japan: 14 */
#define ATW_COUNTRY_MKK2 6 /* Japan: 1-14 */
/*
* register space access macros
*/
#define ATW_READ(sc, reg) \
bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
#define ATW_WRITE(sc, reg, val) \
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
#define ATW_SET(sc, reg, mask) \
ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) | (mask))
#define ATW_CLR(sc, reg, mask) \
ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) & ~(mask))
#define ATW_ISSET(sc, reg, mask) \
(ATW_READ((sc), (reg)) & (mask))
void atw_attach __P((struct atw_softc *));
int atw_detach __P((struct atw_softc *));
int atw_activate __P((struct device *, enum devact));
int atw_intr __P((void *arg));
void atw_power __P((int, void *));
void atw_shutdown __P((void *));
#endif /* _DEV_IC_ATWVAR_H_ */

289
sys/dev/pci/if_atw_pci.c Normal file
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@ -0,0 +1,289 @@
/* $NetBSD: if_atw_pci.c,v 1.1 2003/07/06 22:58:10 dyoung Exp $ */
/*-
* Copyright (c) 1998, 1999, 2000, 2002 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
* NASA Ames Research Center; Charles M. Hannum; and David Young.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* PCI bus front-end for the ADMtek ADM8211 802.11 MAC/BBP chip.
*
* Derived from the ``Tulip'' PCI bus front-end.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: if_atw_pci.c,v 1.1 2003/07/06 22:58:10 dyoung Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/mbuf.h>
#include <sys/malloc.h>
#include <sys/kernel.h>
#include <sys/socket.h>
#include <sys/ioctl.h>
#include <sys/errno.h>
#include <sys/device.h>
#include <machine/endian.h>
#include <net/if.h>
#include <net/if_dl.h>
#include <net/if_media.h>
#include <net/if_ether.h>
#include <net/if_ieee80211.h>
#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/ic/atwreg.h>
#include <dev/ic/atwvar.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcidevs.h>
/*
* PCI configuration space registers used by the ADM8211.
*/
#define ATW_PCI_IOBA 0x10 /* i/o mapped base */
#define ATW_PCI_MMBA 0x14 /* memory mapped base */
struct atw_pci_softc {
struct atw_softc sc_atw; /* real ADM8211 softc */
/* PCI-specific goo. */
void *sc_ih; /* interrupt handle */
pci_chipset_tag_t sc_pc; /* our PCI chipset */
pcitag_t sc_pcitag; /* our PCI tag */
};
int atw_pci_match __P((struct device *, struct cfdata *, void *));
void atw_pci_attach __P((struct device *, struct device *, void *));
CFATTACH_DECL(atw_pci, sizeof(struct atw_pci_softc),
atw_pci_match, atw_pci_attach, NULL, NULL);
const struct atw_pci_product {
u_int32_t app_vendor; /* PCI vendor ID */
u_int32_t app_product; /* PCI product ID */
const char *app_product_name;
} atw_pci_products[] = {
{ PCI_VENDOR_ADMTEK, PCI_PRODUCT_ADMTEK_ADM8211,
"ADMtek ADM8211 802.11 MAC/BBP" },
{ 0, 0, NULL },
};
const struct atw_pci_product *atw_pci_lookup
__P((const struct pci_attach_args *));
const struct atw_pci_product *
atw_pci_lookup(pa)
const struct pci_attach_args *pa;
{
const struct atw_pci_product *app;
for (app = atw_pci_products;
app->app_product_name != NULL;
app++) {
if (PCI_VENDOR(pa->pa_id) == app->app_vendor &&
PCI_PRODUCT(pa->pa_id) == app->app_product)
return (app);
}
return (NULL);
}
int
atw_pci_match(parent, match, aux)
struct device *parent;
struct cfdata *match;
void *aux;
{
struct pci_attach_args *pa = aux;
if (atw_pci_lookup(pa) != NULL)
return (1); /* beat if_de.c */
return (0);
}
void
atw_pci_attach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct atw_pci_softc *psc = (void *) self;
struct atw_softc *sc = &psc->sc_atw;
struct pci_attach_args *pa = aux;
pci_chipset_tag_t pc = pa->pa_pc;
pci_intr_handle_t ih;
const char *intrstr = NULL;
bus_space_tag_t iot, memt;
bus_space_handle_t ioh, memh;
int ioh_valid, memh_valid;
const struct atw_pci_product *app;
pcireg_t reg;
int pmreg, rev;
psc->sc_pc = pa->pa_pc;
psc->sc_pcitag = pa->pa_tag;
app = atw_pci_lookup(pa);
if (app == NULL) {
printf("\n");
panic("atw_pci_attach: impossible");
}
/*
* No power management hooks.
* XXX Maybe we should add some!
*/
sc->sc_flags |= ATWF_ENABLED;
/*
* Get revision info, and set some chip-specific variables.
*/
rev = PCI_REVISION(pa->pa_class);
printf(": %s, pass %d.%d\n", app->app_product_name,
(rev >> 4) & 0xf, rev & 0xf);
/*
* Check to see if the device is in power-save mode, and
* being it out if necessary.
*
* XXX This code comes almost verbatim from if_tlp_pci.c. I do
* not understand it. Tulip clears the "sleep mode" bit in the
* CFDA register, first. There is an equivalent (?) register at the
* same place in the ADM8211, but the docs do not assign its bits
* any meanings. -dcy
*/
if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) {
reg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR);
switch (reg & PCI_PMCSR_STATE_MASK) {
case PCI_PMCSR_STATE_D1:
case PCI_PMCSR_STATE_D2:
printf(": waking up from power state D%d\n%s",
reg & PCI_PMCSR_STATE_MASK, sc->sc_dev.dv_xname);
pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR,
(reg & ~PCI_PMCSR_STATE_MASK) |
PCI_PMCSR_STATE_D0);
break;
case PCI_PMCSR_STATE_D3:
/*
* The card has lost all configuration data in
* this state, so punt.
*/
printf(": unable to wake up from power state D3, "
"reboot required.\n");
pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR,
(reg & ~PCI_PMCSR_STATE_MASK) |
PCI_PMCSR_STATE_D0);
return;
}
}
/*
* Map the device.
*/
ioh_valid = (pci_mapreg_map(pa, ATW_PCI_IOBA,
PCI_MAPREG_TYPE_IO, 0,
&iot, &ioh, NULL, NULL) == 0);
memh_valid = (pci_mapreg_map(pa, ATW_PCI_MMBA,
PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
&memt, &memh, NULL, NULL) == 0);
if (memh_valid) {
sc->sc_st = memt;
sc->sc_sh = memh;
} else if (ioh_valid) {
sc->sc_st = iot;
sc->sc_sh = ioh;
} else {
printf(": unable to map device registers\n");
return;
}
sc->sc_dmat = pa->pa_dmat;
/*
* Make sure bus mastering is enabled.
*/
pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) |
PCI_COMMAND_MASTER_ENABLE);
/*
* Get the cacheline size.
*/
sc->sc_cacheline = PCI_CACHELINE(pci_conf_read(pc, pa->pa_tag,
PCI_BHLC_REG));
/*
* Get PCI data moving command info.
*/
if (pa->pa_flags & PCI_FLAGS_MRL_OKAY) /* read line */
sc->sc_flags |= ATWF_MRL;
if (pa->pa_flags & PCI_FLAGS_MRM_OKAY) /* read multiple */
sc->sc_flags |= ATWF_MRM;
if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) /* write invalidate */
sc->sc_flags |= ATWF_MWI;
/*
* Map and establish our interrupt.
*/
if (pci_intr_map(pa, &ih)) {
printf("%s: unable to map interrupt\n",
sc->sc_dev.dv_xname);
return;
}
intrstr = pci_intr_string(pc, ih);
psc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, atw_intr, sc);
if (psc->sc_ih == NULL) {
printf("%s: unable to establish interrupt",
sc->sc_dev.dv_xname);
if (intrstr != NULL)
printf(" at %s", intrstr);
printf("\n");
return;
}
printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
/*
* Finish off the attach.
*/
atw_attach(sc);
}