Added UPA_MID definitions and macros(similar to FreeBSD).
Added membar_store, membar_load macros. No need to set %asi _after_ alternate space use in corresponding functions. Enable(unifdef) casa functions for __arch64__.
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petrov
parent
d93fc4c14e
commit
a021a66c36
@ -1,4 +1,4 @@
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/* $NetBSD: ctlreg.h,v 1.35 2004/07/01 14:57:46 heas Exp $ */
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/* $NetBSD: ctlreg.h,v 1.36 2004/07/01 22:59:16 petrov Exp $ */
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/*
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* Copyright (c) 1996-2002 Eduardo Horvath
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@ -189,8 +189,23 @@
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*/
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/* Get the CPU's UPAID */
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#define UPA_CR_MID(x) (((x)>>17)&0x1f)
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#define UPA_CR_MID_SHIFT (17)
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#define UPA_CR_MID_SIZE (5)
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#define UPA_CR_MID_MASK \
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(((1 << UPA_CR_MID_SIZE) - 1) << UPA_CR_MID_SHIFT)
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#define UPA_CR_MID(x) (((x)>>UPA_CR_MID_SHIFT)&((1 << UPA_CR_MID_SIZE) - 1))
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#ifdef _LOCORE
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#define UPA_GET_MID(r1) \
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ldxa [%g0] ASI_MID_REG, r1 ; \
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srlx r1, UPA_CR_MID_SHIFT, r1 ; \
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and r1, (1 << UPA_CR_MID_SIZE) - 1, r1
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#else
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#define CPU_UPAID UPA_CR_MID(ldxa(0, ASI_MID_REG))
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#endif
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/*
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* [4u] MMU and Cache Control Register (MCCR)
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@ -460,9 +475,8 @@ lduba(paddr_t loc, int asi)
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register unsigned int _lduba_v;
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__asm __volatile(
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"wr %2,%%g0,%%asi; "
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"lduba [%1]%%asi,%0; "
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"wr %%g0, 0x82, %%asi"
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"wr %2, %%g0, %%asi; "
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"lduba [%1]%%asi, %0 "
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: "=r" (_lduba_v)
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: "r" ((unsigned long)(loc)), "r" (asi));
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return (_lduba_v);
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@ -510,9 +524,8 @@ lduha(paddr_t loc, int asi)
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register unsigned int _lduha_v;
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__asm __volatile(
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"wr %2,%%g0,%%asi; "
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"lduha [%1]%%asi,%0; "
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"wr %%g0, 0x82, %%asi "
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"wr %2, %%g0, %%asi; "
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"lduha [%1]%%asi, %0 "
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: "=r" (_lduha_v)
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: "r" ((unsigned long)(loc)), "r" (asi));
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return (_lduha_v);
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@ -578,7 +591,6 @@ ldswa(paddr_t loc, int asi)
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__asm __volatile(
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"wr %2,%%g0,%%asi; "
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"ldswa [%1]%%asi,%0; "
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"wr %%g0, 0x82, %%asi "
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: "=r" (_lda_v)
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: "r" ((unsigned long)(loc)), "r" (asi));
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return (_lda_v);
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@ -662,8 +674,7 @@ ldda(paddr_t loc, int asi)
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__asm __volatile(
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"wr %2,%%g0,%%asi; "
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"ldda [%1]%%asi,%0; "
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"wr %%g0, 0x82, %%asi "
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"ldda [%1]%%asi,%0 "
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: "=r" (_lda_v)
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: "r" ((unsigned long)(loc)), "r" (asi));
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return (_lda_v);
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@ -714,8 +725,7 @@ ldxa(paddr_t loc, int asi)
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__asm __volatile(
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"wr %2,%%g0,%%asi; "
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"ldxa [%1]%%asi,%0; "
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"wr %%g0, 0x82, %%asi "
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"ldxa [%1]%%asi,%0 "
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: "=r" (_lda_v)
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: "r" ((unsigned long)(loc)), "r" (asi));
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return (_lda_v);
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@ -767,8 +777,7 @@ stba(paddr_t loc, int asi, u_char value)
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{
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__asm __volatile(
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"wr %2, %%g0, %%asi; "
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"stba %0, [%1]%%asi; "
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"wr %%g0, 0x82, %%asi "
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"stba %0, [%1]%%asi "
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: : "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (asi));
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}
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#else
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@ -811,8 +820,7 @@ stha(paddr_t loc, int asi, u_short value)
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{
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__asm __volatile(
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"wr %2,%%g0,%%asi; "
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"stha %0,[%1]%%asi; "
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"wr %%g0, 0x82, %%asi "
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"stha %0,[%1]%%asi "
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: : "r" ((int)(value)), "r" ((unsigned long)(loc)),
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"r" (asi) : "memory");
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}
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@ -859,8 +867,7 @@ sta(paddr_t loc, int asi, u_int value)
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{
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__asm __volatile(
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"wr %2,%%g0,%%asi; "
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"sta %0,[%1]%%asi; "
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"wr %%g0, 0x82, %%asi "
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"sta %0,[%1]%%asi "
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: : "r" ((int)(value)), "r" ((unsigned long)(loc)),
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"r" (asi) : "memory");
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}
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@ -906,8 +913,7 @@ stda(paddr_t loc, int asi, u_int64_t value)
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{
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__asm __volatile(
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"wr %2,%%g0,%%asi; "
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"stda %0,[%1]%%asi; "
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"wr %%g0, 0x82, %%asi "
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"stda %0,[%1]%%asi "
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: : "r" ((long long)(value)), "r" ((unsigned long)(loc)), "r" (asi)
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: "memory");
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}
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@ -955,8 +961,7 @@ stxa(paddr_t loc, int asi, u_int64_t value)
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{
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__asm __volatile(
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"wr %2,%%g0,%%asi; "
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"stxa %0,[%1]%%asi; "
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"wr %%g0, 0x82, %%asi "
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"stxa %0,[%1]%%asi "
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: : "r" ((unsigned long)(value)),
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"r" ((unsigned long)(loc)), "r" (asi)
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: "memory");
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@ -1006,22 +1011,33 @@ stxa(paddr_t loc, int asi, u_int64_t value)
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}
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#endif
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#if 0
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#ifdef __arch64__
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/* native store 32-bit int to alternate address space w/64-bit compiler*/
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static __inline__ u_int32_t
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casa(paddr_t loc, int asi, u_int32_t value, u_int32_t oldvalue)
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{
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__asm __volatile(
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"wr %3,%%g0,%%asi; "
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"casa [%1]%%asi,%2,%0 "
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: "+r" (value)
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: "r" ((unsigned long)(loc)), "r" (oldvalue), "r" (asi)
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: "memory");
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return (value);
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}
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/* native store 64-bit int to alternate address space w/64-bit compiler*/
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static __inline__ u_int64_t
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casxa(paddr_t loc, int asi, u_int64_t value, u_int64_t oldvalue)
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{
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__asm __volatile(
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"wr %3,%%g0,%%asi; "
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"casxa [%1]%%asi,%2,%0; "
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"wr %%g0, 0x82, %%asi "
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"casxa [%1]%%asi,%2,%0 "
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: "+r" (value)
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: "r" ((unsigned long)(loc)), "r" (oldvalue), "r" (asi)
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: "memory");
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return (value);
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}
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#else
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#if 0
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/* native store 64-bit int to alternate address space w/32-bit compiler*/
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static __inline__ u_int64_t
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casxa(paddr_t loc, int asi, u_int64_t value, u_int64_t oldvalue)
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@ -1082,7 +1098,7 @@ casxa(paddr_t loc, int asi, u_int64_t value, u_int64_t oldvalue)
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return (((u_int64_t)_casxa_hi<<32)|(u_int64_t)_casxa_lo);
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}
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#endif
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#endif /* 0 */
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#endif
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/* flush address from data cache */
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#define flush(loc) ({ \
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@ -1128,6 +1144,9 @@ casxa(paddr_t loc, int asi, u_int64_t value, u_int64_t oldvalue)
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/* Complete all outstanding stores before any new loads */
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#define membar_lookaside() __asm __volatile("membar #Lookaside" : :)
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#define membar_load() __asm __volatile("membar #LoadLoad | #LoadStore" : :)
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#define membar_store() __asm __volatile("membar #LoadStore | #StoreStore" : :)
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#ifdef __arch64__
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/* read 64-bit %tick register */
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#define tick() ({ \
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