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This commit is contained in:
nia 2022-05-04 06:45:53 +00:00
parent 71673aa608
commit a0036ffd0a
2 changed files with 6589 additions and 6486 deletions
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39
sys/dev/pci/pcidevs.h
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@ -1,10 +1,10 @@
/* $NetBSD: pcidevs.h,v 1.1437 2022/04/27 06:58:17 msaitoh Exp $ */
/* $NetBSD: pcidevs.h,v 1.1438 2022/05/04 06:45:53 nia Exp $ */
/*
* THIS FILE IS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
* NetBSD: pcidevs,v 1.1454 2022/04/27 06:57:48 msaitoh Exp
* NetBSD: pcidevs,v 1.1455 2022/05/04 06:42:43 nia Exp
*/
/*
@ -4565,9 +4565,40 @@
#define PCI_PRODUCT_INTEL_C2000_DUMMYGBE 0x1f42 /* C2000 Ethernet(Dummy function) */
#define PCI_PRODUCT_INTEL_C2000_25GBE 0x1f45 /* C2000 Ethernet(2.5Gbe) */
#define PCI_PRODUCT_INTEL_XEONSC_UBOX_0 0x2014 /* Xeon Scalable Ubox */
#define PCI_PRODUCT_INTEL_XEONSC_UBOX_1 0x2016 /* Xeon Scalable Ubox */
#define PCI_PRODUCT_INTEL_XEONSC_UBOX_1 0x2015 /* Xeon Scalable Ubox */
#define PCI_PRODUCT_INTEL_XEONSC_UBOX_2 0x2016 /* Xeon Scalable Ubox */
#define PCI_PRODUCT_INTEL_XEONSC_M2PCIR 0x2018 /* Xeon Scalable M2PCI */
#define PCI_PRODUCT_INTEL_XEONSC_CBDMAR 0x2021 /* Xeon Scalable CBDMA */
#define PCI_PRODUCT_INTEL_XEONSC_MMVTD 0x2024 /* Xeon Scalable MM/Vt-d */
#define PCI_PRODUCT_INTEL_XEONSC_RAS 0x2025 /* Xeon Scalable RAS */
#define PCI_PRODUCT_INTEL_XEONSC_IOAPIC 0x2026 /* Xeon Scalable I/O APIC */
#define PCI_PRODUCT_INTEL_XEONSC_VTD 0x2034 /* Xeon Scalable VT-d */
#define PCI_PRODUCT_INTEL_XEONSC_RAS 0x2035 /* Xeon Scalable RAS */
#define PCI_PRODUCT_INTEL_XEONSC_IOAPIC_C 0x2036 /* Xeon Scalable IOxAPIC */
#define PCI_PRODUCT_INTEL_XEONSC_IMC_1 0x2041 /* Xeon Scalable IMC */
#define PCI_PRODUCT_INTEL_XEONSC_IMC_2 0x2042 /* Xeon Scalable IMC */
#define PCI_PRODUCT_INTEL_XEONSC_IMC_3 0x2043 /* Xeon Scalable IMC */
#define PCI_PRODUCT_INTEL_XEONSC_IMC_4 0x2044 /* Xeon Scalable IMC */
#define PCI_PRODUCT_INTEL_XEONSC_LMC_1 0x2045 /* Xeon Scalable LM */
#define PCI_PRODUCT_INTEL_XEONSC_LMSC_1 0x2046 /* Xeon Scalable LMS */
#define PCI_PRODUCT_INTEL_XEONSC_LMDPC_1 0x2047 /* Xeon Scalable LMDP */
#define PCI_PRODUCT_INTEL_XEONSC_DECSC_1 0x2048 /* Xeon Scalable DECS */
#define PCI_PRODUCT_INTEL_XEONSC_LMC_2 0x2049 /* Xeon Scalable LM */
#define PCI_PRODUCT_INTEL_XEONSC_LMSC_2 0x204a /* Xeon Scalable LMS */
#define PCI_PRODUCT_INTEL_XEONSC_LMDPC_2 0x204b /* Xeon Scalable LMDP */
#define PCI_PRODUCT_INTEL_XEONSC_M3KTI_1 0x204c /* Xeon Scalable M3KTI */
#define PCI_PRODUCT_INTEL_XEONSC_M3KTI_2 0x204d /* Xeon Scalable M3KTI */
#define PCI_PRODUCT_INTEL_XEONSC_CHA_1 0x2054 /* Xeon Scalable CHA */
#define PCI_PRODUCT_INTEL_XEONSC_CHA_2 0x2055 /* Xeon Scalable CHA */
#define PCI_PRODUCT_INTEL_XEONSC_CHA_3 0x2056 /* Xeon Scalable CHA */
#define PCI_PRODUCT_INTEL_XEONSC_CHA_4 0x2057 /* Xeon Scalable CHA */
#define PCI_PRODUCT_INTEL_XEONSC_KTI 0x2058 /* Xeon Scalable KTI */
#define PCI_PRODUCT_INTEL_XEONSC_UPIR 0x2059 /* Xeon Scalable UPI */
#define PCI_PRODUCT_INTEL_XEONSC_PCU_0 0x2080 /* Xeon Scalable PCU */
#define PCI_PRODUCT_INTEL_XEONSC_PCU_1 0x2082 /* Xeon Scalable PCU */
#define PCI_PRODUCT_INTEL_XEONSC_PCU_1 0x2081 /* Xeon Scalable PCU */
#define PCI_PRODUCT_INTEL_XEONSC_PCU_2 0x2082 /* Xeon Scalable PCU */
#define PCI_PRODUCT_INTEL_XEONSC_CHA_5 0x208d /* Xeon Scalable CHA */
#define PCI_PRODUCT_INTEL_XEONSC_CHA_6 0x208e /* Xeon Scalable CHA */
#define PCI_PRODUCT_INTEL_BSW_HB 0x2280 /* Braswell Soc Transaction Router */
#define PCI_PRODUCT_INTEL_BSW_HDA 0x2284 /* Braswell HD Audio */
#define PCI_PRODUCT_INTEL_BSW_SIO_DMA_2 0x2286 /* Braswell SIO DMA */

13036
sys/dev/pci/pcidevs_data.h
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