Aren
/
NetBSD
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

__EXCEPTION_ENTRY - "tst" already does logical AND, so shave off extra 

"mov" and "and" and just test PSL_MD bit directly.

While here - shuffle around instructions to construct PSL_MD to break
dependencies.

While still here - only interrupt vector uses SSR and SPC as function
args, so don't bother saving them here in r4 and r5.  Other vectors
don't need them and interrupt vector can just as well "stc" them
directly before exceptions are enabled.
This commit is contained in:
uwe 2011-02-04 03:23:33 +00:00
parent 90a7a07b86
commit 9ed9e8742f
2 changed files with 17 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
sys/arch/sh3/include/locore.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.h,v 1.20 2011/01/18 00:26:57 joerg Exp $ */
/* $NetBSD: locore.h,v 1.21 2011/02/04 03:23:33 uwe Exp $ */
/*-
* Copyright (c) 2002 The NetBSD Foundation, Inc.
@ -68,26 +68,24 @@
* + save all registers to trapframe.
* + setup kernel stack.
* + change bank from 1 to 0
* + set BANK0 (r4, r5, r6) = (ssr, spc, ssp)
* + NB: interrupt vector "knows" that r0_bank1 = ssp
*/
#define __EXCEPTION_ENTRY ;\
/* Check kernel/user mode. */ ;\
mov #0x40, r3 ;\
stc ssr, r2 /* r2 = SSR */ ;\
swap.b r3, r3 ;\
stc ssr, r2 ;\
swap.w r3, r3 /* r3 = 0x40000000 */ ;\
mov r2, r0 /* r2 = r0 = SSR */ ;\
and r3, r0 ;\
tst r0, r0 /* if (SSR.MD == 0) T = 1 */ ;\
mov r14, r1 ;\
mov r6, r14 /* frame pointer */ ;\
swap.w r3, r3 /* r3 = PSL_MD */ ;\
mov r6, r14 /* trapframe pointer */ ;\
tst r3, r2 /* if (SSR.MD == 0) T = 1 */ ;\
mov.l r1, @-r14 /* save tf_r14 */ ;\
bf/s 1f /* T==0 ...Exception from kernel mode */;\
mov r15, r0 ;\
/* Exception from user mode */ ;\
mov r7, r15 /* change to kernel stack */ ;\
1: ;\
/* Save registers */ ;\
mov.l r1, @-r14 /* tf_r14 */ ;\
/* Save remaining registers */ ;\
mov.l r0, @-r14 /* tf_r15 */ ;\
stc.l r0_bank,@-r14 /* tf_r0 */ ;\
stc.l r1_bank,@-r14 /* tf_r1 */ ;\
@ -112,14 +110,12 @@
add #-8, r14 /* skip tf_ubc, tf_expevt */ ;\
mov r14, r6 /* store frame pointer */ ;\
/* Change register bank to 0 */ ;\
shlr r3 /* r3 = 0x20000000 */ ;\
shlr r3 /* r3 = PSL_RB */ ;\
stc sr, r1 /* r1 = SR */ ;\
not r3, r3 ;\
and r1, r3 ;\
ldc r3, sr /* SR.RB = 0 */ ;\
/* Set up arguments. r4 = ssr, r5 = spc */ ;\
stc r2_bank,r4 ;\
stc spc, r5
ldc r3, sr /* SR.RB = 0 */
/*
* __EXCEPTION_RETURN:

9
sys/arch/sh3/sh3/exception_vector.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: exception_vector.S,v 1.47 2011/01/28 21:06:08 uwe Exp $ */
/* $NetBSD: exception_vector.S,v 1.48 2011/02/04 03:23:33 uwe Exp $ */
/*-
* Copyright (c) 2002 The NetBSD Foundation, Inc.
@ -48,7 +48,7 @@
#define _ALIGN_TEXT .align 5
#include <sh3/asm.h>
__KERNEL_RCSID(0, "$NetBSD: exception_vector.S,v 1.47 2011/01/28 21:06:08 uwe Exp $")
__KERNEL_RCSID(0, "$NetBSD: exception_vector.S,v 1.48 2011/02/04 03:23:33 uwe Exp $")
/*
@ -458,7 +458,10 @@ VECTOR_END_MARKER(sh4_vector_tlbmiss_end)
*/
NENTRY(sh_vector_interrupt)
__EXCEPTION_ENTRY
stc r0_bank, r6 ! ssp - 3rd arg to intc_intr()
!! arguments for intc_intr(): for struct clockframe
stc ssr, r4
stc spc, r5
stc r0_bank, r6 ! ssp
__INTR_MASK(r0, r1)
__EXCEPTION_UNBLOCK(r0, r1) ! enable exceptions for P3 access