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ienab_bi[cs] are never used in a context common to both sun4/4c and sun4m, 

so there's no point in constructing common entry points for them in locore.s.
This commit is contained in:
pk 2002-12-06 17:45:39 +00:00
parent 699eeb228c
commit 9ebe0ee7a6
4 changed files with 20 additions and 52 deletions
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6
sys/arch/sparc/sparc/autoconf.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: autoconf.c,v 1.183 2002/11/29 08:02:05 pk Exp $ */
/* $NetBSD: autoconf.c,v 1.184 2002/12/06 17:45:39 pk Exp $ */
/*
* Copyright (c) 1996
@ -402,7 +402,7 @@ bootstrap4m()
setpte4m(SI_INTR_VA, pte);
/* Now disable interrupts */
ienab_bis(SINTR_MA);
icr_si_bis(SINTR_MA);
/* Send all interrupts to primary processor */
*((u_int *)ICR_ITR) = 0;
@ -952,7 +952,7 @@ cpu_configure()
#if defined(SUN4M)
#if !defined(MSIIEP)
if (CPU_ISSUN4M)
ienab_bic(SINTR_MA);
icr_si_bic(SINTR_MA);
#else
if (CPU_ISSUN4M)
/* nothing for ms-IIep so far */;

13
sys/arch/sparc/sparc/intreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: intreg.h,v 1.9 1998/10/26 08:12:15 pk Exp $ */
/* $NetBSD: intreg.h,v 1.10 2002/12/06 17:45:39 pk Exp $ */
/*
* Copyright (c) 1992, 1993
@ -150,3 +150,14 @@ struct icr_pi {
"f\0\7VME\0f\7\7SBUS\0b\16K\0b\17S\0b\20E\0" \
"b\21A\0b\22SC\0b\23T\0b\24VI\0b\25MI\0" \
"b\26F\0b\33V\0b\34M\0b\35I\0b\36ME\0b\37MA\0"
/*
* Set & clear bits in the system interrupt register
*/
#define icr_si_bis(bis) do { \
*((u_int32_t *)ICR_SI_SET) = (bis); \
} while (0)
#define icr_si_bic(bic) do { \
*((u_int32_t *)ICR_SI_CLR) = (bic); \
} while (0)

49
sys/arch/sparc/sparc/locore.s
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.s,v 1.166 2002/12/06 16:04:12 pk Exp $ */
/* $NetBSD: locore.s,v 1.167 2002/12/06 17:45:39 pk Exp $ */
/*
* Copyright (c) 1996 Paul Kranenburg
@ -4022,8 +4022,6 @@ Lgandul: nop
MUNGE(NOP_ON_4M_10)
MUNGE(NOP_ON_4M_11)
MUNGE(NOP_ON_4M_12)
MUNGE(NOP_ON_4M_13)
MUNGE(NOP_ON_4M_14)
MUNGE(NOP_ON_4M_15)
b,a 2f
@ -5969,31 +5967,15 @@ ENTRY(loadfpstate)
* ienab_bis(bis) int bis;
* ienab_bic(bic) int bic;
*
* Set and clear bits in the interrupt register.
* Set and clear bits in the sun4/sun4c interrupt register.
*/
#if defined(SUN4M) && (defined(SUN4) || defined(SUN4C))
ENTRY(ienab_bis)
NOP_ON_4M_13:
b,a _C_LABEL(ienab_bis_4_4c)
b,a _C_LABEL(ienab_bis_4m)
ENTRY(ienab_bic)
NOP_ON_4M_14:
b,a _C_LABEL(ienab_bic_4_4c)
b,a _C_LABEL(ienab_bic_4m)
#endif
#if defined(SUN4) || defined(SUN4C)
/*
* Since there are no read-modify-write instructions for this,
* and one of the interrupts is nonmaskable, we must disable traps.
*/
#if defined(SUN4M)
ENTRY(ienab_bis_4_4c)
#else
ENTRY(ienab_bis)
#endif
! %o0 = bits to set
rd %psr, %o2
wr %o2, PSR_ET, %psr ! disable traps
@ -6007,11 +5989,7 @@ ENTRY(ienab_bis)
retl
nop
#if defined(SUN4M)
ENTRY(ienab_bic_4_4c)
#else
ENTRY(ienab_bic)
#endif
! %o0 = bits to clear
rd %psr, %o2
wr %o2, PSR_ET, %psr ! disable traps
@ -6024,30 +6002,9 @@ ENTRY(ienab_bic)
nop
retl
nop
#endif
#endif /* SUN4 || SUN4C */
#if defined(SUN4M)
/*
* sun4m has separate registers for clearing/setting the interrupt mask.
*/
#if defined(SUN4) || defined(SUN4C)
ENTRY(ienab_bis_4m)
#else
ENTRY(ienab_bis)
#endif
set ICR_SI_SET, %o1
retl
st %o0, [%o1]
#if defined(SUN4) || defined(SUN4C)
ENTRY(ienab_bic_4m)
#else
ENTRY(ienab_bic)
#endif
set ICR_SI_CLR, %o1
retl
st %o0, [%o1]
/*
* raise(cpu, level)
*/

4
sys/arch/sparc/sparc/timer_sun4m.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: timer_sun4m.c,v 1.1 2002/08/25 16:10:35 thorpej Exp $ */
/* $NetBSD: timer_sun4m.c,v 1.2 2002/12/06 17:45:40 pk Exp $ */
/*
* Copyright (c) 1992, 1993
@ -93,7 +93,7 @@ timer_init_4m(void)
continue;
cpi->counterreg_4m->t_limit = tmr_ustolim4m(statint);
}
ienab_bic(SINTR_T);
icr_si_bic(SINTR_T);
}
/*