Fixed multiple miscellaneous bugs. Fixed the case of some instruction
operands. Added support for dissassembly of more of the instruction set.
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mark
parent
aeec9c8ac1
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9e18e78df6
@ -1,4 +1,4 @@
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/* $NetBSD: db_disasm.c,v 1.1 1996/02/15 22:37:13 mark Exp $ */
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/* $NetBSD: db_disasm.c,v 1.2 1996/03/06 22:46:37 mark Exp $ */
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/*
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* Copyright (c) 1996 Mark Brinicombe.
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@ -45,15 +45,50 @@
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* Paul Kranenburg
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*
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* This code is not complete. Not all instructions are disassembled.
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* Current LDR, STR, LDF, STF, CDT and MSRF are not supported.
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*
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* $Id: db_disasm.c,v 1.1 1996/02/15 22:37:13 mark Exp $
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* Current LDF, STF, CDT and MSRF are not supported.
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*/
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#include <sys/param.h>
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#include <machine/db_machdep.h>
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#include <ddb/db_sym.h>
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/*
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* General instruction format
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*
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* insn[cc][mod] [operands]
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*
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* Those fields with an uppercase format code indicate that the field follows
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* directly after the instruction before the separator i.e. they modify the instruction
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* rather than just being an operand to the instruction. The only exception is the
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* writeback flag which follows a operand.
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*
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*
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* 2 - print Operand 2 of a data processing instrcution
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* d - destination register (bits 12-15)
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* n - n register (bits 16-19)
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* s - s register (bits 8-11)
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* o - indirect register rn (bits 16-19) (used by swap)
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* m - m register (bits 0-4)
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* a - address operand of ldr/str instruction
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* l - register list for ldm/stm instruction
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* f - 1st fp operand (register) (bits 12-14)
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* g - 2nd fp operand (register) (bits 16-18)
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* h - 3rd fp operand (register/immediate) (bits 0-4)
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* b - branch address
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* X - block transfer type
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* c - comment field bits(0-23)
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* p - saved or current status register
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* B - byte transfer flag
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* S - set status flag
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* T - user mode transfer
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* P - fp precision
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* R - fp rounding
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* w - writeback flag
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* # - co-processor number
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* y - co-processor data processing registers
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* z - co-processor data transfer registers
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*/
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struct arm32_insn {
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u_int mask;
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u_int pattern;
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@ -67,32 +102,32 @@ struct arm32_insn arm32_i[] = {
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{ 0x0f000000, 0x0b000000, "bl", "b" },
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{ 0x0fe000f0, 0x00000090, "mul", "Sdms" },
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{ 0x0fe000f0, 0x00200090, "mla", "Sdmsn" },
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{ 0x0e100000, 0x04000000, "str", "BTdaw" },
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{ 0x0e100000, 0x04100000, "ldr", "BTdaw" },
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{ 0x0c100010, 0x04000000, "str", "BTdaw" },
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{ 0x0c100010, 0x04100000, "ldr", "BTdaw" },
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{ 0x0e100000, 0x08000000, "stm", "Xnwl" },
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{ 0x0e100000, 0x08100000, "ldm", "Xnwl" },
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{ 0x0e100000, 0x04000000, "str", "BTdaW" },
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{ 0x0e100000, 0x04100000, "ldr", "BTdaW" },
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{ 0x0c100010, 0x04000000, "str", "BTdaW" },
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{ 0x0c100010, 0x04100000, "ldr", "BTdaW" },
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{ 0x0e100000, 0x08000000, "stm", "XnWl" },
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{ 0x0e100000, 0x08100000, "ldm", "XnWl" },
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{ 0x0fb00ff0, 0x01000090, "swap", "Bdmo" },
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{ 0x0fbf0fff, 0x010f0000, "mrs", "dp" },
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{ 0x0dbffff0, 0x0129f000, "msr", "pm" },
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{ 0x0dbffff0, 0x0128f000, "msrf", "pm" },
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{ 0x0de00000, 0x00000000, "and" "Sdn2" },
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{ 0x0de00000, 0x00200000, "eor" "Sdn2" },
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{ 0x0de00000, 0x00400000, "sub" "Sdn2" },
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{ 0x0de00000, 0x00600000, "rsb" "Sdn2" },
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{ 0x0de00000, 0x00800000, "add" "Sdn2" },
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{ 0x0de00000, 0x00a00000, "adc" "Sdn2" },
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{ 0x0de00000, 0x00c00000, "sbc" "Sdn2" },
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{ 0x0de00000, 0x00e00000, "rsc" "Sdn2" },
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{ 0x0de00000, 0x01000000, "tst" "Sn2" },
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{ 0x0de00000, 0x01200000, "teq" "Sn2" },
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{ 0x0de00000, 0x01400000, "cmp" "Sn2" },
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{ 0x0de00000, 0x01600000, "cmn" "Sn2" },
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{ 0x0de00000, 0x01800000, "orr" "Sdn2" },
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{ 0x0de00000, 0x01a00000, "mov" "Sd2" },
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{ 0x0de00000, 0x01c00000, "bic" "Sdn2" },
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{ 0x0de00000, 0x01e00000, "mvn" "Sd2" },
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{ 0x0de00000, 0x00000000, "and", "Sdn2" },
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{ 0x0de00000, 0x00200000, "eor", "Sdn2" },
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{ 0x0de00000, 0x00400000, "sub", "Sdn2" },
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{ 0x0de00000, 0x00600000, "rsb", "Sdn2" },
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{ 0x0de00000, 0x00800000, "add", "Sdn2" },
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{ 0x0de00000, 0x00a00000, "adc", "Sdn2" },
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{ 0x0de00000, 0x00c00000, "sbc", "Sdn2" },
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{ 0x0de00000, 0x00e00000, "rsc", "Sdn2" },
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{ 0x0de00000, 0x01000000, "tst", "Sn2" },
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{ 0x0de00000, 0x01200000, "teq", "Sn2" },
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{ 0x0de00000, 0x01400000, "cmp", "Sn2" },
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{ 0x0de00000, 0x01600000, "cmn", "Sn2" },
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{ 0x0de00000, 0x01800000, "orr", "Sdn2" },
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{ 0x0de00000, 0x01a00000, "mov", "Sd2" },
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{ 0x0de00000, 0x01c00000, "bic", "Sdn2" },
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{ 0x0de00000, 0x01e00000, "mvn", "Sd2" },
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{ 0x0ff08f10, 0x0e000100, "adf", "PRfgh" },
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{ 0x0ff08f10, 0x0e100100, "muf", "PRfgh" },
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{ 0x0ff08f10, 0x0e200100, "suf", "PRfgh" },
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@ -132,57 +167,57 @@ struct arm32_insn arm32_i[] = {
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};
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char *arm32_insn_conditions[] = {
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"EQ",
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"NE",
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"CS",
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"CC",
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"MI",
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"PL",
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"VS",
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"VC",
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"HI",
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"LS",
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"GE",
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"LT",
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"GT",
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"LE",
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"eq",
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"ne",
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"cs",
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"cc",
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"mi",
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"pl",
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"vs",
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"vc",
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"hi",
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"ls",
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"ge",
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"lt",
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"gt",
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"le",
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"",
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"NV"
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"nv"
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};
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char *insn_block_transfers[] = {
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"DA",
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"IA",
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"DB",
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"IB"
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"da",
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"ia",
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"db",
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"ib"
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};
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char *insn_stack_block_transfers[] = {
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"FA",
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"EA",
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"FD",
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"FA"
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"fa",
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"ea",
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"fd",
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"fa"
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};
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char *op_shifts[] = {
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"LSL",
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"LSR",
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"ASR",
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"ROR"
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"lsl",
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"lsr",
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"asr",
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"ror"
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};
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char *insn_fpa_rounding[] = {
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"",
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"P",
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"M",
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"Z"
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"p",
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"m",
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"z"
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};
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char *insn_fpa_precision[] = {
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"S",
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"D",
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"E",
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"P"
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"s",
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"d",
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"e",
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"p"
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};
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char *insn_fpaconstants[] = {
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@ -199,10 +234,10 @@ char *insn_fpaconstants[] = {
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#define insn_condition(x) arm32_insn_conditions[(x >> 28) & 0x0f]
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#define insn_blktrans(x) insn_block_transfers[(x >> 23) & 3]
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#define insn_stkblktrans(x) insn_stack_block_transfers[(x >> 23) & 3]
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#define op2_shift(x) op_shifts[(x >> 5) & 3]
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#define insn_fparnd(x) insn_fpa_rounding[(x >> 5) & 0x03]
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#define insn_fpaprec(x) insn_fpa_precision[(((x >> 18) & 2)|(x >> 7)) & 3]
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#define insn_fpaimm(x) insn_fpaconstants[x & 0x07]
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#define op2_shift(x) op_shifts[(x >> 5) & 3]
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#define insn_fparnd(x) insn_fpa_rounding[(x >> 5) & 0x03]
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#define insn_fpaprec(x) insn_fpa_precision[(((x >> 18) & 2)|(x >> 7)) & 3]
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#define insn_fpaimm(x) insn_fpaconstants[x & 0x07]
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void db_register_shift __P((u_int insn));
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void db_print_reglist __P((u_int insn));
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@ -226,7 +261,8 @@ db_disasm(loc, altfmt)
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matchp = 0;
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insn = db_get_value(loc, 4, 0);
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db_printf("loc=%08x insn=%08x : ", loc, insn);
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/* db_printf("loc=%08x insn=%08x : ", loc, insn);*/
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/* db_printf("loc=%08x : ", loc);*/
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while (i_ptr->name) {
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if ((insn & i_ptr->mask) == i_ptr->pattern) {
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@ -252,7 +288,6 @@ db_disasm(loc, altfmt)
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db_printf("#0x%08x", (insn & 0xff) << (((insn >> 7) & 0x1e)));
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} else {
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db_register_shift(insn);
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db_printf("Op2");
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}
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break;
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case 'd':
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@ -303,20 +338,20 @@ db_disasm(loc, altfmt)
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break;
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case 'p':
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if (insn & 0x00400000)
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db_printf("SPSR");
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db_printf("spsr");
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else
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db_printf("CPSR");
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db_printf("cpsr");
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case 'B':
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if (insn & 0x00400000)
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db_printf("B");
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db_printf("b");
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break;
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case 'S':
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if (insn & 0x00100000)
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db_printf("S");
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db_printf("s");
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break;
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case 'T':
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if ((insn & 0x01200000) == 0x00200000)
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db_printf("T");
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db_printf("t");
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break;
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case 'P':
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db_printf("%s", insn_fpaprec(insn));
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@ -324,7 +359,7 @@ db_disasm(loc, altfmt)
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case 'R':
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db_printf("%s", insn_fparnd(insn));
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break;
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case 'w':
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case 'W':
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if (insn & (1 << 21))
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db_printf("!");
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break;
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@ -348,17 +383,18 @@ db_disasm(loc, altfmt)
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db_printf(", %d", (insn >> 5) & 0x07);
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break;
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default:
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db_printf("(UNKNOWN)");
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db_printf("[%02x:c](unknown)", *f_ptr, *f_ptr);
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break;
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}
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++fmt;
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if (*(f_ptr+1) > 'A' && *(f_ptr+1) < 'Z')
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fmt = 0;
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if (*(++f_ptr))
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++f_ptr;
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else if (*(++f_ptr)) {
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if (fmt == 1)
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db_printf("\t");
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else
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db_printf(", ");
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}
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};
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db_printf("\n");
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