IDT32364's Config register uses a different base for IC/DC (instruction

and data cache sizes).   R4000 uses 2^(12+IC) and 2^(12+DC).  IDT32364
uses 2^(9+IC) and 2^(9+DC).

abstract around the problem by making the base a parameter to the
MIPS3_CONFIG_CACHE_SIZE macro.   we pass the base down from mips_vector_init
to mips3_vector_init and to mips3_ConfigCache (where it is used).

XXX: someone with an MIPS3_4100 should switch to this and get rid
of the ugly ifdefs in cpuregs.h

sys/arch/mips/include/cpuregs.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: cpuregs.h,v 1.35 2000/07/17 23:35:13 jeffs Exp $	*/
+/*	$NetBSD: cpuregs.h,v 1.36 2000/09/16 00:04:57 chuck Exp $	*/
 
 /*
  * Copyright (c) 1992, 1993
@@ -291,13 +291,15 @@
 #define MIPS3_CONFIG_DC_SHIFT	6
 #define MIPS3_CONFIG_IC_MASK	0x00000e00	/* Primary I-cache size */
 #define MIPS3_CONFIG_IC_SHIFT	9
+#define MIPS3_CONFIG_C_DEFBASE	0x1000		/* default base 2^12 */
 #ifdef MIPS3_4100				/* VR4100 core */
+/* XXXCDC: THIS MIPS3_4100 SPECIAL CASE SHOULD GO AWAY */
 #define MIPS3_CONFIG_CS		0x00001000	/* cache size mode indication*/
-#define MIPS3_CONFIG_CACHE_SIZE(config, mask, shift) \
+#define MIPS3_CONFIG_CACHE_SIZE(config, mask, dummy, shift) \
 	((((config)&MIPS3_CONFIG_CS)?0x400:0x1000) << (((config) & (mask)) >> (shift)))
 #else
-#define MIPS3_CONFIG_CACHE_SIZE(config, mask, shift) \
+#define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \
-	(0x1000 << (((config) & (mask)) >> (shift)))
+	((base) << (((config) & (mask)) >> (shift)))
 #endif
 
 /* Block ordering: 0: sequential, 1: sub-block */

sys/arch/mips/include/locore.h

@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.41 2000/09/13 01:20:41 chuck Exp $ */
+/* $NetBSD: locore.h,v 1.42 2000/09/16 00:04:57 chuck Exp $ */
 
 /*
  * Copyright 1996 The Board of Trustees of The Leland Stanford
@@ -62,7 +62,7 @@ void	mips1_wbflush(void);
 void	mips1_proc_trampoline(void);
 void	mips1_cpu_switch_resume(void);
 
-void	mips3_ConfigCache(void);
+void	mips3_ConfigCache(int);
 void	mips3_FlushCache(void);
 void	mips3_FlushDCache(vaddr_t addr, vaddr_t len);
 void	mips3_FlushICache(vaddr_t addr, vaddr_t len);

sys/arch/mips/mips/mips_machdep.c

@@ -1,4 +1,4 @@
-/*	$NetBSD: mips_machdep.c,v 1.100 2000/09/13 01:53:01 nisimura Exp $	*/
+/*	$NetBSD: mips_machdep.c,v 1.101 2000/09/16 00:04:57 chuck Exp $	*/
 
 /*-
  * Copyright (c) 1998 The NetBSD Foundation, Inc.
@@ -52,7 +52,7 @@
 
 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
 
-__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.100 2000/09/13 01:53:01 nisimura Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.101 2000/09/16 00:04:57 chuck Exp $");
 
 #include "opt_compat_netbsd.h"
 #include "opt_compat_ultrix.h"
@@ -94,7 +94,7 @@ static void	mips1_vector_init __P((void));
 #endif
 
 #ifdef MIPS3
-static void	mips3_vector_init __P((void));
+static void	mips3_vector_init __P((int));
 #endif
 
 mips_locore_jumpvec_t mips_locore_jumpvec;
@@ -210,18 +210,19 @@ mips_locore_jumpvec_t mips3_locore_vec =
  *----------------------------------------------------------------------------
  */
 void
-mips3_ConfigCache()
+mips3_ConfigCache(mips3_csizebase)
+	int mips3_csizebase;
 {
 	u_int32_t config = mips3_read_config();
 	static int snoop_check = 0;
 	int i;
 
 	mips_L1ICacheSize = MIPS3_CONFIG_CACHE_SIZE(config,
-	    MIPS3_CONFIG_IC_MASK, MIPS3_CONFIG_IC_SHIFT);
+	    MIPS3_CONFIG_IC_MASK, mips3_csizebase, MIPS3_CONFIG_IC_SHIFT);
 	mips_L1ICacheLSize = MIPS3_CONFIG_CACHE_L1_LSIZE(config,
 	    MIPS3_CONFIG_IB);
 	mips_L1DCacheSize = MIPS3_CONFIG_CACHE_SIZE(config,
-	    MIPS3_CONFIG_DC_MASK, MIPS3_CONFIG_DC_SHIFT);
+	    MIPS3_CONFIG_DC_MASK, mips3_csizebase, MIPS3_CONFIG_DC_SHIFT);
 	mips_L1DCacheLSize = MIPS3_CONFIG_CACHE_L1_LSIZE(config,
 	    MIPS3_CONFIG_DB);
 
@@ -252,7 +253,8 @@ mips3_ConfigCache()
 }
 
 static void
-mips3_vector_init()
+mips3_vector_init(mips3_csizebase)
+	int mips3_csizebase;
 {
 
 	/* r4000 exception handler address and end */
@@ -289,7 +291,7 @@ mips3_vector_init()
 	/*
 	 * Clear out the I and D caches.
 	 */
-	mips3_ConfigCache();
+	mips3_ConfigCache(mips3_csizebase);
 
 #ifdef pmax		/* XXX */
 	mips_L2CachePresent = 1;
@@ -336,6 +338,9 @@ mips3_vector_init()
 void
 mips_vector_init()
 {
+#ifdef MIPS3
+	int mips3_csizebase = MIPS3_CONFIG_C_DEFBASE;
+#endif
 
 	/*
 	 * Copy exception-dispatch code down to exception vector.
@@ -417,6 +422,23 @@ mips_vector_init()
 		mips_num_tlb_entries = 64;
 		mips3_L1TwoWayCache = 1;
 		break;
+#if 0	/* not ready yet */
+	case MIPS_RC32364:
+		/* 
+		 * the IDT RC32364 core is a 32 bit MIPS2 processor with
+		 * MIPS3/MIPS4 extensions (e.g. it has an R4000-style TLB).
+		 * all registers are 32 bits (64 bit instructions like
+		 * ld/sd/dmfc0/dmtc0 are not allowed.
+		 * 
+		 * note that the Config register has a non-standard base
+		 * for IC and DC (2^9 instead of 2^12).
+		 */
+		cpu_arch = 3;
+		mips_num_tlb_entries = 16;  /* each entry maps 2 pages */
+		mips3_L1TwoWayCache = 1;    /* note: line size is 16bytes */
+		mips3_csizebase = 0x200;    /* non-standard base in Config */
+		break;
+#endif
 #endif /* MIPS3 */
 
 	default:
@@ -443,7 +465,7 @@ mips_vector_init()
 			mips3_locore_vec.flushDCache = mips3_FlushDCache_2way;
 			mips3_locore_vec.flushICache = mips3_FlushICache_2way;
 		}
-		mips3_vector_init();
+		mips3_vector_init(mips3_csizebase);
 		memcpy(mips_locoresw, mips3_locoresw, sizeof(mips_locoresw));
 		break;
 #endif