Sun Blade 100 support (and some psycho fixes from Jason Wright).
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eeh
parent
58bcf84390
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9d636228e1
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@ -1,4 +1,4 @@
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/* $NetBSD: ebus.c,v 1.24 2001/07/25 03:49:54 eeh Exp $ */
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/* $NetBSD: ebus.c,v 1.25 2001/09/10 16:17:06 eeh Exp $ */
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/*
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* Copyright (c) 1999, 2000 Matthew R. Green
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@ -140,6 +140,14 @@ ebus_match(parent, match, aux)
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strcmp(name, "ebus") == 0)
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return (1);
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/* Or a real ebus III */
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OF_getprop(node, "name", &name, sizeof(name));
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if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
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PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN &&
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PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_EBUSIII &&
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strcmp(name, "ebus") == 0)
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return (1);
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/* Or a PCI-ISA bridge XXX I hope this is on-board. */
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if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
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PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA) {
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@ -1,4 +1,4 @@
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/* $NetBSD: psycho.c,v 1.34 2001/07/20 00:07:13 eeh Exp $ */
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/* $NetBSD: psycho.c,v 1.35 2001/09/10 16:17:06 eeh Exp $ */
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/*
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* Copyright (c) 1999, 2000 Matthew R. Green
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@ -169,10 +169,20 @@ struct cfattach psycho_ca = {
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* We really should attach handlers for each.
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*
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*/
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#define ROM_PCI_NAME "pci"
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#define ROM_SABRE_MODEL "SUNW,sabre"
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#define ROM_SIMBA_MODEL "SUNW,simba"
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#define ROM_PSYCHO_MODEL "SUNW,psycho"
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struct psycho_names {
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char *p_name;
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int p_type;
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} psycho_names[] = {
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{ "SUNW,psycho", PSYCHO_MODE_PSYCHO },
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{ "pci108e,8000", PSYCHO_MODE_PSYCHO },
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{ "SUNW,sabre", PSYCHO_MODE_SABRE },
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{ "pci108e,a000", PSYCHO_MODE_SABRE },
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{ "pci108e,a001", PSYCHO_MODE_SABRE },
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{ NULL, 0 }
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};
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static int
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psycho_match(parent, match, aux)
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@ -182,13 +192,19 @@ psycho_match(parent, match, aux)
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{
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struct mainbus_attach_args *ma = aux;
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char *model = getpropstring(ma->ma_node, "model");
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int i;
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/* match on a name of "pci" and a sabre or a psycho */
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if (strcmp(ma->ma_name, ROM_PCI_NAME) == 0 &&
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(strcmp(model, ROM_SABRE_MODEL) == 0 ||
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strcmp(model, ROM_PSYCHO_MODEL) == 0))
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return (1);
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if (strcmp(ma->ma_name, ROM_PCI_NAME) == 0) {
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for (i=0; psycho_names[i].p_name; i++)
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if (strcmp(model, psycho_names[i].p_name) == 0)
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return (1);
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model = getpropstring(ma->ma_node, "compatible");
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for (i=0; psycho_names[i].p_name; i++)
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if (strcmp(model, psycho_names[i].p_name) == 0)
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return (1);
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}
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return (0);
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}
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@ -216,7 +232,7 @@ psycho_attach(parent, self, aux)
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struct mainbus_attach_args *ma = aux;
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bus_space_handle_t bh;
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u_int64_t csr;
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int psycho_br[2], n;
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int psycho_br[2], n, i;
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struct pci_ctl *pci_ctl;
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char *model = getpropstring(ma->ma_node, "model");
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@ -229,13 +245,21 @@ psycho_attach(parent, self, aux)
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/*
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* call the model-specific initialisation routine.
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*/
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for (i=0; psycho_names[i].p_name; i++)
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if (strcmp(model, psycho_names[i].p_name) == 0) {
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sc->sc_mode = psycho_names[i].p_type;
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goto found;
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}
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if (strcmp(model, ROM_SABRE_MODEL) == 0)
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sc->sc_mode = PSYCHO_MODE_SABRE;
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else if (strcmp(model, ROM_PSYCHO_MODEL) == 0)
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sc->sc_mode = PSYCHO_MODE_PSYCHO;
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else
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panic("psycho_attach: unknown model %s?", model);
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model = getpropstring(ma->ma_node, "compatible");
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for (i=0; psycho_names[i].p_name; i++)
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if (strcmp(model, psycho_names[i].p_name) == 0) {
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sc->sc_mode = psycho_names[i].p_type;
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goto found;
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}
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panic("unknown psycho model %s", model);
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found:
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/*
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* The psycho gets three register banks:
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@ -600,7 +624,8 @@ psycho_bus_a(arg)
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panic("%s: PCI bus A error AFAR %llx AFSR %llx\n",
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sc->sc_dev.dv_xname,
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(long long)regs->psy_ue_afar, (long long)regs->psy_ue_afsr);
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(long long)regs->psy_pcictl[0].pci_afar,
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(long long)regs->psy_pcictl[0].pci_afsr);
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return (1);
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}
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static int
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@ -616,7 +641,8 @@ psycho_bus_b(arg)
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panic("%s: PCI bus B error AFAR %llx AFSR %llx\n",
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sc->sc_dev.dv_xname,
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(long long)regs->psy_ue_afar, (long long)regs->psy_ue_afsr);
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(long long)regs->psy_pcictl[0].pci_afar,
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(long long)regs->psy_pcictl[0].pci_afsr);
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return (1);
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}
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static int
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@ -1,4 +1,4 @@
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/* $NetBSD: psychoreg.h,v 1.7 2001/07/20 00:07:13 eeh Exp $ */
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/* $NetBSD: psychoreg.h,v 1.8 2001/09/10 16:17:06 eeh Exp $ */
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/*
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* Copyright (c) 1998, 1999 Eduardo E. Horvath
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@ -95,7 +95,7 @@ struct psychoreg {
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u_int64_t pcib_slot2_int; /* PCI bus b slot 1 irq map reg */ /* 1fe.0000.0c30 */
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u_int64_t pcib_slot3_int; /* PCI bus b slot 1 irq map reg */ /* 1fe.0000.0c38 */
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u_int64_t pad5[120];
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u_int64_t pad4[120];
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u_int64_t scsi_int_map; /* SCSI interrupt map reg */ /* 1fe.0000.1000 */
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u_int64_t ether_int_map; /* ethernet interrupt map reg */ /* 1fe.0000.1008 */
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@ -119,7 +119,7 @@ struct psychoreg {
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u_int64_t ffb0_int_map; /* FFB0 graphics interrupt map reg */ /* 1fe.0000.1098 */
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u_int64_t ffb1_int_map; /* FFB1 graphics interrupt map reg */ /* 1fe.0000.10a0 */
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u_int64_t pad6[107];
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u_int64_t pad5[107];
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/* Note: clear interrupt 0 registers are not really used */
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u_int64_t pcia0_clr_int[4]; /* PCI a slot 0 clear int regs 0..7 */ /* 1fe.0000.1400-1418 */
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@ -131,7 +131,7 @@ struct psychoreg {
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u_int64_t pcib2_clr_int[4]; /* PCI b slot 2 clear int regs 0..7 */ /* 1fe.0000.14c0-14d8 */
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u_int64_t pcib3_clr_int[4]; /* PCI b slot 3 clear int regs 0..7 */ /* 1fe.0000.14d0-14f8 */
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u_int64_t pad8[96];
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u_int64_t pad6[96];
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u_int64_t scsi_clr_int; /* SCSI clear int reg */ /* 1fe.0000.1800 */
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u_int64_t ether_clr_int; /* ethernet clear int reg */ /* 1fe.0000.1808 */
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@ -153,11 +153,11 @@ struct psychoreg {
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u_int64_t pciberr_clr_int; /* PCI bus b error clear int reg */ /* 1fe.0000.1888 */
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u_int64_t pwrmgt_clr_int; /* power mgmt wake clr interrupt reg */ /* 1fe.0000.1890 */
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u_int64_t pad9[45];
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u_int64_t pad7[45];
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u_int64_t intr_retry_timer; /* interrupt retry timer */ /* 1fe.0000.1a00 */
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u_int64_t pad10[63];
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u_int64_t pad8[63];
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struct timer_counter {
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u_int64_t tc_count; /* timer/counter 0/1 count register */ /* 1fe.0000.1c00,1c10 */
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@ -166,55 +166,56 @@ struct psychoreg {
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u_int64_t pci_dma_write_sync; /* PCI DMA write sync register (IIi) */ /* 1fe.0000.1c20 */
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u_int64_t pad11[123];
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u_int64_t pad9[123];
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struct pci_ctl {
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u_int64_t pci_csr; /* PCI a/b control/status register */ /* 1fe.0000.2000,4000 */
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u_int64_t pad10;
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u_int64_t pci_afsr; /* PCI a/b AFSR register */ /* 1fe.0000.2010,4010 */
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u_int64_t pci_afar; /* PCI a/b AFAR register */ /* 1fe.0000.2018,4018 */
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u_int64_t pci_diag; /* PCI a/b diagnostic register */ /* 1fe.0000.2020,4020 */
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u_int64_t pci_tasr; /* PCI target address space reg (IIi)*/ /* 1fe.0000.2028,4028 */
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u_int64_t pad12[251];
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u_int64_t pad11[250];
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/* This is really the IOMMU's, not the PCI bus's */
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struct iommu_strbuf pci_strbuf; /* 1fe.0000.2800-210 */
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#define psy_iommu_strbuf psy_pcictl[0].pci_strbuf
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u_int64_t pad13[765];
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u_int64_t pad12[765];
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} psy_pcictl[2]; /* For PCI a and b */
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/* NB: FFB0 and FFB1 intr map regs also appear at 1fe.0000.6000 and 1fe.0000.8000 respectively */
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u_int64_t pad14[2048];
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u_int64_t pad13[2048];
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u_int64_t dma_scb_diag0; /* DMA scoreboard diag reg 0 */ /* 1fe.0000.a000 */
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u_int64_t dma_scb_diag1; /* DMA scoreboard diag reg 1 */ /* 1fe.0000.a008 */
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u_int64_t pad15[126];
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u_int64_t pad14[126];
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u_int64_t iommu_svadiag; /* IOMMU virtual addr diag reg */ /* 1fe.0000.a400 */
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u_int64_t iommu_tlb_comp_diag; /* IOMMU TLB tag compare diag reg */ /* 1fe.0000.a408 */
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u_int64_t pad16[30];
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u_int64_t pad15[30];
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u_int64_t iommu_queue_diag[16]; /* IOMMU LRU queue diag */ /* 1fe.0000.a500-a578 */
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u_int64_t tlb_tag_diag[16]; /* TLB tag diag */ /* 1fe.0000.a580-a5f8 */
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u_int64_t tlb_data_diag[16]; /* TLB data RAM diag */ /* 1fe.0000.a600-a678 */
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u_int64_t pad17[48];
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u_int64_t pad16[48];
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u_int64_t pci_int_diag; /* SBUS int state diag reg */ /* 1fe.0000.a800 */
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u_int64_t obio_int_diag; /* OBIO and misc int state diag reg */ /* 1fe.0000.a808 */
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u_int64_t pad18[254];
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u_int64_t pad17[254];
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struct strbuf_diag {
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u_int64_t strbuf_data_diag[128]; /* streaming buffer data RAM diag */ /* 1fe.0000.b000-b3f8 */
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u_int64_t strbuf_error_diag[128]; /* streaming buffer error status diag *//* 1fe.0000.b400-b7f8 */
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u_int64_t strbuf_pg_tag_diag[16]; /* streaming buffer page tag diag */ /* 1fe.0000.b800-b878 */
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u_int64_t pad19[16];
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u_int64_t pad18[16];
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u_int64_t strbuf_ln_tag_diag[16]; /* streaming buffer line tag diag */ /* 1fe.0000.b900-b978 */
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u_int64_t pad20[208];
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u_int64_t pad19[208];
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} psy_strbufdiag[2]; /* For PCI a and b */
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/*
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