Move the DVMA mapin/mapout functions from the SBus driver to the iommu driver.
This commit is contained in:
eeh
parent
069858b1e2
commit
9cf2782159
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@ -1,4 +1,4 @@
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/* $NetBSD: iommu.c,v 1.1 1999/06/04 13:48:48 mrg Exp $ */
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/* $NetBSD: iommu.c,v 1.2 1999/06/20 00:51:29 eeh Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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@ -136,31 +136,18 @@ iommu_init(name, is, tsbsize)
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/* we want 8K pages */
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is->is_cr = IOMMUCR_8KPG | IOMMUCR_EN;
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/* set the tsbsize and get the dvmabase */
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switch (tsbsize) {
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case 0:
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is->is_dvmabase = 0x1fffffff;
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is->is_cr |= IOMMUCR_TSB1K;
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break;
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#if 0
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/* XXX are these right? got the values from the linux driver */
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case 1:
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is->is_dvmabase = 0x3fffffff;
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is->is_cr |= IOMMUCR_TSB2K;
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break;
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case 2:
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is->is_dvmabase = 0x7fffffff;
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is->is_cr |= IOMMUCR_TSB4K;
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break;
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#endif
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default:
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panic("unknown tsbsize, fix me");
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}
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/*
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*
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* The IOMMU address space always ends at 0xffffe000, but the starting
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* address depends on the size of the map. The map size is 1024 * 2 ^
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* is->is_tsbsize entries, where each entry is 8 bytes. The start of
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* the map can be calculated by (0xffffe000 << (8 + is->is_tsbsize)).
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*
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* Note: the stupid IOMMU ignores the high bits of an address, so a
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* NULL DMA pointer will be translated by the first page of the IOTSB.
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* To trap bugs we'll skip the first entry in the IOTSB.
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*/
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is->is_dvmabase = IOTSB_VSTART(is->is_tsbsize) + NBPG;
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is->is_tsbsize = tsbsize;
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is->is_tsb = malloc(NBPG, M_DMAMAP, M_WAITOK); /* XXX */
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is->is_ptsb = pmap_extract(pmap_kernel(), (vaddr_t)is->is_tsb);
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@ -194,18 +181,9 @@ iommu_init(name, is, tsbsize)
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/*
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* Now all the hardware's working we need to allocate a dvma map.
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*
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* The IOMMU address space always ends at 0xffffe000, but the starting
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* address depends on the size of the map. The map size is 1024 * 2 ^
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* is->is_tsbsize entries, where each entry is 8 bytes. The start of
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* the map can be calculated by (0xffffe000 << (8 + is->is_tsbsize)).
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*
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* Note: the stupid IOMMU ignores the high bits of an address, so a
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* NULL DMA pointer will be translated by the first page of the IOTSB.
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* To trap bugs we'll skip the first entry in the IOTSB.
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*/
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is->is_dvmamap = extent_create(name,
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IOTSB_VSTART(is->is_tsbsize) + NBPG, IOTSB_VEND,
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is->is_dvmabase, IOTSB_VEND,
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M_DEVBUF, 0, 0, EX_NOWAIT);
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}
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@ -220,3 +198,162 @@ iommu_reset(is)
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/* Enable diagnostics mode? */
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bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_ctl, 0, STRBUF_EN);
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}
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/*
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* Here are the iommu control routines.
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*/
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void
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iommu_enter(is, va, pa, flags)
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struct iommu_state *is;
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vaddr_t va;
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int64_t pa;
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int flags;
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{
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int64_t tte;
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#ifdef DIAGNOSTIC
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if (va < is->is_dvmabase)
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panic("sbus_enter: va 0x%lx not in DVMA space",va);
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#endif
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tte = MAKEIOTTE(pa, !(flags&BUS_DMA_NOWRITE), !(flags&BUS_DMA_NOCACHE),
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!(flags&BUS_DMA_COHERENT));
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/* Is the streamcache flush really needed? */
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bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_pgflush,
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0, va);
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iommu_flush(is);
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#ifdef DEBUG
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if (iommudebug & IDB_DVMA)
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printf("Clearing TSB slot %d for va %p\n",
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(int)IOTSBSLOT(va,is->is_tsbsize), va);
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#endif
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is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)] = tte;
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bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_flush,
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0, va);
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#ifdef DEBUG
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if (iommudebug & IDB_DVMA)
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printf("sbus_enter: va %lx pa %lx TSB[%lx]@%p=%lx\n",
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va, (long)pa, IOTSBSLOT(va,is->is_tsbsize),
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&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)],
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(long)tte);
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#endif
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}
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/*
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* iommu_remove: removes mappings created by iommu_enter
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*
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* Only demap from IOMMU if flag is set.
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*/
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void
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iommu_remove(is, va, len)
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struct iommu_state *is;
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vaddr_t va;
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size_t len;
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{
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#ifdef DIAGNOSTIC
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if (va < is->is_dvmabase)
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panic("sbus_remove: va 0x%lx not in DVMA space", (long)va);
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if ((long)(va + len) < (long)va)
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panic("sbus_remove: va 0x%lx + len 0x%lx wraps",
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(long) va, (long) len);
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if (len & ~0xfffffff)
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panic("sbus_remove: rediculous len 0x%lx", (long)len);
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#endif
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va = trunc_page(va);
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while (len > 0) {
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/*
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* Streaming buffer flushes:
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*
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* 1 Tell strbuf to flush by storing va to strbuf_pgflush
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* If we're not on a cache line boundary (64-bits):
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* 2 Store 0 in flag
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* 3 Store pointer to flag in flushsync
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* 4 wait till flushsync becomes 0x1
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*
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* If it takes more than .5 sec, something went wrong.
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*/
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#ifdef DEBUG
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if (iommudebug & IDB_DVMA)
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printf("sbus_remove: flushing va %p TSB[%lx]@%p=%lx, %lu bytes left\n",
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(long)va, (long)IOTSBSLOT(va,is->is_tsbsize),
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(long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)],
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(long)(is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)]),
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(u_long)len);
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#endif
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bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_pgflush, 0, va);
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if (len <= NBPG) {
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iommu_flush(is);
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len = 0;
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} else len -= NBPG;
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#ifdef DEBUG
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if (iommudebug & IDB_DVMA)
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printf("sbus_remove: flushed va %p TSB[%lx]@%p=%lx, %lu bytes left\n",
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(long)va, (long)IOTSBSLOT(va,is->is_tsbsize),
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(long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)],
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(long)(is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)]),
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(u_long)len);
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#endif
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is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)] = 0;
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bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_flush, 0, va);
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va += NBPG;
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}
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}
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int
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iommu_flush(is)
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struct iommu_state *is;
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{
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struct timeval cur, flushtimeout;
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#define BUMPTIME(t, usec) { \
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register volatile struct timeval *tp = (t); \
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register long us; \
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\
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tp->tv_usec = us = tp->tv_usec + (usec); \
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if (us >= 1000000) { \
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tp->tv_usec = us - 1000000; \
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tp->tv_sec++; \
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} \
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}
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is->is_flush = 0;
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membar_sync();
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bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_flushsync, 0, is->is_flushpa);
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membar_sync();
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microtime(&flushtimeout);
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cur = flushtimeout;
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BUMPTIME(&flushtimeout, 500000); /* 1/2 sec */
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#ifdef DEBUG
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if (iommudebug & IDB_DVMA)
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printf("sbus_flush: flush = %lx at va = %lx pa = %lx now=%lx:%lx until = %lx:%lx\n",
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(long)is->is_flush, (long)&is->is_flush,
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(long)is->is_flushpa, cur.tv_sec, cur.tv_usec,
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flushtimeout.tv_sec, flushtimeout.tv_usec);
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#endif
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/* Bypass non-coherent D$ */
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while (!ldxa(is->is_flushpa, ASI_PHYS_CACHED) &&
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((cur.tv_sec <= flushtimeout.tv_sec) &&
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(cur.tv_usec <= flushtimeout.tv_usec)))
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microtime(&cur);
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#ifdef DIAGNOSTIC
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if (!is->is_flush) {
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printf("sbus_flush: flush timeout %p at %p\n", (long)is->is_flush,
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(long)is->is_flushpa); /* panic? */
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#ifdef DDB
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Debugger();
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#endif
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}
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#endif
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#ifdef DEBUG
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if (iommudebug & IDB_DVMA)
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printf("sbus_flush: flushed\n");
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#endif
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return (is->is_flush);
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: iommuvar.h,v 1.1 1999/06/04 13:48:48 mrg Exp $ */
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/* $NetBSD: iommuvar.h,v 1.2 1999/06/20 00:51:29 eeh Exp $ */
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/*
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* Copyright (c) 1999 Matthew R. Green
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@ -55,5 +55,8 @@ struct iommu_state {
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/* interfaces for PCI/SBUS code */
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void iommu_init __P((char *, struct iommu_state *, int));
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void iommu_reset __P((struct iommu_state *));
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void iommu_enter __P((struct iommu_state *, vaddr_t, int64_t, int));
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void iommu_remove __P((struct iommu_state *, vaddr_t, size_t));
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int iommu_flush __P((struct iommu_state *));
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#endif /* _SPARC64_DEV_IOMMUVAR_H_ */
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@ -1,4 +1,4 @@
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/* $NetBSD: sbus.c,v 1.18 1999/06/07 05:28:03 eeh Exp $ */
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/* $NetBSD: sbus.c,v 1.19 1999/06/20 00:51:30 eeh Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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@ -135,7 +135,6 @@ int sbusdebug = 0;
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#endif
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void sbusreset __P((int));
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int sbus_flush __P((struct sbus_softc *));
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static bus_space_tag_t sbus_alloc_bustag __P((struct sbus_softc *));
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static bus_dma_tag_t sbus_alloc_dmatag __P((struct sbus_softc *));
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@ -173,8 +172,6 @@ extern struct cfdriver sbus_cd;
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/*
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* DVMA routines
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*/
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void sbus_enter __P((struct sbus_softc *, vaddr_t, int64_t, int));
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void sbus_remove __P((struct sbus_softc *, vaddr_t, size_t));
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int sbus_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *,
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bus_size_t, struct proc *, int));
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void sbus_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t));
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@ -549,165 +546,6 @@ sbusreset(sbus)
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iommu_reset(&sc->sc_is);
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}
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/*
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* Here are the iommu control routines.
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*/
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void
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sbus_enter(sc, va, pa, flags)
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struct sbus_softc *sc;
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vaddr_t va;
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int64_t pa;
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int flags;
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{
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int64_t tte;
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#ifdef DIAGNOSTIC
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if (va < sc->sc_is.is_dvmabase)
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panic("sbus_enter: va 0x%lx not in DVMA space",va);
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#endif
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tte = MAKEIOTTE(pa, !(flags&BUS_DMA_NOWRITE), !(flags&BUS_DMA_NOCACHE),
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!(flags&BUS_DMA_COHERENT));
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/* Is the streamcache flush really needed? */
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bus_space_write_8(sc->sc_bustag, &sc->sc_is.is_sb->strbuf_pgflush,
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0, va);
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sbus_flush(sc);
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#ifdef DEBUG
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if (sbusdebug & SDB_DVMA)
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printf("Clearing TSB slot %d for va %p\n", (int)IOTSBSLOT(va,sc->sc_is.is_tsbsize), va);
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#endif
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sc->sc_is.is_tsb[IOTSBSLOT(va,sc->sc_is.is_tsbsize)] = tte;
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bus_space_write_8(sc->sc_bustag, &sc->sc_sysio->sys_iommu.iommu_flush,
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0, va);
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#ifdef DEBUG
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if (sbusdebug & SDB_DVMA)
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printf("sbus_enter: va %lx pa %lx TSB[%lx]@%p=%lx\n",
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va, (long)pa, IOTSBSLOT(va,sc->sc_is.is_tsbsize),
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&sc->sc_is.is_tsb[IOTSBSLOT(va,sc->sc_is.is_tsbsize)],
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(long)tte);
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#endif
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}
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/*
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* sbus_clear: clears mappings created by sbus_enter
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*
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* Only demap from IOMMU if flag is set.
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*/
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void
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sbus_remove(sc, va, len)
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struct sbus_softc *sc;
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vaddr_t va;
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size_t len;
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{
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#ifdef DIAGNOSTIC
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if (va < sc->sc_is.is_dvmabase)
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panic("sbus_remove: va 0x%lx not in DVMA space", (long)va);
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if ((long)(va + len) < (long)va)
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panic("sbus_remove: va 0x%lx + len 0x%lx wraps",
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(long) va, (long) len);
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if (len & ~0xfffffff)
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panic("sbus_remove: rediculous len 0x%lx", (long)len);
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#endif
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va = trunc_page(va);
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while (len > 0) {
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/*
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* Streaming buffer flushes:
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*
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* 1 Tell strbuf to flush by storing va to strbuf_pgflush
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* If we're not on a cache line boundary (64-bits):
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* 2 Store 0 in flag
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* 3 Store pointer to flag in flushsync
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* 4 wait till flushsync becomes 0x1
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*
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* If it takes more than .5 sec, something went wrong.
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*/
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#ifdef DEBUG
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if (sbusdebug & SDB_DVMA)
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printf("sbus_remove: flushing va %p TSB[%lx]@%p=%lx, %lu bytes left\n",
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(long)va, (long)IOTSBSLOT(va,sc->sc_is.is_tsbsize),
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(long)&sc->sc_is.is_tsb[IOTSBSLOT(va,sc->sc_is.is_tsbsize)],
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(long)(sc->sc_is.is_tsb[IOTSBSLOT(va,sc->sc_is.is_tsbsize)]),
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(u_long)len);
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#endif
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bus_space_write_8(sc->sc_bustag, &sc->sc_is.is_sb->strbuf_pgflush, 0, va);
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if (len <= NBPG) {
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sbus_flush(sc);
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len = 0;
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} else len -= NBPG;
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#ifdef DEBUG
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if (sbusdebug & SDB_DVMA)
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printf("sbus_remove: flushed va %p TSB[%lx]@%p=%lx, %lu bytes left\n",
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(long)va, (long)IOTSBSLOT(va,sc->sc_is.is_tsbsize),
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(long)&sc->sc_is.is_tsb[IOTSBSLOT(va,sc->sc_is.is_tsbsize)],
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(long)(sc->sc_is.is_tsb[IOTSBSLOT(va,sc->sc_is.is_tsbsize)]),
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(u_long)len);
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#endif
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sc->sc_is.is_tsb[IOTSBSLOT(va,sc->sc_is.is_tsbsize)] = 0;
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bus_space_write_8(sc->sc_bustag, &sc->sc_sysio->sys_iommu.iommu_flush, 0, va);
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va += NBPG;
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}
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}
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int
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sbus_flush(sc)
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struct sbus_softc *sc;
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{
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struct timeval cur, flushtimeout;
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struct iommu_state *is = &sc->sc_is;
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#define BUMPTIME(t, usec) { \
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register volatile struct timeval *tp = (t); \
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register long us; \
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\
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tp->tv_usec = us = tp->tv_usec + (usec); \
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if (us >= 1000000) { \
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tp->tv_usec = us - 1000000; \
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tp->tv_sec++; \
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} \
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}
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is->is_flush = 0;
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membar_sync();
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bus_space_write_8(sc->sc_bustag, &is->is_sb->strbuf_flushsync, 0, is->is_flushpa);
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membar_sync();
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microtime(&flushtimeout);
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cur = flushtimeout;
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BUMPTIME(&flushtimeout, 500000); /* 1/2 sec */
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#ifdef DEBUG
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if (sbusdebug & SDB_DVMA)
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printf("sbus_flush: flush = %lx at va = %lx pa = %lx now=%lx:%lx until = %lx:%lx\n",
|
||||
(long)is->is_flush, (long)&is->is_flush,
|
||||
(long)is->is_flushpa, cur.tv_sec, cur.tv_usec,
|
||||
flushtimeout.tv_sec, flushtimeout.tv_usec);
|
||||
#endif
|
||||
/* Bypass non-coherent D$ */
|
||||
while (!ldxa(is->is_flushpa, ASI_PHYS_CACHED) &&
|
||||
((cur.tv_sec <= flushtimeout.tv_sec) &&
|
||||
(cur.tv_usec <= flushtimeout.tv_usec)))
|
||||
microtime(&cur);
|
||||
|
||||
#ifdef DIAGNOSTIC
|
||||
if (!is->is_flush) {
|
||||
printf("sbus_flush: flush timeout %p at %p\n", (long)is->is_flush,
|
||||
(long)is->is_flushpa); /* panic? */
|
||||
#ifdef DDB
|
||||
Debugger();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
#ifdef DEBUG
|
||||
if (sbusdebug & SDB_DVMA)
|
||||
printf("sbus_flush: flushed\n");
|
||||
#endif
|
||||
return (is->is_flush);
|
||||
}
|
||||
|
||||
/*
|
||||
* Get interrupt attributes for an Sbus device.
|
||||
*/
|
||||
|
|
@ -969,7 +807,7 @@ sbus_dmamap_load(t, map, buf, buflen, p, flags)
|
|||
#endif
|
||||
bus_dmamap_unload(t, map);
|
||||
}
|
||||
#if 1
|
||||
|
||||
/*
|
||||
* Make sure that on error condition we return "no valid mappings".
|
||||
*/
|
||||
|
|
@ -1017,10 +855,6 @@ sbus_dmamap_load(t, map, buf, buflen, p, flags)
|
|||
map->dm_segs[0].ds_addr = dvmaddr + (vaddr & PGOFSET);
|
||||
map->dm_segs[0].ds_len = sgsize;
|
||||
|
||||
#else
|
||||
if ((err = bus_dmamap_load(t->_parent, map, buf, buflen, p, flags)))
|
||||
return (err);
|
||||
#endif
|
||||
if (p != NULL)
|
||||
pmap = p->p_vmspace->vm_map.pmap;
|
||||
else
|
||||
|
|
@ -1049,7 +883,7 @@ sbus_dmamap_load(t, map, buf, buflen, p, flags)
|
|||
printf("sbus_dmamap_load: map %p loading va %lx at pa %lx\n",
|
||||
map, (long)dvmaddr, (long)(curaddr & ~(NBPG-1)));
|
||||
#endif
|
||||
sbus_enter(sc, trunc_page(dvmaddr), trunc_page(curaddr), flags);
|
||||
iommu_enter(&sc->sc_is, trunc_page(dvmaddr), trunc_page(curaddr), flags);
|
||||
|
||||
dvmaddr += PAGE_SIZE;
|
||||
vaddr += sgsize;
|
||||
|
|
@ -1080,8 +914,7 @@ sbus_dmamap_unload(t, map)
|
|||
printf("sbus_dmamap_unload: map %p removing va %lx size %lx\n",
|
||||
map, (long)addr, (long)len);
|
||||
#endif
|
||||
sbus_remove(sc, addr, len);
|
||||
#if 1
|
||||
iommu_remove(&sc->sc_is, addr, len);
|
||||
dvmaddr = (map->dm_segs[0].ds_addr & ~PGOFSET);
|
||||
sgsize = map->dm_segs[0].ds_len;
|
||||
|
||||
|
|
@ -1097,9 +930,6 @@ sbus_dmamap_unload(t, map)
|
|||
printf("warning: %ld of DVMA space lost\n", (long)sgsize);
|
||||
|
||||
cache_flush((caddr_t)dvmaddr, (u_int) sgsize);
|
||||
#else
|
||||
bus_dmamap_unload(t->_parent, map);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1157,7 +987,7 @@ sbus_dmamap_sync(t, map, offset, len, ops)
|
|||
#endif
|
||||
bus_space_write_8(sc->sc_bustag, &sc->sc_is.is_sb->strbuf_pgflush, 0, va);
|
||||
if (len <= NBPG) {
|
||||
sbus_flush(sc);
|
||||
iommu_flush(&sc->sc_is);
|
||||
len = 0;
|
||||
} else
|
||||
len -= NBPG;
|
||||
|
|
@ -1242,7 +1072,7 @@ sbus_dmamem_alloc(t, size, alignment, boundary, segs, nsegs, rsegs, flags)
|
|||
printf("sbus_dmamem_alloc: map %p loading va %lx at pa %lx\n",
|
||||
(long)m, (long)dvmaddr, (long)(curaddr & ~(NBPG-1)));
|
||||
#endif
|
||||
sbus_enter(sc, dvmaddr, curaddr, flags);
|
||||
iommu_enter(&sc->sc_is, dvmaddr, curaddr, flags);
|
||||
dvmaddr += PAGE_SIZE;
|
||||
}
|
||||
}
|
||||
|
|
@ -1264,7 +1094,7 @@ sbus_dmamem_free(t, segs, nsegs)
|
|||
for (n=0; n<nsegs; n++) {
|
||||
addr = segs[n].ds_addr;
|
||||
len = segs[n].ds_len;
|
||||
sbus_remove(sc, addr, len);
|
||||
iommu_remove(&sc->sc_is, addr, len);
|
||||
#if 1
|
||||
s = splhigh();
|
||||
error = extent_free(sc->sc_is.is_dvmamap, addr, len, EX_NOWAIT);
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: cpu.h,v 1.10 1999/06/07 05:28:04 eeh Exp $ */
|
||||
/* $NetBSD: cpu.h,v 1.11 1999/06/20 00:51:30 eeh Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1992, 1993
|
||||
|
|
@ -212,9 +212,6 @@ void kgdb_attach __P((int (*)(void *), void (*)(void *, int), void *));
|
|||
void kgdb_connect __P((int));
|
||||
void kgdb_panic __P((void));
|
||||
#endif
|
||||
/* iommu.c */
|
||||
void iommu_enter __P((u_int, u_int));
|
||||
void iommu_remove __P((u_int, u_int));
|
||||
/* emul.c */
|
||||
int fixalign __P((struct proc *, struct trapframe *));
|
||||
int emulinstr __P((vaddr_t, struct trapframe *));
|
||||
|
|
|
|||
Loading…
Reference in New Issue