OMAP4 EHCI enhancements
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matt
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@ -1,4 +1,4 @@
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/* $NetBSD: omap2_reg.h,v 1.18 2013/04/30 05:37:51 matt Exp $ */
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/* $NetBSD: omap2_reg.h,v 1.19 2013/06/16 16:42:13 matt Exp $ */
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/*
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* Copyright (c) 2007 Microsoft
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@ -87,6 +87,32 @@
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#define OMAP4430_L4_ABE_BASE 0x49000000 /* Actually L3 */
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#define OMAP4430_L4_ABE_SIZE 0x01000000 /* 16MB */
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#define OMAP4430_EMIF1_BASE 0x4C000000 /* MemCtrl 0 */
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#define OMAP4430_EMIF1_SIZE 0x00100000 /* 4KB padded to 1M */
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#define OMAP4430_EMIF2_BASE 0x4D000000 /* MemCtrl 1 */
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#define OMAP4430_EMIF2_SIZE 0x00100000 /* 4KB padded to 1M */
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/* OMAP5 processors */
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#define OMAP5430_L4_CORE_BASE 0x4A000000
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#define OMAP5430_L4_CORE_SIZE 0x01000000 /* 16MB - CFG */
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#define OMAP5430_L4_WAKEUP_BASE 0x4AE00000
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#define OMAP5430_L4_WAKEUP_SIZE 0x00200000 /* 2M */
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#define OMAP5430_L4_PERIPHERAL_BASE 0x48000000
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#define OMAP5430_L4_PERIPHERAL_SIZE 0x01000000 /* 16MB */
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#define OMAP5430_L4_ABE_BASE 0x49000000 /* Actually L3 */
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#define OMAP5430_L4_ABE_SIZE 0x01000000 /* 16MB */
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#define OMAP5430_EMIF1_BASE 0x4C000000 /* MemCtrl 0 */
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#define OMAP5430_EMIF1_SIZE 0x00100000 /* 4KB padded to 1M */
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#define OMAP5430_EMIF2_BASE 0x4D000000 /* MemCtrl 1 */
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#define OMAP5430_EMIF2_SIZE 0x00100000 /* 4KB padded to 1M */
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/* TI Sitara AM335x (OMAP like) */
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#define TI_AM335X_L4_WAKEUP_BASE 0x44C00000
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@ -98,8 +124,8 @@
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#define TI_AM335X_L4_FAST_BASE 0x4A000000
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#define TI_AM335X_L4_FAST_SIZE 0x01000000 /* 16MB */
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#define TI_AM335X_L4_EMIF_BASE 0x4C000000
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#define TI_AM335X_L4_EMIF_SIZE 0x01000000 /* 16MB */
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#define TI_AM335X_EMIF1_BASE 0x4C000000
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#define TI_AM335X_EMIF1_SIZE 0x00100000 /* 4KB pad to 1MB */
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/* TI Sitara DM37xx (OMAP like) */
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@ -133,6 +159,9 @@
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#ifdef OMAP_4430
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#define OMAP2_CM_BASE (OMAP4430_L4_CORE_BASE + 0x04000)
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#endif
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#ifdef OMAP_5430
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#define OMAP2_CM_BASE (OMAP5430_L4_CORE_BASE + 0x04000)
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#endif
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#ifdef TI_AM335X
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#define OMAP2_CM_BASE (TI_AM335X_L4_WAKEUP_BASE + 0x200000)
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#endif
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@ -346,6 +375,9 @@
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#ifdef OMAP_4430
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#define OMAP2_PRM_BASE (OMAP4430_L4_WAKEUP_BASE + 0x6000)
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#endif
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#ifdef OMAP_5430
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#define OMAP2_PRM_BASE (OMAP5430_L4_WAKEUP_BASE + 0x6000)
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#endif
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#ifdef TI_AM335X
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#define OMAP2_PRM_BASE 0x48306000
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#endif
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@ -670,6 +702,15 @@
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#define GPIO5_BASE_4430 0x4805b000
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#define GPIO6_BASE_4430 0x4805d000
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#define GPIO1_BASE_5430 0x4ae10000
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#define GPIO2_BASE_5430 0x48055000
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#define GPIO3_BASE_5430 0x48057000
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#define GPIO4_BASE_5430 0x48059000
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#define GPIO5_BASE_5430 0x4805b000
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#define GPIO6_BASE_5430 0x4805d000
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#define GPIO7_BASE_5430 0x48051000
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#define GPIO8_BASE_5430 0x48053000
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#define GPIO0_BASE_TI_AM335X 0x44e07000
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#define GPIO1_BASE_TI_AM335X 0x4804c000
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#define GPIO2_BASE_TI_AM335X 0x481ac000
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@ -718,14 +759,11 @@
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*/
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#define OHCI1_BASE_2430 0x4805e000
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#define OHCI1_BASE_3430 0x48064400
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#define EHCI1_BASE_3430 0x48064800
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#define OHCI1_BASE_OMAP3 0x48064400
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#define EHCI1_BASE_OMAP3 0x48064800
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#define OHCI1_BASE_3530 0x48064400
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#define EHCI1_BASE_3530 0x48064800
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#define OHCI1_BASE_4430 0x4A064800
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#define EHCI1_BASE_4430 0x4A064C00
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#define OHCI1_BASE_OMAP4 0x4A064800
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#define EHCI1_BASE_OMAP4 0x4A064C00
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/*
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* SDRC
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@ -743,13 +781,13 @@
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#define TI_AM335X_CTLMOD_BASE 0x44e10000
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#define CTLMOD_CONTROL_STATUS 0x40
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#define CTLMOD_CONTROL_STATUS_SYSBOOT1 __BITS(23,22)
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#define TI_AM335X_EMIF0_BASE 0x4c000000
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#define TI_AM335X_EMIF0_SIZE 0x00100000
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#endif
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#if defined(OMAP4) || defined(TI_AM335X)
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#define EMIF_SDRAM_CONFIG 8
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#define SDRAM_CONFIG_WIDTH __BITS(15,14)
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#define SDRAM_CONFIG_RSIZE __BITS(9,7)
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#define SDRAM_CONFIG_IBANK __BITS(6,4)
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#define SDRAM_CONFIG_EBANK __BIT(3)
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#define SDRAM_CONFIG_PAGESIZE __BITS(2,0)
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#endif
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@ -1,4 +1,4 @@
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/* $NetBSD: omap3_ehci.c,v 1.6 2012/12/24 06:41:02 kiyohara Exp $ */
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/* $NetBSD: omap3_ehci.c,v 1.7 2013/06/16 16:42:13 matt Exp $ */
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/*-
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* Copyright (c) 2010-2012 Jared D. McNeill <jmcneill@invisible.ca>
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@ -26,7 +26,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: omap3_ehci.c,v 1.6 2012/12/24 06:41:02 kiyohara Exp $");
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__KERNEL_RCSID(0, "$NetBSD: omap3_ehci.c,v 1.7 2013/06/16 16:42:13 matt Exp $");
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#include "locators.h"
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@ -273,10 +273,18 @@ omap3_ehci_attach1(device_t self)
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static int
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omap3_ehci_match(device_t parent, cfdata_t match, void *opaque)
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{
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#ifdef OMAP3
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struct obio_attach_args *obio = opaque;
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#endif
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if (obio->obio_addr == EHCI1_BASE_3530)
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#if defined(OMAP3) && !defined(OMAP4)
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if (obio->obio_addr == EHCI1_BASE_OMAP3)
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return 1;
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#endif
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#ifdef OMAP4
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if (obio->obio_addr == EHCI1_BASE_OMAP4)
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return 1;
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#endif
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return 0;
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}
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@ -429,7 +437,6 @@ dpll5_init(struct omap3_ehci_softc *sc)
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{
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bus_space_tag_t iot = sc->sc.iot;
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bus_space_handle_t ioh;
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uint32_t m, n, m2;
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int err;
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if (sc->sc_dpll5.m == 0 || sc->sc_dpll5.n == 0 || sc->sc_dpll5.m2 == 0)
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@ -440,27 +447,38 @@ dpll5_init(struct omap3_ehci_softc *sc)
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panic("%s: cannot map CCR_CM_BASE at %#x, error %d\n",
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__func__, CCR_CM_BASE, err);
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#if OMAP_MPU_TIMER_CLOCK_FREQ != 12000000
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#error FIXME
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#endif
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#if defined(OMAP_3530) || defined(OMAP_3540)
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/* set the multiplier and divider values for the desired CLKOUT freq */
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m = sc->sc_dpll5.m;
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n = sc->sc_dpll5.n;
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uint32_t m = sc->sc_dpll5.m;
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uint32_t n = sc->sc_dpll5.n;
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/* set the corresponding output dividers */
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m2 = sc->sc_dpll5.m2;
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uint32_t m2 = sc->sc_dpll5.m2;
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/* 4.7.6.2 In the DPLL programming sequence, the DPLL_FREQSEL must be programmed
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* before the new Multiplier factor M and the Divider factor N are programmed so
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* that the new value is taken into account during current DPLL relock.
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KASSERTMSG(479900000 <= 2 * m * (omap_sys_clk / ((n + 1) * m2)),
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"m=%u n=%u m2=%u freq=%u",
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m, n, m2, 2 * m * (omap_sys_clk / ((n + 1) * m2)));
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KASSERTMSG(2 * m * (omap_sys_clk / ((n + 1) * m2)) <= 480100000,
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"m=%u n=%u m2=%u freq=%u",
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m, n, m2, 2 * m * (omap_sys_clk / ((n + 1) * m2)));
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/* 4.7.6.2
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* In the DPLL programming sequence, the DPLL_FREQSEL must be
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* programmed before the new Multiplier factor M and the Divider
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* factor N are programmed so that the new value is taken into
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* account during current DPLL relock.
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*/
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bus_space_write_4(iot, ioh, CM_CLKEN2_PLL, (0x4 << 4) | 0x7);
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bus_space_write_4(iot, ioh, CM_CLKSEL4_PLL, (m << 8) | n);
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bus_space_write_4(iot, ioh, CM_CLKSEL5_PLL, m2);
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/* Put DPLL5 into low power stop mode when the 120MHz clock is not required (restarted automatically) */
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/*
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* Put DPLL5 into low power stop mode when the 120MHz clock
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* is not required (restarted automatically)
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*/
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bus_space_write_4(iot, ioh, CM_AUTOIDLE2_PLL, AUTO_PERIPH2_DPLL);
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#endif /* OMAP_3540 || OMAP_3530 */
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bus_space_unmap(iot, ioh, CCR_CM_SIZE);
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}
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