Remove all i386 host bridges, as they don't apply. Remove pchb_rndattach
call for now (may be back later).
This commit is contained in:
fvdl
parent
99193cfa98
commit
9c71037485
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@ -1,4 +1,4 @@
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/* $NetBSD: pchb.c,v 1.2 2002/05/16 01:01:42 thorpej Exp $ */
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/* $NetBSD: pchb.c,v 1.3 2002/06/04 17:51:30 fvdl Exp $ */
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/*-
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* Copyright (c) 1996, 1998, 2000 The NetBSD Foundation, Inc.
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@ -102,19 +102,10 @@ pchbattach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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#if NRND > 0
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struct pchb_softc *sc = (void *) self;
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#endif
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struct pci_attach_args *pa = aux;
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char devinfo[256];
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struct pcibus_attach_args pba;
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pcireg_t bcreg;
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u_char bdnum, pbnum;
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pcitag_t tag;
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int doattach;
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printf("\n");
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doattach = 0;
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/*
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* Print out a description, and configure certain chipsets which
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@ -125,139 +116,11 @@ pchbattach(parent, self, aux)
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printf("%s: %s (rev. 0x%02x)\n", self->dv_xname, devinfo,
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PCI_REVISION(pa->pa_class));
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switch (PCI_VENDOR(pa->pa_id)) {
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case PCI_VENDOR_SERVERWORKS:
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pbnum = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x44) & 0xff;
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if (pbnum == 0)
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/* Nothing yet */
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default:
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break;
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/*
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* This host bridge has a second PCI bus.
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* Configure it.
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*/
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doattach = 1;
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break;
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case PCI_VENDOR_INTEL:
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switch (PCI_PRODUCT(pa->pa_id)) {
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case PCI_PRODUCT_INTEL_82443BX_AGP:
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case PCI_PRODUCT_INTEL_82443BX_NOAGP:
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/*
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* BIOS BUG WORKAROUND! The 82443BX
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* datasheet indicates that the only
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* legal setting for the "Idle/Pipeline
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* DRAM Leadoff Timing (IPLDT)" parameter
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* (bits 9:8) is 01. Unfortunately, some
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* BIOSs do not set these bits properly.
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*/
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bcreg = pci_conf_read(pa->pa_pc, pa->pa_tag,
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I82443BX_SDRAMC_REG);
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if ((bcreg & 0x0300) != 0x0100) {
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printf("%s: fixing Idle/Pipeline DRAM "
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"Leadoff Timing\n", self->dv_xname);
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bcreg &= ~0x0300;
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bcreg |= 0x0100;
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pci_conf_write(pa->pa_pc, pa->pa_tag,
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I82443BX_SDRAMC_REG, bcreg);
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}
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break;
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case PCI_PRODUCT_INTEL_PCI450_PB:
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bcreg = pci_conf_read(pa->pa_pc, pa->pa_tag,
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PCISET_BUSCONFIG_REG);
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bdnum = PCISET_BRIDGE_NUMBER(bcreg);
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pbnum = PCISET_PCI_BUS_NUMBER(bcreg);
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switch (bdnum & PCISET_BRIDGETYPE_MASK) {
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default:
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printf("%s: bdnum=%x (reserved)\n",
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self->dv_xname, bdnum);
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break;
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case PCISET_TYPE_COMPAT:
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printf("%s: Compatibility PB (bus %d)\n",
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self->dv_xname, pbnum);
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break;
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case PCISET_TYPE_AUX:
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printf("%s: Auxiliary PB (bus %d)\n",
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self->dv_xname, pbnum);
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/*
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* This host bridge has a second PCI bus.
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* Configure it.
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*/
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doattach = 1;
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break;
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}
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break;
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case PCI_PRODUCT_INTEL_CDC:
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bcreg = pci_conf_read(pa->pa_pc, pa->pa_tag,
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I82424_CPU_BCTL_REG);
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if (bcreg & I82424_BCTL_CPUPCI_POSTEN) {
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bcreg &= ~I82424_BCTL_CPUPCI_POSTEN;
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pci_conf_write(pa->pa_pc, pa->pa_tag,
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I82424_CPU_BCTL_REG, bcreg);
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printf("%s: disabled CPU-PCI write posting\n",
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self->dv_xname);
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}
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break;
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case PCI_PRODUCT_INTEL_82451NX_PXB:
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/*
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* The NX chipset supports up to 2 "PXB" chips
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* which can drive 2 PCI buses each. Each bus
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* shows up as logical PCI device, with fixed
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* device numbers between 18 and 21.
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* See the datasheet at
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ftp://download.intel.com/design/chipsets/datashts/24377102.pdf
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* for details.
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* (It would be easier to attach all the buses
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* at the MIOC, but less aesthetical imho.)
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*/
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pbnum = 0;
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switch (pa->pa_device) {
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case 18: /* PXB 0 bus A - primary bus */
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break;
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case 19: /* PXB 0 bus B */
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/* read SUBA0 from MIOC */
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tag = pci_make_tag(pa->pa_pc, 0, 16, 0);
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bcreg = pci_conf_read(pa->pa_pc, tag, 0xd0);
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pbnum = ((bcreg & 0x0000ff00) >> 8) + 1;
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break;
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case 20: /* PXB 1 bus A */
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/* read BUSNO1 from MIOC */
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tag = pci_make_tag(pa->pa_pc, 0, 16, 0);
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bcreg = pci_conf_read(pa->pa_pc, tag, 0xd0);
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pbnum = (bcreg & 0xff000000) >> 24;
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break;
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case 21: /* PXB 1 bus B */
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/* read SUBA1 from MIOC */
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tag = pci_make_tag(pa->pa_pc, 0, 16, 0);
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bcreg = pci_conf_read(pa->pa_pc, tag, 0xd4);
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pbnum = (bcreg & 0x000000ff) + 1;
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break;
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}
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if (pbnum != 0)
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doattach = 1;
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break;
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}
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break;
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}
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if (doattach) {
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pba.pba_busname = "pci";
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pba.pba_iot = pa->pa_iot;
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pba.pba_memt = pa->pa_memt;
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pba.pba_dmat = pa->pa_dmat;
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pba.pba_bus = pbnum;
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pba.pba_bridgetag = NULL;
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pba.pba_flags = pa->pa_flags;
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pba.pba_pc = pa->pa_pc;
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config_found(self, &pba, pchb_print);
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}
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#if NRND > 0
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/*
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* Attach a random number generator, if there is one.
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*/
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pchb_attach_rnd(sc, pa);
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#endif
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}
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int
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