Add PA-RISC 2.0 PIM support.
Fix the HPMC exception handler so that, if we're running on a PA-RISC 2.0 machine, we use the 64-bit PIM data structures. There was also a bug in the HPMC exception handler that stopped output being written to the console after we'd taken the exception. We need to make a PDC_IO pdc call to reset I/O.
This commit is contained in:
mjf
parent
87e79748d0
commit
9c6bc36bdd
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@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.63 2009/05/13 14:33:42 skrll Exp $ */
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/* $NetBSD: machdep.c,v 1.64 2009/05/16 16:06:06 mjf Exp $ */
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/*-
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* Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
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@ -58,7 +58,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.63 2009/05/13 14:33:42 skrll Exp $");
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.64 2009/05/16 16:06:06 mjf Exp $");
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#include "opt_cputype.h"
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#include "opt_ddb.h"
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@ -1455,12 +1455,20 @@ cpu_dumpsize(void)
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* an LPMC, or a TOC. The check type is passed in as a trap
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* type, one of T_HPMC, T_LPMC, or T_INTERRUPT (for TOC).
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*/
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static char pim_data_buffer[4096]; /* XXX assumed to be big enough */
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static char pim_data_buffer[896] __attribute__((__aligned__(8)));
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static char in_check = 0;
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void
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hppa_machine_check(int check_type)
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#define PIM_WORD(name, word, bits) \
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do { \
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snprintb(bitmask_buffer, sizeof(bitmask_buffer),\
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bits, word); \
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printf("%s %s", name, bitmask_buffer); \
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} while (/* CONSTCOND */ 0)
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static inline void
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hppa_pim_dump(int check_type)
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{
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int pdc_pim_type;
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struct hp700_pim_hpmc *hpmc;
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struct hp700_pim_lpmc *lpmc;
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struct hp700_pim_toc *toc;
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@ -1470,37 +1478,20 @@ hppa_machine_check(int check_type)
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int reg_i, reg_j, reg_k;
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char bitmask_buffer[64];
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const char *name;
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int error;
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#define PIM_WORD(name, word, bits) \
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do { \
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snprintb(bitmask_buffer, sizeof(bitmask_buffer),\
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bits, word); \
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printf("%s %s", name, bitmask_buffer); \
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} while (/* CONSTCOND */ 0)
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/* Do an fcacheall(). */
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fcacheall();
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/* Dispatch on the check type. */
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regs = NULL;
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checks = NULL;
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switch (check_type) {
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case T_HPMC:
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name = "HPMC";
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pdc_pim_type = PDC_PIM_HPMC;
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hpmc = (struct hp700_pim_hpmc *) pim_data_buffer;
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regs = &hpmc->pim_hpmc_regs;
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checks = &hpmc->pim_hpmc_checks;
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break;
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case T_LPMC:
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name = "LPMC";
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pdc_pim_type = PDC_PIM_LPMC;
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lpmc = (struct hp700_pim_lpmc *) pim_data_buffer;
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checks = &lpmc->pim_lpmc_checks;
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break;
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case T_INTERRUPT:
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name = "TOC";
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pdc_pim_type = PDC_PIM_TOC;
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toc = (struct hp700_pim_toc *) pim_data_buffer;
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regs = &toc->pim_toc_regs;
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break;
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@ -1508,11 +1499,6 @@ do { \
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panic("unknown machine check type");
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/* NOTREACHED */
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}
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printf("\nmachine check: %s", name);
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error = pdc_call((iodcio_t)pdc, 0, PDC_PIM, pdc_pim_type,
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&pdc_pim, pim_data_buffer, sizeof(pim_data_buffer));
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if (error < 0)
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printf(" - WARNING: could not transfer PIM info (%d)", error);
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/* If we have register arrays, display them. */
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if (regs != NULL) {
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@ -1538,7 +1524,8 @@ do { \
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}
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/* Print out some interesting registers. */
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printf("\n\n\tIIA 0x%x:0x%08x 0x%x:0x%08x",
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printf("\n\n\tIIA head 0x%x:0x%08x\n"
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"\tIIA tail 0x%x:0x%08x",
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regs->pim_regs_cr17, regs->pim_regs_cr18,
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regs->pim_regs_iisq_tail, regs->pim_regs_iioq_tail);
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PIM_WORD("\n\tIPSW", regs->pim_regs_cr22, PSW_BITS);
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@ -1569,6 +1556,164 @@ do { \
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printf("\n\tPath Info 0x%08x",
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checks->pim_check_path_info);
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}
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}
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static inline void
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hppa_pim64_dump(int check_type)
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{
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struct hp700_pim64_hpmc *hpmc;
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struct hp700_pim64_lpmc *lpmc;
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struct hp700_pim64_toc *toc;
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struct hp700_pim64_regs *regs;
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struct hp700_pim64_checks *checks;
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int reg_i, reg_j, reg_k;
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uint64_t *regarray;
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char bitmask_buffer[64];
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const char *name;
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regs = NULL;
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checks = NULL;
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switch (check_type) {
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case T_HPMC:
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hpmc = (struct hp700_pim64_hpmc *) pim_data_buffer;
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regs = &hpmc->pim_hpmc_regs;
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checks = &hpmc->pim_hpmc_checks;
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break;
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case T_LPMC:
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lpmc = (struct hp700_pim64_lpmc *) pim_data_buffer;
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checks = &lpmc->pim_lpmc_checks;
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break;
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case T_INTERRUPT:
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toc = (struct hp700_pim64_toc *) pim_data_buffer;
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regs = &toc->pim_toc_regs;
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break;
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default:
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panic("unknown machine check type");
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/* NOTREACHED */
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}
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/* If we have register arrays, display them. */
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if (regs != NULL) {
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for (reg_i = 0; reg_i < 3; reg_i++) {
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if (reg_i == 0) {
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name = "General";
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regarray = ®s->pim_regs_r0;
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reg_j = 32;
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} else if (reg_i == 1) {
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name = "Control";
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regarray = ®s->pim_regs_cr0;
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reg_j = 32;
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} else {
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name = "Space";
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regarray = ®s->pim_regs_sr0;
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reg_j = 8;
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}
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printf("\n\n\t%s Registers:", name);
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for (reg_k = 0; reg_k < reg_j; reg_k++) {
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printf("%s",
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(reg_k & 1) ? " " : "\n\t");
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if (!(reg_k & 1))
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printf("%2d: ", reg_k);
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printf("0x%016lx",
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(unsigned long)regarray[reg_k]);
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}
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}
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/* Print out some interesting registers. */
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printf("\n\n\tIIA head 0x%lx:0x%016lx\n"
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"\tIIA tail 0x%lx:0x%016lx",
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(unsigned long)regs->pim_regs_cr17,
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(unsigned long)regs->pim_regs_cr18,
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(unsigned long)regs->pim_regs_iisq_tail,
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(unsigned long)regs->pim_regs_iioq_tail);
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PIM_WORD("\n\tIPSW", regs->pim_regs_cr22, PSW_BITS);
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printf("\n\tSP 0x%lx:0x%016lx\n\tFP 0x%lx:0x%016lx",
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(unsigned long)regs->pim_regs_sr0,
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(unsigned long)regs->pim_regs_r30,
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(unsigned long)regs->pim_regs_sr0,
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(unsigned long)regs->pim_regs_r3);
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}
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/* If we have check words, display them. */
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if (checks != NULL) {
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PIM_WORD("\n\n\tCheck Type", checks->pim_check_type,
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PIM_CHECK_BITS);
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PIM_WORD("\n\tCPU State", checks->pim_check_cpu_state,
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PIM_CPU_BITS PIM_CPU_HPMC_BITS);
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PIM_WORD("\n\tCache Check", checks->pim_check_cache,
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PIM_CACHE_BITS);
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PIM_WORD("\n\tTLB Check", checks->pim_check_tlb,
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PIM_TLB_BITS);
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PIM_WORD("\n\tBus Check", checks->pim_check_bus,
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PIM_BUS_BITS);
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PIM_WORD("\n\tAssist Check", checks->pim_check_assist,
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PIM_ASSIST_BITS);
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printf("\tAssist State %u", checks->pim_check_assist_state);
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printf("\n\tSystem Responder 0x%016lx",
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(unsigned long)checks->pim_check_responder);
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printf("\n\tSystem Requestor 0x%016lx",
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(unsigned long)checks->pim_check_requestor);
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printf("\n\tPath Info 0x%08x",
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checks->pim_check_path_info);
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}
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}
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void
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hppa_machine_check(int check_type)
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{
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int pdc_pim_type;
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const char *name;
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int error;
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/* Do an fcacheall(). */
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fcacheall();
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/* Dispatch on the check type. */
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switch (check_type) {
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case T_HPMC:
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name = "HPMC";
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pdc_pim_type = PDC_PIM_HPMC;
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break;
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case T_LPMC:
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name = "LPMC";
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pdc_pim_type = PDC_PIM_LPMC;
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break;
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case T_INTERRUPT:
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name = "TOC";
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pdc_pim_type = PDC_PIM_TOC;
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break;
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default:
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panic("unknown machine check type");
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/* NOTREACHED */
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}
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error = pdc_call((iodcio_t)pdc, 0, PDC_PIM, pdc_pim_type,
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&pdc_pim, pim_data_buffer, sizeof(pim_data_buffer));
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if (error < 0)
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printf(" - WARNING: could not transfer PIM info (%d)", error);
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CTASSERT(pdc_pim.count <= sizeof(pim_data_buffer));
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/*
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* Reset IO and log errors.
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*
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* This seems to be needed in order to output to the console
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* if we take a HPMC interrupt. This PDC procedure may not be
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* implemented by some machines.
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*/
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error = pdc_call((iodcio_t)pdc, 0, PDC_IO, 0, 0, 0, 0);
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if (error != PDC_ERR_OK && error != PDC_ERR_NOPROC)
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/* This seems futile if we can't print to the console. */
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panic("PDC_IO failed");
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printf("\nmachine check: %s", name);
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if (hppa_cpu_info->hci_features & HPPA_FTRS_W32B)
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hppa_pim64_dump(check_type);
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else
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hppa_pim_dump(check_type);
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printf("\n");
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/* If this is our first check, panic. */
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@ -1,4 +1,4 @@
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/* $NetBSD: pim.h,v 1.2 2008/04/28 20:23:19 martin Exp $ */
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/* $NetBSD: pim.h,v 1.3 2009/05/16 16:06:06 mjf Exp $ */
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/*-
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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@ -36,6 +36,9 @@
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*
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* "PA/RISC 1.1 I/O Firmware Architecture Reference Specification",
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* Version 1.0, August 22, 2001.
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*
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* "PA/RISC 2.0 I/O Firmware Architecture Reference Specification",
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* Version 1.0, August 22, 2001.
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*/
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/* The PIM data for HPMC and TOC contains these register arrays. */
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@ -262,3 +265,138 @@ struct hp700_pim_toc {
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u_int pim_toc_hversion_dep;
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u_int pim_toc_cpu_state;
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};
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struct hp700_pim64_regs {
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/* The general registers. */
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u_int64_t pim_regs_r0;
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u_int64_t pim_regs_r1;
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u_int64_t pim_regs_r2;
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u_int64_t pim_regs_r3;
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u_int64_t pim_regs_r4;
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u_int64_t pim_regs_r5;
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u_int64_t pim_regs_r6;
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u_int64_t pim_regs_r7;
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u_int64_t pim_regs_r8;
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u_int64_t pim_regs_r9;
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u_int64_t pim_regs_r10;
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u_int64_t pim_regs_r11;
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u_int64_t pim_regs_r12;
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u_int64_t pim_regs_r13;
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u_int64_t pim_regs_r14;
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u_int64_t pim_regs_r15;
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u_int64_t pim_regs_r16;
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u_int64_t pim_regs_r17;
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u_int64_t pim_regs_r18;
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u_int64_t pim_regs_r19;
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u_int64_t pim_regs_r20;
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u_int64_t pim_regs_r21;
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u_int64_t pim_regs_r22;
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u_int64_t pim_regs_r23;
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u_int64_t pim_regs_r24;
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u_int64_t pim_regs_r25;
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u_int64_t pim_regs_r26;
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u_int64_t pim_regs_r27;
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u_int64_t pim_regs_r28;
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u_int64_t pim_regs_r29;
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u_int64_t pim_regs_r30;
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u_int64_t pim_regs_r31;
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/* The control registers. */
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u_int64_t pim_regs_cr0;
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u_int64_t pim_regs_cr1;
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u_int64_t pim_regs_cr2;
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u_int64_t pim_regs_cr3;
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u_int64_t pim_regs_cr4;
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u_int64_t pim_regs_cr5;
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u_int64_t pim_regs_cr6;
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u_int64_t pim_regs_cr7;
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u_int64_t pim_regs_cr8;
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u_int64_t pim_regs_cr9;
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u_int64_t pim_regs_cr10;
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u_int64_t pim_regs_cr11;
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u_int64_t pim_regs_cr12;
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u_int64_t pim_regs_cr13;
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u_int64_t pim_regs_cr14;
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u_int64_t pim_regs_cr15;
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u_int64_t pim_regs_cr16;
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u_int64_t pim_regs_cr17;
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u_int64_t pim_regs_cr18;
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u_int64_t pim_regs_cr19;
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u_int64_t pim_regs_cr20;
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u_int64_t pim_regs_cr21;
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u_int64_t pim_regs_cr22;
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u_int64_t pim_regs_cr23;
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u_int64_t pim_regs_cr24;
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u_int64_t pim_regs_cr25;
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u_int64_t pim_regs_cr26;
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u_int64_t pim_regs_cr27;
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u_int64_t pim_regs_cr28;
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u_int64_t pim_regs_cr29;
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u_int64_t pim_regs_cr30;
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u_int64_t pim_regs_cr31;
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/* The space registers. */
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u_int64_t pim_regs_sr0;
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u_int64_t pim_regs_sr1;
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u_int64_t pim_regs_sr2;
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u_int64_t pim_regs_sr3;
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u_int64_t pim_regs_sr4;
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u_int64_t pim_regs_sr5;
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u_int64_t pim_regs_sr6;
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u_int64_t pim_regs_sr7;
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/* The back entries of the instruction address queues. */
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u_int64_t pim_regs_iisq_tail;
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u_int64_t pim_regs_iioq_tail;
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};
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struct hp700_pim64_checks {
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/* The Check Type. */
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u_int pim_check_type;
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/*
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* The CPU State. In addition to the common PIM_CPU_
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* bits defined below, some fields are HPMC-specific.
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*/
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u_int pim_check_cpu_state;
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/* The Cache Check word. */
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u_int pim_check_cache;
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/* The TLB Check word. */
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u_int pim_check_tlb;
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/* The Bus Check word. */
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u_int pim_check_bus;
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/* The Assist Check word. */
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u_int pim_check_assist;
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/* Additional information about the check. */
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u_int pim_check_assist_state;
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u_int pim_check_path_info;
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u_int64_t pim_check_responder;
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u_int64_t pim_check_requestor;
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};
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/* The PARISC 2.0 HPMC PIM data. */
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struct hp700_pim64_hpmc {
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struct hp700_pim64_regs pim_hpmc_regs;
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struct hp700_pim64_checks pim_hpmc_checks;
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struct hp700_pim_fpregs pim_hpmc_fpregs;
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};
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/* The PARISC 2.0 LPMC PIM data. */
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struct hp700_pim64_lpmc {
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u_int64_t pim_lmpc_hversion_dep[74];
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struct hp700_pim64_checks pim_lpmc_checks;
|
||||
struct hp700_pim_fpregs pim_lpmc_fpregs;
|
||||
};
|
||||
|
||||
/* The PARISC 2.0 TOC PIM data. */
|
||||
struct hp700_pim64_toc {
|
||||
struct hp700_pim64_regs pim_toc_regs;
|
||||
u_int pim_toc_hversion_dep;
|
||||
u_int pim_toc_cpu_state;
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue