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x86 changes for pcc and LKMs. 

- Replace most inline assembly with proper functions. As a side effect
  this reduces the size of amd64 GENERIC by about 120kB, and i386 by a
  smaller amount. Nearly all of the inlines did something slow, or something
  that does not need to be fast.
- Make curcpu() and curlwp functions proper, unless __GNUC__ && _KERNEL.
  In that case make them inlines. Makes curlwp LKM and preemption safe.
- Make bus_space and bus_dma more LKM friendly.
- Share a few more files between the ports.
- Other minor changes.
This commit is contained in:
ad 2007-09-26 19:48:34 +00:00
parent 7bc5694f64
commit 9c412e0cbf
79 changed files with 3816 additions and 3604 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

456
sys/arch/amd64/amd64/busfunc.S Normal file
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@ -0,0 +1,456 @@
/* $NetBSD: busfunc.S,v 1.1 2007/09/26 19:48:34 ad Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Andrew Doran.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <machine/asm.h>
#include "assym.h"
/* XXX */
#undef _ALIGN_TEXT
#define _ALIGN_TEXT .align 16
#if X86_BUS_SPACE_IO != 0
#error depends on X86_BUS_SPACE_IO == 0
#endif
/*
* uint8_t bus_space_read_1(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset);
*/
NENTRY(bus_space_read_1)
addq %rsi, %rdx
testl %edi, %edi
je 1f
movzbl (%rdx), %eax
ret
1:
xorl %eax, %eax
inb %dx, %al
ret
/*
* uint16_t bus_space_read_2(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset);
*/
NENTRY(bus_space_read_2)
addq %rsi, %rdx
testl %edi, %edi
je 1f
movzwl (%rdx), %eax
ret
1:
xorl %eax, %eax
inw %dx, %ax
ret
/*
* uint32_t bus_space_read_4(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset);
*/
NENTRY(bus_space_read_4)
addq %rsi, %rdx
testl %edi, %edi
je 1f
movl (%rdx), %eax
ret
1:
inl %dx, %eax
ret
STRONG_ALIAS(bus_space_read_stream_1,bus_space_read_1)
STRONG_ALIAS(bus_space_read_stream_2,bus_space_read_2)
STRONG_ALIAS(bus_space_read_stream_4,bus_space_read_4)
/*
* void bus_space_write_1(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, uint8_t value);
*/
NENTRY(bus_space_write_1)
addq %rsi, %rdx
testl %edi, %edi
je 1f
movb %cl, (%rdx)
ret
1:
movl %ecx, %eax
outb %al, %dx
ret
/*
* void bus_space_write_2(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, uint16_t value);
*/
NENTRY(bus_space_write_2)
addq %rsi, %rdx
testl %edi, %edi
je 1f
movw %cx, (%rdx)
ret
1:
movl %ecx, %eax
outw %ax, %dx
ret
/*
* void bus_space_write_4(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, uint32_t value);
*/
NENTRY(bus_space_write_4)
addq %rsi, %rdx
testl %edi, %edi
je 1f
movl %ecx, (%rdx)
ret
1:
movl %ecx, %eax
outl %eax, %dx
ret
STRONG_ALIAS(bus_space_write_stream_1,bus_space_write_1)
STRONG_ALIAS(bus_space_write_stream_2,bus_space_write_2)
STRONG_ALIAS(bus_space_write_stream_4,bus_space_write_4)
/*
* void bus_space_read_multi_1(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, uint8_t *addr, size_t count);
*/
NENTRY(bus_space_read_multi_1)
testl %edi, %edi
leaq (%rsi,%rdx,1), %rdx
jne 1f
movq %rcx, %rdi
movq %r8, %rcx
cld
rep
insb (%dx), %es:(%rdi)
ret
.align 16
1:
movb (%rdx), %al
decq %r8
movb %al, (%rcx)
leaq 1(%rcx), %rcx
jnz 1b
ret
/*
* void bus_space_read_multi_2(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, uint16_t *addr, size_t count);
*/
NENTRY(bus_space_read_multi_2)
testl %edi, %edi
leaq (%rsi,%rdx,1), %rdx
jne 1f
movq %rcx, %rdi
movq %r8, %rcx
cld
rep
insw (%dx), %es:(%rdi)
ret
.align 16
1:
movw (%rdx), %ax
decq %r8
movw %ax, (%rcx)
leaq 2(%rcx), %rcx
jnz 1b
ret
/*
* void bus_space_read_multi_4(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, uint32_t *addr, size_t count);
*/
NENTRY(bus_space_read_multi_4)
testl %edi, %edi
leaq (%rsi,%rdx,1), %rdx
jne 1f
movq %rcx, %rdi
movq %r8, %rcx
cld
rep
insl (%dx), %es:(%rdi)
ret
.align 16
1:
movl (%rdx), %eax
decq %r8
movl %eax, (%rcx)
leaq 4(%rcx), %rcx
jnz 1b
ret
STRONG_ALIAS(bus_space_read_multi_stream_1,bus_space_read_multi_1)
STRONG_ALIAS(bus_space_read_multi_stream_2,bus_space_read_multi_2)
STRONG_ALIAS(bus_space_read_multi_stream_4,bus_space_read_multi_4)
/*
* void bus_space_write_multi_1(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, const uint8_t *addr, size_t count);
*/
NENTRY(bus_space_write_multi_1)
testl %edi, %edi
leaq (%rsi,%rdx,1), %rdx
jne 1f
movq %rcx, %rsi
movq %r8, %rcx
cld
rep
outsb %ds:(%rsi), (%dx)
ret
.align 16
1:
movb (%rcx), %al
decq %r8
movb %al, (%rdx)
leaq 1(%rcx), %rcx
jnz 1b
ret
/*
* void bus_space_write_multi_2(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, const uint16_t *addr, size_t count);
*/
NENTRY(bus_space_write_multi_2)
testl %edi, %edi
leaq (%rsi,%rdx,1), %rdx
jne 1f
movq %rcx, %rsi
movq %r8, %rcx
cld
rep
outsw %ds:(%rsi), (%dx)
ret
.align 16
1:
movw (%rcx), %ax
decq %r8
movw %ax, (%rdx)
leaq 2(%rcx), %rcx
jnz 1b
ret
/*
* void bus_space_write_multi_4(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, const uint32_t *addr, size_t count);
*/
NENTRY(bus_space_write_multi_4)
testl %edi, %edi
leaq (%rsi,%rdx,1), %rdx
jne 1f
movq %rcx, %rsi
movq %r8, %rcx
cld
rep
outsl %ds:(%rsi), (%dx)
ret
.align 16
1:
movl (%rcx), %eax
decq %r8
movl %eax, (%rdx)
leaq 4(%rcx), %rcx
jnz 1b
ret
STRONG_ALIAS(bus_space_write_multi_stream_1,bus_space_write_multi_1)
STRONG_ALIAS(bus_space_write_multi_stream_2,bus_space_write_multi_2)
STRONG_ALIAS(bus_space_write_multi_stream_4,bus_space_write_multi_4)
/*
* void bus_space_read_region_1(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, uint8_t *addr, size_t count);
*/
NENTRY(bus_space_read_region_1)
testl %edi, %edi
jne 2f
1:
addq %rdx, %rsi
movq %rcx, %rdi
movq %r8, %rcx
cld
rep
movsb %ds:(%rsi), %es:(%rdi)
ret
2:
addl %esi, %edx
3:
inb %dx, %al
incl %edx
decq %r8
movb %al, (%rcx)
leaq 1(%rcx), %rcx
jnz 3b
ret
/*
* void bus_space_read_region_2(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, uint16_t *addr, size_t count);
*/
NENTRY(bus_space_read_region_2)
testl %edi, %edi
jne 2f
1:
addq %rdx, %rsi
movq %rcx, %rdi
movq %r8, %rcx
cld
rep
movsw %ds:(%rsi), %es:(%rdi)
ret
2:
addl %esi, %edx
3:
inw %dx, %ax
addl $2, %edx
decq %r8
movw %ax, (%rcx)
leaq 2(%rcx), %rcx
jnz 3b
ret
/*
* void bus_space_read_region_4(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, uint32_t *addr, size_t count);
*/
NENTRY(bus_space_read_region_4)
testl %edi, %edi
jne 2f
1:
addq %rdx, %rsi
movq %rcx, %rdi
movq %r8, %rcx
cld
rep
movsl %ds:(%rsi), %es:(%rdi)
ret
2:
addl %esi, %edx
3:
inl %dx, %eax
addl $4, %edx
decq %r8
movl %eax, (%rcx)
leaq 4(%rcx), %rcx
jnz 3b
ret
STRONG_ALIAS(bus_space_read_region_stream_1,bus_space_read_region_1)
STRONG_ALIAS(bus_space_read_region_stream_2,bus_space_read_region_2)
STRONG_ALIAS(bus_space_read_region_stream_4,bus_space_read_region_4)
/*
* void bus_space_write_region_1(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, const uint8_t *addr, size_t count);
*/
NENTRY(bus_space_write_region_1)
testl %edi, %edi
jne 2f
1:
addq %rdx, %rsi
movq %rcx, %rdi
movq %r8, %rcx
cld
rep
movsb %ds:(%rsi), %es:(%rdi)
ret
2:
addl %esi, %edx
3:
movb (%rcx), %al
incq %rcx
decq %r8
outb %al, %dx
leaq 1(%rdx), %rdx
jnz 3b
ret
/*
* void bus_space_write_region_2(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, const uint16_t *addr, size_t count);
*/
NENTRY(bus_space_write_region_2)
testl %edi, %edi
jne 2f
1:
addq %rdx, %rsi
movq %rcx, %rdi
movq %r8, %rcx
cld
rep
movsw %ds:(%rsi), %es:(%rdi)
ret
2:
addl %esi, %edx
3:
movw (%rcx), %ax
addq $2, %rcx
decq %r8
outw %ax, %dx
leaq 2(%rdx), %rdx
jnz 3b
ret
/*
* void bus_space_write_region_4(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, const uint32_t *addr, size_t count);
*/
NENTRY(bus_space_write_region_4)
testl %edi, %edi
jne 2f
1:
addq %rdx, %rsi
movq %rcx, %rdi
movq %r8, %rcx
cld
rep
movsl %ds:(%rsi), %es:(%rdi)
ret
2:
addl %esi, %edx
3:
movl (%rcx), %eax
addq $4, %rcx
decq %r8
outl %eax, %dx
leaq 4(%rdx), %rdx
jnz 3b
ret
STRONG_ALIAS(bus_space_write_region_stream_1,bus_space_write_region_1)
STRONG_ALIAS(bus_space_write_region_stream_2,bus_space_write_region_2)
STRONG_ALIAS(bus_space_write_region_stream_4,bus_space_write_region_4)

515
sys/arch/amd64/amd64/cpufunc.S Normal file
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/* $NetBSD: cpufunc.S,v 1.1 2007/09/26 19:48:34 ad Exp $ */
/*-
* Copyright (c) 1998, 2007 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Charles M. Hannum, and by Andrew Doran.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Functions to provide access to i386-specific instructions.
*/
#include <machine/asm.h>
#include <machine/specialreg.h>
#include <machine/segments.h>
#include "assym.h"
/* Small and slow, so align less. */
#undef _ALIGN_TEXT
#define _ALIGN_TEXT .align 8
NENTRY(x86_lfence)
lfence
ret
NENTRY(x86_sfence)
sfence
ret
NENTRY(x86_mfence)
mfence
ret
NENTRY(invlpg)
invlpg (%rdi)
ret
NENTRY(lidt)
lidt (%rdi)
ret
NENTRY(lldt)
lldt %di
ret
NENTRY(ltr)
ltr %di
ret
NENTRY(lcr0)
movq %rdi, %cr0
ret
NENTRY(rcr0)
movq %cr0, %rax
ret
NENTRY(rcr2)
movq %cr2, %rax
ret
NENTRY(lcr3)
movq %rdi, %cr3
ret
NENTRY(rcr3)
movq %cr3, %rax
ret
NENTRY(lcr4)
movq %rdi, %cr4
ret
NENTRY(rcr4)
movq %cr4, %rax
ret
NENTRY(lcr8)
movq %rdi, %cr8
ret
NENTRY(rcr8)
movq %cr8, %rax
ret
/*
* Big hammer: flush all TLB entries, including ones from PTE's
* with the G bit set. This should only be necessary if TLB
* shootdown falls far behind.
*
* Intel Architecture Software Developer's Manual, Volume 3,
* System Programming, section 9.10, "Invalidating the
* Translation Lookaside Buffers (TLBS)":
* "The following operations invalidate all TLB entries, irrespective
* of the setting of the G flag:
* ...
* "(P6 family processors only): Writing to control register CR4 to
* modify the PSE, PGE, or PAE flag."
*
* (the alternatives not quoted above are not an option here.)
*/
NENTRY(tlbflushg)
movq %cr4, %rax
movq %rax, %rdx
andq $~CR4_PGE, %rdx
movq %rdx, %cr4
movq %rax, %cr4
ret
NENTRY(tlbflush)
movq %cr3, %rax
movq %rax, %cr3
ret
NENTRY(ldr6)
movq %rdi, %dr6
ret
NENTRY(rdr6)
movq %dr6, %rdi
ret
NENTRY(x86_disable_intr)
cli
ret
NENTRY(x86_enable_intr)
sti
ret
NENTRY(x86_read_flags)
pushfq
popq %rax
ret
STRONG_ALIAS(x86_read_psl,x86_read_flags)
NENTRY(x86_write_flags)
pushq %rdi
popfq
ret
STRONG_ALIAS(x86_write_psl,x86_write_flags)
NENTRY(rdmsr)
movq %rdi, %rcx
xorq %rax, %rax
rdmsr
shlq $32, %rdx
orq %rdx, %rax
ret
NENTRY(wrmsr)
movq %rdi, %rcx
movq %rsi, %rax
movq %rsi, %rdx
shrq $32, %rdx
wrmsr
ret
NENTRY(rdmsr_locked)
movq %rdi, %rcx
xorq %rax, %rax
movl $OPTERON_MSR_PASSCODE, %edi
rdmsr
shlq $32, %rdx
orq %rdx, %rax
ret
NENTRY(wrmsr_locked)
movq %rdi, %rcx
movq %rsi, %rax
movq %rsi, %rdx
shrq $32, %rdx
movl $OPTERON_MSR_PASSCODE, %edi
wrmsr
ret
NENTRY(wbinvd)
wbinvd
ret
NENTRY(rdtsc)
xorq %rax, %rax
rdtsc
shlq $32, %rdx
orq %rdx, %rax
ret
NENTRY(rdpmc)
movq %rdi, %rcx
xorq %rax, %rax
rdpmc
shlq $32, %rdx
orq %rdx, %rax
ret
NENTRY(breakpoint)
int $0x03 /* paranoid, not 'int3' */
ret
NENTRY(x86_atomic_testset_ul)
movq %rsi, %rax
xchgq %rax, (%rdi)
ret
NENTRY(x86_atomic_testset_i)
movl %esi, %eax
xchgl %eax, (%rdi)
ret
NENTRY(x86_atomic_testset_b)
movl %esi, %eax
xchgb %al, (%rdi)
andl $0xff, %eax
ret
NENTRY(x86_atomic_setbits_l)
lock
orq %rsi, (%rdi)
ret
NENTRY(x86_atomic_clearbits_l)
notq %rsi
lock
andq %rsi, (%rdi)
ret
NENTRY(x86_curcpu)
movq %gs:(CPU_INFO_SELF), %rax
ret
NENTRY(x86_curlwp)
movq %gs:(CPU_INFO_CURLWP), %rax
ret
NENTRY(__byte_swap_u32_variable)
movl %edi, %eax
bswapl %eax
ret
NENTRY(__byte_swap_u16_variable)
movl %edi, %eax
xchgb %al, %ah
ret
/*
* void lgdt(struct region_descriptor *rdp);
*
* Load a new GDT pointer (and do any necessary cleanup).
* XXX It's somewhat questionable whether reloading all the segment registers
* is necessary, since the actual descriptor data is not changed except by
* process creation and exit, both of which clean up via task switches. OTOH,
* this only happens at run time when the GDT is resized.
*/
NENTRY(lgdt)
/* Reload the descriptor table. */
movq %rdi,%rax
lgdt (%rax)
/* Flush the prefetch q. */
jmp 1f
nop
1: /* Reload "stale" selectors. */
movl $GSEL(GDATA_SEL, SEL_KPL),%eax
movl %eax,%ds
movl %eax,%es
movl %eax,%ss
/* FALLTHROUGH */
/*
* void x86_flush()
*
* Flush instruction pipelines by doing an intersegment (far) return.
*/
NENTRY(x86_flush)
popq %rax
pushq $GSEL(GCODE_SEL, SEL_KPL)
pushq %rax
lretq
/* Waits - set up stack frame. */
NENTRY(x86_hlt)
pushq %rbp
movq %rsp, %rbp
hlt
leave
ret
/* Waits - set up stack frame. */
NENTRY(x86_stihlt)
pushq %rbp
movq %rsp, %rbp
sti
hlt
leave
ret
NENTRY(x86_monitor)
movq %rdi, %rax
movq %rsi, %rcx
monitor %eax, %ecx, %edx /* XXXgas %rax */
ret
/* Waits - set up stack frame. */
NENTRY(x86_mwait)
pushq %rbp
movq %rsp, %rbp
movq %rdi, %rax
movq %rsi, %rcx
mwait %eax, %ecx
leave
ret
NENTRY(x86_pause)
pause
ret
NENTRY(x86_cpuid)
movq %rbx, %r8
movq %rdi, %rax
cpuid
movl %eax, 0(%rsi)
movl %ebx, 4(%rsi)
movl %ecx, 8(%rsi)
movl %edx, 12(%rsi)
movq %r8, %rbx
ret
NENTRY(getss)
movl %ss, %eax
ret
NENTRY(fldcw)
fldcw (%rdi)
ret
NENTRY(fnclex)
fnclex
ret
NENTRY(fninit)
fninit
ret
NENTRY(fnsave)
fnsave (%rdi)
ret
NENTRY(fnstcw)
fnstcw (%rdi)
ret
NENTRY(fnstsw)
fnstsw (%rdi)
ret
NENTRY(fp_divide_by_0)
fldz
fld1
fdiv %st, %st(1)
fwait
ret
NENTRY(frstor)
frstor (%rdi)
ret
ENTRY(fwait)
fwait
ret
ENTRY(clts)
clts
ret
ENTRY(stts)
movq %cr0, %rax
orq $CR0_TS, %rax
movq %rax, %cr0
ret
NENTRY(fxsave)
fxsave (%rdi)
ret
NENTRY(fxrstor)
fxrstor (%rdi)
ret
NENTRY(fldummy)
ffree %st(7)
fld (%rdi)
ret
NENTRY(x86_ldmxcsr)
ldmxcsr (%rdi)
ret
NENTRY(inb)
movq %rdi, %rdx
xorq %rax, %rax
inb %dx, %al
ret
NENTRY(insb)
movq %rdi, %rdx
movq %rsi, %rdi
movq %rdx, %rcx
cld
rep
insb
ret
NENTRY(inw)
movq %rdi, %rdx
xorq %rax, %rax
inw %dx, %ax
ret
NENTRY(insw)
movq %rdi, %rdx
movq %rsi, %rdi
movq %rdx, %rcx
cld
rep
insw
ret
NENTRY(inl)
movq %rdi, %rdx
xorq %rax, %rax
inl %dx, %eax
ret
NENTRY(insl)
movq %rdi, %rdx
movq %rsi, %rdi
movq %rdx, %rcx
cld
rep
insl
ret
NENTRY(outb)
movq %rdi, %rdx
movq %rsi, %rax
outb %al, %dx
ret
NENTRY(outsb)
movq %rdi, %rdx
movq %rdx, %rcx
cld
rep
outsb
ret
NENTRY(outw)
movq %rdi, %rdx
movq %rsi, %rax
outw %ax, %dx
ret
NENTRY(outsw)
movq %rdi, %rdx
movq %rdx, %rcx
cld
rep
outsw
ret
NENTRY(outl)
movq %rdi, %rdx
movq %rsi, %rax
outl %eax, %dx
ret
NENTRY(outsl)
movq %rdi, %rdx
movq %rdx, %rcx
cld
rep
outsl
ret

48
sys/arch/amd64/amd64/fpu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: fpu.c,v 1.17 2007/02/09 21:55:01 ad Exp $ */
/* $NetBSD: fpu.c,v 1.18 2007/09/26 19:48:35 ad Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@ -71,7 +71,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: fpu.c,v 1.17 2007/02/09 21:55:01 ad Exp $");
__KERNEL_RCSID(0, "$NetBSD: fpu.c,v 1.18 2007/09/26 19:48:35 ad Exp $");
#include "opt_multiprocessor.h"
@ -117,17 +117,6 @@ __KERNEL_RCSID(0, "$NetBSD: fpu.c,v 1.17 2007/02/09 21:55:01 ad Exp $");
* state is saved.
*/
#define fninit() __asm("fninit")
#define fwait() __asm("fwait")
#define fnclex() __asm("fnclex")
#define fnstsw(addr) __asm("fnstsw %0" : "=m" (*addr))
#define fxsave(addr) __asm("fxsave %0" : "=m" (*addr))
#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*addr))
#define fldcw(addr) __asm("fldcw %0" : : "m" (*addr))
#define ldmxcsr(addr) __asm("ldmxcsr %0" : : "m" (*addr))
#define clts() __asm("clts")
#define stts() lcr0(rcr0() | CR0_TS)
void fpudna(struct cpu_info *);
static int x86fpflags_to_ksiginfo(u_int32_t);
@ -160,21 +149,19 @@ fputrap(frame)
u_int16_t cw;
ksiginfo_t ksi;
#ifdef DIAGNOSTIC
/*
* At this point, fpcurlwp should be curlwp. If it wasn't, the TS bit
* should be set, and we should have gotten a DNA exception.
*/
if (l != curlwp)
panic("fputrap: wrong lwp");
#endif
fxsave(sfp);
if (frame->tf_trapno == T_XMM) {
mxcsr = sfp->fp_fxsave.fx_mxcsr;
statbits = mxcsr;
mxcsr &= ~0x3f;
ldmxcsr(&mxcsr);
x86_ldmxcsr(&mxcsr);
} else {
fninit();
fwait();
@ -238,12 +225,7 @@ fpudna(struct cpu_info *ci)
}
s = splipi();
#ifdef MULTIPROCESSOR
l = ci->ci_curlwp;
#else
l = curlwp;
#endif
/*
* Initialize the FPU state to clear any exceptions. If someone else
@ -276,7 +258,7 @@ fpudna(struct cpu_info *ci)
cw = l->l_addr->u_pcb.pcb_savefpu.fp_fxsave.fx_fcw;
fldcw(&cw);
mxcsr = l->l_addr->u_pcb.pcb_savefpu.fp_fxsave.fx_mxcsr;
ldmxcsr(&mxcsr);
x86_ldmxcsr(&mxcsr);
l->l_md.md_flags |= MDP_USEDFPU;
} else {
/*
@ -298,7 +280,7 @@ fpudna(struct cpu_info *ci)
* the x87 stack, but we don't care since we're about to call
* fxrstor() anyway.
*/
__asm __volatile("ffree %%st(7)\n\tfld %0" : : "m" (zero));
fldummy(&zero);
fxrstor(&l->l_addr->u_pcb.pcb_savefpu);
}
}
@ -353,37 +335,25 @@ fpusave_lwp(struct lwp *l, int save)
KDASSERT(l->l_addr != NULL);
oci = l->l_addr->u_pcb.pcb_fpcpu;
if (oci == NULL)
return;
#if defined(MULTIPROCESSOR)
if (oci == ci) {
int s = splipi();
fpusave_cpu(ci, save);
splx(s);
} else {
#ifdef DIAGNOSTIC
} else if (oci != NULL) {
#ifdef MULTIPROCESSOR
int spincount;
#endif
x86_send_ipi(oci,
save ? X86_IPI_SYNCH_FPU : X86_IPI_FLUSH_FPU);
#ifdef DIAGNOSTIC
spincount = 0;
#endif
while (l->l_addr->u_pcb.pcb_fpcpu != NULL) {
#ifdef DIAGNOSTIC
x86_pause();
spincount++;
if (spincount > 10000000) {
panic("fp_save ipi didn't");
}
#endif
__insn_barrier();
}
}
#else
KASSERT(ci->ci_fpcurlwp == l);
fpusave_cpu(ci, save);
#endif
}
}

9
sys/arch/amd64/amd64/genassym.cf
View File

@ -1,4 +1,4 @@
# $NetBSD: genassym.cf,v 1.11 2007/09/26 00:14:53 ad Exp $
# $NetBSD: genassym.cf,v 1.12 2007/09/26 19:48:35 ad Exp $
#
# Copyright (c) 1998 The NetBSD Foundation, Inc.
@ -106,6 +106,7 @@ include <machine/pmap.h>
include <machine/vmparam.h>
include <machine/intr.h>
include <machine/types.h>
include <machine/cpufunc.h>
if defined(COMPAT_NETBSD32)
include <machine/netbsd32_machdep.h>
@ -132,6 +133,8 @@ include <machine/i82093reg.h>
include <machine/i82093var.h>
endif
include <x86/busdefs.h>
define LSRUN LSRUN
define LSONPROC LSONPROC
@ -295,3 +298,7 @@ define MB_HEAD offsetof(struct pmap_mbox, mb_head)
define MB_TAIL offsetof(struct pmap_mbox, mb_tail)
define EV_COUNT offsetof(struct evcnt, ev_count)
define OPTERON_MSR_PASSCODE OPTERON_MSR_PASSCODE
define X86_BUS_SPACE_IO X86_BUS_SPACE_IO

36
sys/arch/amd64/amd64/identcpu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: identcpu.c,v 1.24 2007/08/29 23:38:02 ad Exp $ */
/* $NetBSD: identcpu.c,v 1.25 2007/09/26 19:48:35 ad Exp $ */
/*
* Copyright (c) 2003 Wasabi Systems, Inc.
@ -36,7 +36,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.24 2007/08/29 23:38:02 ad Exp $");
__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.25 2007/09/26 19:48:35 ad Exp $");
#include "opt_enhanced_speedstep.h"
#include "opt_intel_odcm.h"
@ -58,26 +58,32 @@ void
identifycpu(struct cpu_info *ci)
{
u_int64_t last_tsc;
u_int32_t dummy, val;
u_int32_t val;
char buf[512];
u_int32_t brand[12];
u_int32_t brand[12], descs[4];
int vendor;
const char *feature_str[3];
CPUID(0, ci->ci_cpuid_level,
ci->ci_vendor[0],
ci->ci_vendor[2],
ci->ci_vendor[1]);
x86_cpuid(0, descs);
ci->ci_cpuid_level = descs[0];
ci->ci_vendor[0] = descs[1];
ci->ci_vendor[2] = descs[2];
ci->ci_vendor[1] = descs[3];
ci->ci_vendor[3] = 0;
CPUID(1, ci->ci_signature, val,
ci->ci_feature2_flags, ci->ci_feature_flags);
CPUID(0x80000001, dummy, dummy, dummy, val);
ci->ci_feature_flags |= val;
x86_cpuid(1, descs);
ci->ci_signature = descs[0];
val = descs[1];
ci->ci_feature2_flags = descs[2];
ci->ci_feature_flags = descs[3];
CPUID(0x80000002, brand[0], brand[1], brand[2], brand[3]);
CPUID(0x80000003, brand[4], brand[5], brand[6], brand[7]);
CPUID(0x80000004, brand[8], brand[9], brand[10], brand[11]);
x86_cpuid(0x80000001, descs);
ci->ci_feature_flags |= descs[3];
x86_cpuid(0x80000002, brand);
x86_cpuid(0x80000003, brand + 4);
x86_cpuid(0x80000004, brand + 8);
strcpy(cpu_model, (char *)brand);

8
sys/arch/amd64/amd64/ipifuncs.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: ipifuncs.c,v 1.10 2007/08/29 23:38:02 ad Exp $ */
/* $NetBSD: ipifuncs.c,v 1.11 2007/09/26 19:48:35 ad Exp $ */
/*-
* Copyright (c) 2000 The NetBSD Foundation, Inc.
@ -40,7 +40,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: ipifuncs.c,v 1.10 2007/08/29 23:38:02 ad Exp $");
__KERNEL_RCSID(0, "$NetBSD: ipifuncs.c,v 1.11 2007/09/26 19:48:35 ad Exp $");
/*
* Interprocessor interrupt handlers.
@ -94,10 +94,10 @@ void (*ipifunc[X86_NIPI])(struct cpu_info *) =
void
x86_64_ipi_halt(struct cpu_info *ci)
{
disable_intr();
x86_disable_intr();
for(;;) {
__asm volatile("hlt");
x86_hlt();
}
}

36
sys/arch/amd64/amd64/locore.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.S,v 1.26 2007/08/29 23:38:02 ad Exp $ */
/* $NetBSD: locore.S,v 1.27 2007/09/26 19:48:35 ad Exp $ */
/*
* Copyright-o-rama!
@ -635,40 +635,6 @@ longmode_hi:
/*****************************************************************************/
/*
* void lgdt(struct region_descriptor *rdp);
*
* Change the global descriptor table.
*/
NENTRY(lgdt)
/* Reload the descriptor table. */
movq %rdi,%rax
lgdt (%rax)
/* Flush the prefetch q. */
jmp 1f
nop
1: /* Reload "stale" selectors. */
movl $GSEL(GDATA_SEL, SEL_KPL),%eax
movl %eax,%ds
movl %eax,%es
movl %eax,%ss
/* Reload code selector by doing intersegment return. */
popq %rax
pushq $GSEL(GCODE_SEL, SEL_KPL)
pushq %rax
lretq
/*
* void x86_flush()
*
* Flush instruction pipelines by doing an intersegment (far) return.
*/
NENTRY(x86_flush)
popq %rax
pushq $GSEL(GCODE_SEL, SEL_KPL)
pushq %rax
lretq
/*
* int setjmp(label_t *)
*

12
sys/arch/amd64/amd64/machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.61 2007/08/29 23:38:02 ad Exp $ */
/* $NetBSD: machdep.c,v 1.62 2007/09/26 19:48:35 ad Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998, 2000, 2006, 2007
@ -73,7 +73,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.61 2007/08/29 23:38:02 ad Exp $");
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.62 2007/09/26 19:48:35 ad Exp $");
#include "opt_user_ldt.h"
#include "opt_ddb.h"
@ -1504,22 +1504,20 @@ init_x86_64(paddr_t first_avail)
softintr_init();
splraise(IPL_IPI);
enable_intr();
x86_enable_intr();
x86_init();
/* Make sure maxproc is sane */
if (maxproc > cpu_maxproc())
maxproc = cpu_maxproc();
curlwp = &lwp0;
}
void
cpu_reset(void)
{
disable_intr();
x86_disable_intr();
/*
* The keyboard controller has 4 random output pins, one of which is
@ -1540,7 +1538,7 @@ cpu_reset(void)
VM_PROT_READ|VM_PROT_WRITE);
memset((void *)idt, 0, NIDT * sizeof(idt[0]));
__asm volatile("divl %0,%1" : : "q" (0), "a" (0));
breakpoint();
#if 0
/*

4
sys/arch/amd64/conf/files.amd64
View File

@ -1,4 +1,4 @@
# $NetBSD: files.amd64,v 1.43 2007/08/29 23:38:03 ad Exp $
# $NetBSD: files.amd64,v 1.44 2007/09/26 19:48:40 ad Exp $
#
# new style config file for amd64 architecture
#
@ -27,6 +27,8 @@ defflag VM86
defflag eisa.h EISA
file arch/amd64/amd64/autoconf.c
file arch/amd64/amd64/busfunc.S
file arch/amd64/amd64/cpufunc.S
file arch/amd64/amd64/db_disasm.c ddb
file arch/amd64/amd64/db_interface.c ddb
file arch/amd64/amd64/db_memrw.c ddb | kgdb

61
sys/arch/amd64/include/cpu.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.h,v 1.26 2007/09/25 17:08:09 ad Exp $ */
/* $NetBSD: cpu.h,v 1.27 2007/09/26 19:48:40 ad Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
@ -146,17 +146,45 @@ extern struct cpu_info *cpu_info_list;
#define CPU_INFO_FOREACH(cii, ci) cii = 0, ci = cpu_info_list; \
ci != NULL; ci = ci->ci_next
#if defined(MULTIPROCESSOR)
#define X86_MAXPROCS 32 /* bitmask; can be bumped to 64 */
#define CPU_STARTUP(_ci) ((_ci)->ci_func->start(_ci))
#define CPU_STOP(_ci) ((_ci)->ci_func->stop(_ci))
#define CPU_START_CLEANUP(_ci) ((_ci)->ci_func->cleanup(_ci))
#define curcpu() ({struct cpu_info *__ci; \
__asm volatile("movq %%gs:8,%0" : "=r" (__ci)); \
__ci;})
#if defined(__GNUC__) && defined(_KERNEL)
static struct cpu_info *x86_curcpu(void);
static lwp_t *x86_curlwp(void);
__inline static struct cpu_info * __attribute__((__unused__))
x86_curcpu(void)
{
struct cpu_info *ci;
__asm volatile("movq %%gs:%1, %0" :
"=r" (ci) :
"m"
(*(struct cpu_info * const *)offsetof(struct cpu_info, ci_self)));
return ci;
}
__inline static lwp_t * __attribute__((__unused__))
x86_curlwp(void)
{
lwp_t *l;
__asm volatile("movq %%gs:%1, %0" :
"=r" (l) :
"m"
(*(struct cpu_info * const *)offsetof(struct cpu_info, ci_curlwp)));
return l;
}
#else /* __GNUC__ && _KERNEL */
/* For non-GCC and LKMs */
struct cpu_info *x86_curcpu(void);
lwp_t *x86_curlwp(void);
#endif /* __GNUC__ && _KERNEL */
#define cpu_number() (curcpu()->ci_cpuid)
#define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY)
@ -166,29 +194,12 @@ extern struct cpu_info *cpu_info[X86_MAXPROCS];
void cpu_boot_secondary_processors(void);
void cpu_init_idle_lwps(void);
#else /* !MULTIPROCESSOR */
#define X86_MAXPROCS 1
extern struct cpu_info cpu_info_primary;
#define curcpu() (&cpu_info_primary)
/*
* definitions of cpu-dependent requirements
* referenced in generic code
*/
#define cpu_number() 0
#define CPU_IS_PRIMARY(ci) 1
#endif
#define aston(l) ((l)->l_md.md_astpending = 1)
extern u_int32_t cpus_attached;
#define curlwp curcpu()->ci_curlwp
#define curcpu() x86_curcpu()
#define curlwp x86_curlwp()
#define curpcb (&curlwp->l_addr->u_pcb)
/*

342
sys/arch/amd64/include/cpufunc.h
View File

@ -1,341 +1,3 @@
/* $NetBSD: cpufunc.h,v 1.17 2007/05/21 08:10:39 fvdl Exp $ */
/* $NetBSD: cpufunc.h,v 1.18 2007/09/26 19:48:40 ad Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Charles M. Hannum.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _AMD64_CPUFUNC_H_
#define _AMD64_CPUFUNC_H_
/*
* Functions to provide access to i386-specific instructions.
*/
#include <sys/cdefs.h>
#include <sys/types.h>
#include <machine/segments.h>
#include <machine/specialreg.h>
#ifdef _KERNEL
void x86_pause(void);
#else
static __inline void
x86_pause(void)
{
__asm volatile("pause");
}
#endif
/*
* XXX if lfence isn't available...
*
* memory clobber to avoid compiler reordering.
*/
static __inline void
x86_lfence(void)
{
__asm volatile("lfence" : : : "memory");
}
static __inline void
x86_sfence(void)
{
__asm volatile("sfence" : : : "memory");
}
static __inline void
x86_mfence(void)
{
__asm volatile("mfence" : : : "memory");
}
#ifdef _KERNEL
void x86_flush(void);
void x86_patch(void);
extern int cpu_feature;
static __inline void
invlpg(u_int64_t addr)
{
__asm volatile("invlpg (%0)" : : "r" (addr) : "memory");
}
static __inline void
lidt(struct region_descriptor *region)
{
__asm volatile("lidt %0" : : "m" (*region));
}
static __inline void
lldt(u_short sel)
{
__asm volatile("lldt %0" : : "r" (sel));
}
static __inline void
ltr(u_short sel)
{
__asm volatile("ltr %0" : : "r" (sel));
}
static __inline void
lcr8(u_int val)
{
u_int64_t val64 = val;
__asm volatile("movq %0,%%cr8" : : "r" (val64));
}
/*
* Upper 32 bits are reserved anyway, so just keep this 32bits.
*/
static __inline void
lcr0(u_int val)
{
u_int64_t val64 = val;
__asm volatile("movq %0,%%cr0" : : "r" (val64));
}
static __inline u_int
rcr0(void)
{
u_int64_t val64;
u_int val;
__asm volatile("movq %%cr0,%0" : "=r" (val64));
val = val64;
return val;
}
static __inline u_int64_t
rcr2(void)
{
u_int64_t val;
__asm volatile("movq %%cr2,%0" : "=r" (val));
return val;
}
static __inline void
lcr3(u_int64_t val)
{
__asm volatile("movq %0,%%cr3" : : "r" (val));
}
static __inline u_int64_t
rcr3(void)
{
u_int64_t val;
__asm volatile("movq %%cr3,%0" : "=r" (val));
return val;
}
/*
* Same as for cr0. Don't touch upper 32 bits.
*/
static __inline void
lcr4(u_int val)
{
u_int64_t val64 = val;
__asm volatile("movq %0,%%cr4" : : "r" (val64));
}
static __inline u_int
rcr4(void)
{
u_int val;
u_int64_t val64;
__asm volatile("movq %%cr4,%0" : "=r" (val64));
val = val64;
return val;
}
static __inline void
tlbflush(void)
{
u_int64_t val;
__asm volatile("movq %%cr3,%0" : "=r" (val));
__asm volatile("movq %0,%%cr3" : : "r" (val));
}
static __inline void
tlbflushg(void)
{
/*
* Big hammer: flush all TLB entries, including ones from PTE's
* with the G bit set. This should only be necessary if TLB
* shootdown falls far behind.
*
* Intel Architecture Software Developer's Manual, Volume 3,
* System Programming, section 9.10, "Invalidating the
* Translation Lookaside Buffers (TLBS)":
* "The following operations invalidate all TLB entries, irrespective
* of the setting of the G flag:
* ...
* "(P6 family processors only): Writing to control register CR4 to
* modify the PSE, PGE, or PAE flag."
*
* (the alternatives not quoted above are not an option here.)
*
* If PGE is not in use, we reload CR3 for the benefit of
* pre-P6-family processors.
*/
if (cpu_feature & CPUID_PGE) {
u_int cr4 = rcr4();
lcr4(cr4 & ~CR4_PGE);
lcr4(cr4);
} else
tlbflush();
}
#ifdef notyet
void setidt __P((int idx, /*XXX*/void *func, int typ, int dpl));
#endif
/* XXXX ought to be in psl.h with spl() functions */
static __inline void
disable_intr(void)
{
__asm volatile("cli");
}
static __inline void
enable_intr(void)
{
__asm volatile("sti");
}
static __inline u_long
read_rflags(void)
{
u_long ef;
__asm volatile("pushfq; popq %0" : "=r" (ef));
return (ef);
}
static __inline void
write_rflags(u_long ef)
{
__asm volatile("pushq %0; popfq" : : "r" (ef));
}
static __inline u_int64_t
rdmsr(u_int msr)
{
uint32_t hi, lo;
__asm volatile("rdmsr" : "=d" (hi), "=a" (lo) : "c" (msr));
return (((uint64_t)hi << 32) | (uint64_t) lo);
}
static __inline void
wrmsr(u_int msr, u_int64_t newval)
{
__asm volatile("wrmsr" :
: "a" (newval & 0xffffffff), "d" (newval >> 32), "c" (msr));
}
/*
* Some of the undocumented AMD64 MSRs need a 'passcode' to access.
*
* See LinuxBIOSv2: src/cpu/amd/model_fxx/model_fxx_init.c
*/
#define OPTERON_MSR_PASSCODE 0x9c5a203a
static __inline u_int64_t
rdmsr_locked(u_int msr, u_int code)
{
uint32_t hi, lo;
__asm volatile("rdmsr"
: "=d" (hi), "=a" (lo)
: "c" (msr), "D" (code));
return (((uint64_t)hi << 32) | (uint64_t) lo);
}
static __inline void
wrmsr_locked(u_int msr, u_int code, u_int64_t newval)
{
__asm volatile("wrmsr"
:
: "a" (newval & 0xffffffff), "d" (newval >> 32), "c" (msr),
"D" (code));
}
static __inline void
wbinvd(void)
{
__asm volatile("wbinvd");
}
static __inline u_int64_t
rdtsc(void)
{
uint32_t hi, lo;
__asm volatile("rdtsc" : "=d" (hi), "=a" (lo));
return (((uint64_t)hi << 32) | (uint64_t) lo);
}
static __inline u_int64_t
rdpmc(u_int pmc)
{
uint32_t hi, lo;
__asm volatile("rdpmc" : "=d" (hi), "=a" (lo) : "c" (pmc));
return (((uint64_t)hi << 32) | (uint64_t) lo);
}
/* Break into DDB/KGDB. */
static __inline void
breakpoint(void)
{
__asm volatile("int $3");
}
#define read_psl() read_rflags()
#define write_psl(x) write_rflags(x)
#endif /* _KERNEL */
#endif /* !_AMD64_CPUFUNC_H_ */
#include <x86/cpufunc.h>

18
sys/arch/i386/acpi/acpi_wakeup.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: acpi_wakeup.c,v 1.38 2007/08/02 11:23:35 jmcneill Exp $ */
/* $NetBSD: acpi_wakeup.c,v 1.39 2007/09/26 19:48:40 ad Exp $ */
/*-
* Copyright (c) 2002 The NetBSD Foundation, Inc.
@ -37,7 +37,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: acpi_wakeup.c,v 1.38 2007/08/02 11:23:35 jmcneill Exp $");
__KERNEL_RCSID(0, "$NetBSD: acpi_wakeup.c,v 1.39 2007/09/26 19:48:40 ad Exp $");
/*-
* Copyright (c) 2001 Takanori Watanabe <takawata@jp.freebsd.org>
@ -157,8 +157,8 @@ enter_s4_with_bios(void)
AcpiSetRegister(ACPI_BITREG_WAKE_STATUS, 1, ACPI_MTX_LOCK);
ef = read_eflags();
disable_intr();
ef = x86_read_psl();
x86_disable_intr();
AcpiHwDisableAllGpes();
AcpiHwEnableAllWakeupGpes();
@ -183,7 +183,7 @@ enter_s4_with_bios(void)
AcpiHwDisableAllGpes();
AcpiHwEnableAllRuntimeGpes();
write_eflags(ef);
x86_write_psl(ef);
return (AE_OK);
}
@ -342,7 +342,7 @@ acpi_md_sleep(int state)
AcpiSetFirmwareWakingVector(phys_wakeup);
ef = read_eflags();
ef = x86_read_psl();
/* Create identity mapping */
if ((p = curproc) == NULL)
@ -360,7 +360,7 @@ acpi_md_sleep(int state)
cr3 = rcr3();
ret_addr = 0;
disable_intr();
x86_disable_intr();
if (acpi_savecpu()) {
/* Execute Sleep */
@ -458,7 +458,7 @@ acpi_md_sleep(int state)
}
out:
enable_intr();
x86_enable_intr();
lcr3(cr3);
if (pm != pmap_kernel()) {
@ -472,7 +472,7 @@ out:
pmap_update(pm);
}
write_eflags(ef);
x86_write_psl(ef);
return (ret);
#undef WAKECODE_FIXUP

6
sys/arch/i386/bios/vesafb.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: vesafb.c,v 1.22 2007/03/24 00:23:05 reinoud Exp $ */
/* $NetBSD: vesafb.c,v 1.23 2007/09/26 19:48:40 ad Exp $ */
/*-
* Copyright (c) 2006 Jared D. McNeill <jmcneill@invisible.ca>
@ -37,7 +37,7 @@
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: vesafb.c,v 1.22 2007/03/24 00:23:05 reinoud Exp $");
__KERNEL_RCSID(0, "$NetBSD: vesafb.c,v 1.23 2007/09/26 19:48:40 ad Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -451,7 +451,7 @@ vesafb_mmap(void *v, void *vs, off_t offset, int prot)
/* XXX */
if (offset >= 0 && offset <
sc->sc_mi.YResolution*sc->sc_mi.BytesPerScanLine) {
pa = x86_memio_mmap(X86_BUS_SPACE_MEM, sc->sc_mi.PhysBasePtr,
pa = bus_space_mmap(X86_BUS_SPACE_MEM, sc->sc_mi.PhysBasePtr,
offset, prot, BUS_SPACE_MAP_LINEAR);
return pa;
}

5
sys/arch/i386/conf/files.i386
View File

@ -1,4 +1,4 @@
# $NetBSD: files.i386,v 1.314 2007/08/29 23:38:03 ad Exp $
# $NetBSD: files.i386,v 1.315 2007/09/26 19:48:40 ad Exp $
#
# new style config file for i386 architecture
#
@ -67,6 +67,8 @@ file arch/i386/i386/multiboot.c multiboot
defflag POWERNOW_K7
file arch/i386/i386/autoconf.c
file arch/i386/i386/busfunc.S
file arch/i386/i386/cpufunc.S
file arch/i386/i386/db_dbgreg.S ddb | kstack_check_dr0
file arch/i386/i386/db_disasm.c ddb
file arch/i386/i386/db_interface.c ddb
@ -74,6 +76,7 @@ file arch/i386/i386/db_memrw.c ddb | kgdb
file arch/i386/i386/db_trace.c ddb
file kern/subr_disk_mbr.c disk
file arch/i386/i386/gdt.c
file arch/i386/i386/i386func.S
file arch/x86/x86/idle_machdep.c
file arch/i386/i386/in_cksum.S inet | inet6
file arch/i386/i386/ipkdb_glue.c ipkdb

506
sys/arch/i386/i386/busfunc.S Normal file
View File

@ -0,0 +1,506 @@
/* $NetBSD: busfunc.S,v 1.1 2007/09/26 19:48:35 ad Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Andrew Doran.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <machine/asm.h>
#include "assym.h"
/* XXX */
#undef _ALIGN_TEXT
#define _ALIGN_TEXT .align 16
/*
* uint8_t bus_space_read_1(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset);
*/
NENTRY(bus_space_read_1)
movl 8(%esp), %edx
addl 12(%esp), %edx
cmpl $X86_BUS_SPACE_IO, 4(%esp)
je 1f
movzbl (%edx), %eax
ret
1:
xorl %eax, %eax
inb %dx, %al
ret
/*
* uint16_t bus_space_read_2(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset);
*/
NENTRY(bus_space_read_2)
movl 8(%esp), %edx
addl 12(%esp), %edx
cmpl $X86_BUS_SPACE_IO, 4(%esp)
je 1f
movzwl (%edx), %eax
ret
1:
xorl %eax, %eax
inw %dx, %ax
ret
/*
* uint32_t bus_space_read_4(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset);
*/
NENTRY(bus_space_read_4)
movl 8(%esp), %edx
addl 12(%esp), %edx
cmpl $X86_BUS_SPACE_IO, 4(%esp)
je 1f
movl (%edx), %eax
ret
1:
inl %dx, %eax
ret
STRONG_ALIAS(bus_space_read_stream_1,bus_space_read_1)
STRONG_ALIAS(bus_space_read_stream_2,bus_space_read_2)
STRONG_ALIAS(bus_space_read_stream_4,bus_space_read_4)
/*
* void bus_space_write_1(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, uint8_t value);
*/
NENTRY(bus_space_write_1)
movl 8(%esp), %edx
addl 12(%esp), %edx
cmpl $X86_BUS_SPACE_IO, 4(%esp)
movl 16(%esp), %eax
je 1f
movb %al, (%edx)
ret
1:
outb %al, %dx
ret
/*
* void bus_space_write_2(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, uint16_t value);
*/
NENTRY(bus_space_write_2)
movl 8(%esp), %edx
addl 12(%esp), %edx
cmpl $X86_BUS_SPACE_IO, 4(%esp)
movl 16(%esp), %eax
je 1f
movw %ax, (%edx)
ret
1:
outw %ax, %dx
ret
/*
* void bus_space_write_4(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, uint32_t value);
*/
NENTRY(bus_space_write_4)
movl 8(%esp), %edx
addl 12(%esp), %edx
cmpl $X86_BUS_SPACE_IO, 4(%esp)
movl 16(%esp), %eax
je 1f
movl %eax, (%edx)
ret
1:
outl %eax, %dx
ret
STRONG_ALIAS(bus_space_write_stream_1,bus_space_write_1)
STRONG_ALIAS(bus_space_write_stream_2,bus_space_write_2)
STRONG_ALIAS(bus_space_write_stream_4,bus_space_write_4)
/*
* void bus_space_read_multi_1(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, uint8_t *addr, size_t count);
*/
NENTRY(bus_space_read_multi_1)
pushl %edi
movl 12(%esp), %edx
addl 16(%esp), %edx
cmpl $X86_BUS_SPACE_IO, 8(%esp)
movl 20(%esp), %edi
movl 24(%esp), %ecx
jne 1f
cld
rep
insb (%dx), %es:(%edi)
popl %edi
ret
.align 16
1:
movb (%edx), %al
decl %ecx
movb %al, (%edi)
leal 1(%edi), %edi
jnz 1b
popl %edi
ret
/*
* void bus_space_read_multi_2(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, uint16_t *addr, size_t count);
*/
NENTRY(bus_space_read_multi_2)
pushl %edi
movl 12(%esp), %edx
addl 16(%esp), %edx
cmpl $X86_BUS_SPACE_IO, 8(%esp)
movl 20(%esp), %edi
movl 24(%esp), %ecx
jne 1f
cld
rep
insw (%dx), %es:(%edi)
popl %edi
ret
.align 16
1:
movw (%edx), %ax
decl %ecx
movw %ax, (%edi)
leal 2(%edi), %edi
jnz 1b
popl %edi
ret
/*
* void bus_space_read_multi_4(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, uint32_t *addr, size_t count);
*/
NENTRY(bus_space_read_multi_4)
pushl %edi
movl 12(%esp), %edx
addl 16(%esp), %edx
cmpl $X86_BUS_SPACE_IO, 8(%esp)
movl 20(%esp), %edi
movl 24(%esp), %ecx
jne 1f
cld
rep
insl (%dx), %es:(%edi)
popl %edi
ret
.align 16
1:
movl (%edx), %eax
decl %ecx
movl %eax, (%edi)
leal 4(%edi), %edi
jnz 1b
popl %edi
ret
STRONG_ALIAS(bus_space_read_multi_stream_1,bus_space_read_multi_1)
STRONG_ALIAS(bus_space_read_multi_stream_2,bus_space_read_multi_2)
STRONG_ALIAS(bus_space_read_multi_stream_4,bus_space_read_multi_4)
/*
* void bus_space_write_multi_1(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, const uint8_t *addr, size_t count);
*/
NENTRY(bus_space_write_multi_1)
pushl %esi
movl 12(%esp), %edx
addl 16(%esp), %edx
cmpl $X86_BUS_SPACE_IO, 8(%esp)
movl 20(%esp), %esi
movl 24(%esp), %ecx
jne 1f
cld
rep
outsb %ds:(%esi), (%dx)
popl %esi
ret
.align 16
1:
movb (%esi), %al
decl %ecx
movb %al, (%edx)
leal 1(%esi), %esi
jnz 1b
popl %esi
ret
/*
* void bus_space_write_multi_2(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, const uint16_t *addr, size_t count);
*/
NENTRY(bus_space_write_multi_2)
pushl %esi
movl 12(%esp), %edx
addl 16(%esp), %edx
cmpl $X86_BUS_SPACE_IO, 8(%esp)
movl 20(%esp), %esi
movl 24(%esp), %ecx
jne 1f
cld
rep
outsw %ds:(%esi),(%dx)
popl %esi
ret
.align 16
1:
movw (%esi), %ax
decl %ecx
movw %ax, (%edx)
leal 2(%esi), %esi
jnz 1b
popl %esi
ret
/*
* void bus_space_write_multi_4(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, const uint32_t *addr, size_t count);
*/
NENTRY(bus_space_write_multi_4)
pushl %esi
movl 12(%esp), %edx
addl 16(%esp), %edx
cmpl $X86_BUS_SPACE_IO, 8(%esp)
movl 20(%esp), %esi
movl 24(%esp), %ecx
jne 1f
cld
rep
outsl %ds:(%esi),(%dx)
popl %esi
ret
.align 16
1:
movl (%esi), %eax
decl %ecx
movl %eax, (%edx)
leal 4(%esi), %esi
jnz 1b
popl %esi
ret
STRONG_ALIAS(bus_space_write_multi_stream_1,bus_space_write_multi_1)
STRONG_ALIAS(bus_space_write_multi_stream_2,bus_space_write_multi_2)
STRONG_ALIAS(bus_space_write_multi_stream_4,bus_space_write_multi_4)
/*
* void bus_space_read_region_1(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, uint8_t *addr, size_t count);
*/
NENTRY(bus_space_read_region_1)
pushl %edi
movl 12(%esp), %edx
addl 16(%esp), %edx
cmpl $X86_BUS_SPACE_IO, 8(%esp)
movl 20(%esp), %edi
movl 24(%esp), %ecx
je 2f
1:
xchgl %edx, %esi
cld
rep
movsb %ds:(%esi), %es:(%edi)
movl %edx, %esi
popl %edi
ret
2:
inb %dx, %al
incl %edx
decl %ecx
movb %al, (%edi)
leal 1(%edi), %edi
jnz 2b
popl %edi
ret
/*
* void bus_space_read_region_2(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, uint16_t *addr, size_t count);
*/
NENTRY(bus_space_read_region_2)
pushl %edi
movl 12(%esp), %edx
addl 16(%esp), %edx
cmpl $X86_BUS_SPACE_IO, 8(%esp)
movl 20(%esp), %edi
movl 24(%esp), %ecx
je 2f
1:
xchgl %edx, %esi
cld
rep
movsw %ds:(%esi), %es:(%edi)
movl %edx, %esi
popl %edi
ret
2:
inw %dx, %ax
addl $2, %edx
decl %ecx
movw %ax, (%edi)
leal 2(%edi), %edi
jnz 2b
popl %edi
ret
/*
* void bus_space_read_region_4(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, uint32_t *addr, size_t count);
*/
NENTRY(bus_space_read_region_4)
pushl %edi
movl 12(%esp), %edx
addl 16(%esp), %edx
cmpl $X86_BUS_SPACE_IO, 8(%esp)
movl 20(%esp), %edi
movl 24(%esp), %ecx
je 2f
1:
xchgl %edx, %esi
cld
rep
movsl %ds:(%esi), %es:(%edi)
movl %edx, %esi
popl %edi
ret
2:
inl %dx, %eax
addl $4, %edx
decl %ecx
movl %eax, (%edi)
leal 4(%edi), %edi
jnz 2b
popl %edi
ret
STRONG_ALIAS(bus_space_read_region_stream_1,bus_space_read_region_1)
STRONG_ALIAS(bus_space_read_region_stream_2,bus_space_read_region_2)
STRONG_ALIAS(bus_space_read_region_stream_4,bus_space_read_region_4)
/*
* void bus_space_write_region_1(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, const uint8_t *addr, size_t count);
*/
NENTRY(bus_space_write_region_1)
pushl %esi
movl 12(%esp), %edx
addl 16(%esp), %edx
cmpl $X86_BUS_SPACE_IO, 8(%esp)
movl 20(%esp), %esi
movl 24(%esp), %ecx
je 2f
1:
xchgl %edx, %edi
cld
rep
movsb %ds:(%esi), %es:(%edi)
movl %edx, %edi
popl %esi
ret
2:
movb (%esi), %al
incl %esi
decl %ecx
outb %al, %dx
leal 1(%edx), %edx
jnz 2b
popl %esi
ret
/*
* void bus_space_write_region_2(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, const uint16_t *addr, size_t count);
*/
NENTRY(bus_space_write_region_2)
pushl %esi
movl 12(%esp), %edx
addl 16(%esp), %edx
cmpl $X86_BUS_SPACE_IO, 8(%esp)
movl 20(%esp), %esi
movl 24(%esp), %ecx
je 2f
1:
xchgl %edx, %edi
cld
rep
movsw %ds:(%esi), %es:(%edi)
movl %edx, %edi
popl %esi
ret
2:
movw (%esi), %ax
addl $2, %esi
decl %ecx
outw %ax, %dx
leal 2(%edx), %edx
jnz 2b
popl %esi
ret
/*
* void bus_space_write_region_4(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, const uint32_t *addr, size_t count);
*/
NENTRY(bus_space_write_region_4)
pushl %esi
movl 12(%esp), %edx
addl 16(%esp), %edx
cmpl $X86_BUS_SPACE_IO, 8(%esp)
movl 20(%esp), %esi
movl 24(%esp), %ecx
je 2f
1:
xchgl %edx, %edi
cld
rep
movsl %ds:(%esi), %es:(%edi)
movl %edx, %edi
popl %esi
ret
2:
movl (%esi), %eax
addl $4, %esi
decl %ecx
outl %eax, %dx
leal 4(%edx), %edx
jnz 2b
popl %esi
ret
STRONG_ALIAS(bus_space_write_region_stream_1,bus_space_write_region_1)
STRONG_ALIAS(bus_space_write_region_stream_2,bus_space_write_region_2)
STRONG_ALIAS(bus_space_write_region_stream_4,bus_space_write_region_4)

437
sys/arch/i386/i386/cpufunc.S Normal file
View File

@ -0,0 +1,437 @@
/* $NetBSD: cpufunc.S,v 1.1 2007/09/26 19:48:36 ad Exp $ */
/*-
* Copyright (c) 1998, 2007 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Charles M. Hannum, and by Andrew Doran.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Functions to provide access to i386-specific instructions.
*
* These are shared with NetBSD/xen.
*/
#include "opt_xen.h"
#include <machine/asm.h>
#include <machine/specialreg.h>
#include <machine/segments.h>
#include "assym.h"
/* Small and slow, so align less. */
#undef _ALIGN_TEXT
#define _ALIGN_TEXT .align 8
NENTRY(x86_lfence)
lock
addl $0, -4(%esp)
ret
NENTRY(x86_sfence)
lock
addl $0, -4(%esp)
ret
NENTRY(x86_mfence)
lock
addl $0, -4(%esp)
ret
NENTRY(lidt)
movl 4(%esp), %eax
lidt (%eax)
ret
NENTRY(rcr3)
movl %cr3, %eax
ret
NENTRY(lcr4)
movl 4(%esp), %eax
movl %eax, %cr4
ret
NENTRY(rcr4)
movl %cr4, %eax
ret
NENTRY(x86_read_flags)
pushfl
popl %eax
ret
NENTRY(x86_write_flags)
movl 4(%esp), %eax
pushl %eax
popfl
ret
#ifndef XEN
STRONG_ALIAS(x86_write_psl,x86_write_flags)
STRONG_ALIAS(x86_read_psl,x86_read_flags)
#endif /* XEN */
NENTRY(rdmsr)
movl 4(%esp), %ecx
rdmsr
ret
NENTRY(wrmsr)
movl 4(%esp), %ecx
movl 8(%esp), %eax
movl 12(%esp), %edx
wrmsr
ret
NENTRY(rdmsr_locked)
movl 4(%esp), %ecx
pushl %edi
movl $OPTERON_MSR_PASSCODE, %edi
rdmsr
popl %edi
ret
NENTRY(wrmsr_locked)
movl 4(%esp), %ecx
movl 8(%esp), %eax
movl 12(%esp), %edx
pushl %edi
movl $OPTERON_MSR_PASSCODE, %edi
wrmsr
popl %edi
ret
NENTRY(rdtsc)
rdtsc
ret
NENTRY(rdpmc)
movl 4(%esp), %ecx
rdpmc
ret
NENTRY(breakpoint)
int $0x03 /* paranoid, not 'int3' */
ret
NENTRY(x86_atomic_testset_ul)
movl 4(%esp), %ecx
movl 8(%esp), %eax
xchgl %eax, (%ecx)
ret
NENTRY(x86_atomic_testset_i)
movl 4(%esp), %ecx
movl 8(%esp), %eax
xchgl %eax, (%ecx)
ret
NENTRY(x86_atomic_testset_b)
movl 4(%esp), %ecx
movl 8(%esp), %eax
xchgb %al, (%ecx)
andl $0xff, %eax
ret
NENTRY(x86_atomic_setbits_l)
movl 4(%esp), %ecx
movl 8(%esp), %eax
lock
orl %eax, (%ecx)
ret
NENTRY(x86_atomic_clearbits_l)
movl 4(%esp), %ecx
movl 8(%esp), %eax
notl %eax
lock
andl %eax, (%ecx)
ret
NENTRY(x86_curcpu)
movl %fs:(CPU_INFO_SELF), %eax
ret
NENTRY(x86_curlwp)
movl %fs:(CPU_INFO_CURLWP), %eax
ret
NENTRY(__byte_swap_u32_variable)
movl 4(%esp), %eax
bswapl %eax
ret
NENTRY(__byte_swap_u16_variable)
movl 4(%esp), %eax
xchgb %al, %ah
ret
/*
* void x86_flush()
*
* Flush instruction pipelines by doing an intersegment (far) return.
*/
NENTRY(x86_flush)
popl %eax
pushl $GSEL(GCODE_SEL, SEL_KPL)
pushl %eax
lret
/* Waits - set up stack frame. */
NENTRY(x86_hlt)
pushl %ebp
movl %esp, %ebp
hlt
leave
ret
/* Waits - set up stack frame. */
NENTRY(x86_stihlt)
pushl %ebp
movl %esp, %ebp
sti
hlt
leave
ret
NENTRY(x86_monitor)
movl 4(%esp), %eax
movl 8(%esp), %ecx
movl 12(%esp), %edx
monitor %eax, %ecx, %edx
ret
/* Waits - set up stack frame. */
NENTRY(x86_mwait)
pushl %ebp
movl %esp, %ebp
movl 8(%ebp), %eax
movl 12(%ebp), %ecx
mwait %eax, %ecx
leave
ret
NENTRY(x86_pause)
pause
ret
NENTRY(x86_cpuid)
pushl %ebx
pushl %edi
movl 12(%esp), %eax
movl 16(%esp), %edi
cpuid
movl %eax, 0(%edi)
movl %ebx, 4(%edi)
movl %ecx, 8(%edi)
movl %edx, 12(%edi)
popl %edi
popl %ebx
ret
NENTRY(x86_getss)
movl %ss, %eax
ret
NENTRY(fldcw)
movl 4(%esp), %eax
fldcw (%eax)
ret
NENTRY(fnclex)
fnclex
ret
NENTRY(fninit)
fninit
ret
NENTRY(fnsave)
movl 4(%esp), %eax
fnsave (%eax)
ret
NENTRY(fnstcw)
movl 4(%esp), %eax
fnstcw (%eax)
ret
NENTRY(fnstsw)
movl 4(%esp), %eax
fnstsw (%eax)
ret
NENTRY(fp_divide_by_0)
fldz
fld1
fdiv %st, %st(1)
fwait
ret
NENTRY(frstor)
movl 4(%esp), %eax
frstor (%eax)
ret
NENTRY(fwait)
fwait
ret
NENTRY(clts)
clts
ret
NENTRY(stts)
movl %cr0, %eax
orl $CR0_TS, %eax
movl %eax, %cr0
ret
NENTRY(fxsave)
movl 4(%esp), %eax
fxsave (%eax)
ret
NENTRY(fxrstor)
movl 4(%esp), %eax
fxrstor (%eax)
ret
NENTRY(fldummy)
movl 4(%esp), %eax
ffree %st(7)
fld (%eax)
ret
NENTRY(inb)
movl 4(%esp), %edx
xorl %eax, %eax
inb %dx, %al
ret
NENTRY(insb)
pushl %edi
movl 8(%esp), %edx
movl 12(%esp), %edi
movl 16(%esp), %ecx
cld
rep
insb
popl %edi
ret
NENTRY(inw)
movl 4(%esp), %edx
xorl %eax, %eax
inw %dx, %ax
ret
NENTRY(insw)
pushl %edi
movl 8(%esp), %edx
movl 12(%esp), %edi
movl 16(%esp), %ecx
cld
rep
insw
popl %edi
ret
NENTRY(inl)
movl 4(%esp), %edx
inl %dx, %eax
ret
NENTRY(insl)
pushl %edi
movl 8(%esp), %edx
movl 12(%esp), %edi
movl 16(%esp), %ecx
cld
rep
insl
popl %edi
ret
NENTRY(outb)
movl 4(%esp), %edx
movl 8(%esp), %eax
outb %al, %dx
ret
NENTRY(outsb)
pushl %esi
movl 8(%esp), %edx
movl 12(%esp), %esi
movl 16(%esp), %ecx
cld
rep
outsb
popl %esi
ret
NENTRY(outw)
movl 4(%esp), %edx
movl 8(%esp), %eax
outw %ax, %dx
ret
NENTRY(outsw)
pushl %esi
movl 8(%esp), %edx
movl 12(%esp), %esi
movl 16(%esp), %ecx
cld
rep
outsw
popl %esi
ret
NENTRY(outl)
movl 4(%esp), %edx
movl 8(%esp), %eax
outl %eax, %dx
ret
NENTRY(outsl)
pushl %esi
movl 8(%esp), %edx
movl 12(%esp), %esi
movl 16(%esp), %ecx
cld
rep
outsl
popl %esi
ret

71
sys/arch/i386/i386/db_dbgreg.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: db_dbgreg.S,v 1.4 2006/08/30 15:35:56 cube Exp $ */
/* $NetBSD: db_dbgreg.S,v 1.5 2007/09/26 19:48:36 ad Exp $ */
/*
* Mach Operating System
@ -39,75 +39,6 @@
#define B_ARG2 16(%ebp)
#define B_ARG3 20(%ebp)
/*
* void outb(unsigned char *io_port,
* unsigned char byte)
*
* Output a byte to an IO port.
*/
ENTRY(outb)
movl S_ARG0,%edx /* IO port address */
movl S_ARG1,%eax /* data to output */
outb %al,%dx /* send it out */
ret
/*
* unsigned char inb(unsigned char *io_port)
*
* Input a byte from an IO port.
*/
ENTRY(inb)
movl S_ARG0,%edx /* IO port address */
xorl %eax,%eax /* clear high bits of register */
inb %dx,%al /* get the byte */
ret
/*
* void outw(unsigned short *io_port,
* unsigned short word)
*
* Output a word to an IO port.
*/
ENTRY(outw)
movl S_ARG0,%edx /* IO port address */
movl S_ARG1,%eax /* data to output */
outw %ax,%dx /* send it out */
ret
/*
* unsigned short inw(unsigned short *io_port)
*
* Input a word from an IO port.
*/
ENTRY(inw)
movl S_ARG0,%edx /* IO port address */
xorl %eax,%eax /* clear high bits of register */
inw %dx,%ax /* get the word */
ret
/*
* void outl(unsigned int *io_port,
* unsigned int byte)
*
* Output an int to an IO port.
*/
ENTRY(outl)
movl S_ARG0,%edx /* IO port address */
movl S_ARG1,%eax /* data to output */
outl %eax,%dx /* send it out */
ret
/*
* unsigned int inl(unsigned int *io_port)
*
* Input an int from an IO port.
*/
ENTRY(inl)
movl S_ARG0,%edx /* IO port address */
inl %dx,%eax /* get the int */
ret
ENTRY(dr6)
movl %db6, %eax
ret

8
sys/arch/i386/i386/db_interface.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: db_interface.c,v 1.52 2007/09/22 18:40:22 martin Exp $ */
/* $NetBSD: db_interface.c,v 1.53 2007/09/26 19:48:36 ad Exp $ */
/*
* Mach Operating System
@ -33,7 +33,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.52 2007/09/22 18:40:22 martin Exp $");
__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.53 2007/09/26 19:48:36 ad Exp $");
#include "opt_ddb.h"
#include "opt_multiprocessor.h"
@ -212,7 +212,7 @@ kdb_trap(type, code, regs)
* Kernel mode - esp and ss not saved
*/
ddb_regs.tf_esp = (int)&regs->tf_esp; /* kernel stack pointer */
__asm("movw %%ss,%w0" : "=r" (ddb_regs.tf_ss));
ddb_regs.tf_ss = x86_getss();
}
ddb_regs.tf_cs &= 0xffff;
@ -325,7 +325,7 @@ ddb_suspend(struct trapframe *frame)
* Kernel mode - esp and ss not saved
*/
regs.tf_esp = (int)&frame->tf_esp; /* kernel stack pointer */
__asm("movw %%ss,%w0" : "=r" (regs.tf_ss));
regs.tf_ss = x86_getss();
}
ci->ci_ddb_regs = &regs;

8
sys/arch/i386/i386/genassym.cf
View File

@ -1,4 +1,4 @@
# $NetBSD: genassym.cf,v 1.51 2007/09/25 17:08:08 ad Exp $
# $NetBSD: genassym.cf,v 1.52 2007/09/26 19:48:36 ad Exp $
#
# Copyright (c) 1998 The NetBSD Foundation, Inc.
@ -150,6 +150,8 @@ endif
include <machine/tlog.h>
include <x86/busdefs.h>
define PAGE_SIZE PAGE_SIZE
define LSRUN LSRUN
@ -401,3 +403,7 @@ define MB_TAIL offsetof(struct pmap_mbox, mb_tail)
define PM_CPUS offsetof(struct pmap, pm_cpus)
define EV_COUNT offsetof(struct evcnt, ev_count)
define OPTERON_MSR_PASSCODE OPTERON_MSR_PASSCODE
define X86_BUS_SPACE_IO X86_BUS_SPACE_IO

168
sys/arch/i386/i386/i386func.S Normal file
View File

@ -0,0 +1,168 @@
/* $NetBSD: i386func.S,v 1.1 2007/09/26 19:48:36 ad Exp $ */
/*-
* Copyright (c) 1998, 2007 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Charles M. Hannum, and by Andrew Doran.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Functions to provide access to i386-specific instructions.
*
* These are _not_ shared with NetBSD/xen.
*/
#include <machine/asm.h>
#include <machine/specialreg.h>
#include <machine/segments.h>
#include "assym.h"
/* Small and slow, so align less. */
#undef _ALIGN_TEXT
#define _ALIGN_TEXT .align 8
NENTRY(invlpg)
movl 4(%esp), %eax
invlpg (%eax)
ret
NENTRY(lldt)
movl 4(%esp), %eax
lldt %ax
ret
NENTRY(ltr)
movl 4(%esp), %eax
ltr %ax
ret
NENTRY(lcr0)
movl 4(%esp), %eax
movl %eax, %cr0
ret
NENTRY(rcr0)
movl %cr0, %eax
ret
NENTRY(lcr3)
movl 4(%esp), %eax
movl %eax, %cr3
ret
/*
* Big hammer: flush all TLB entries, including ones from PTE's
* with the G bit set. This should only be necessary if TLB
* shootdown falls far behind.
*
* Intel Architecture Software Developer's Manual, Volume 3,
* System Programming, section 9.10, "Invalidating the
* Translation Lookaside Buffers (TLBS)":
* "The following operations invalidate all TLB entries, irrespective
* of the setting of the G flag:
* ...
* "(P6 family processors only): Writing to control register CR4 to
* modify the PSE, PGE, or PAE flag."
*
* (the alternatives not quoted above are not an option here.)
*
* If PGE is not in use, we reload CR3 for the benefit of
* pre-P6-family processors.
*/
NENTRY(tlbflushg)
testl $CPUID_PGE, _C_LABEL(cpu_feature)
jz 1f
movl %cr4, %eax
movl %eax, %edx
andl $~CR4_PGE, %edx
movl %edx, %cr4
movl %eax, %cr4
ret
NENTRY(tlbflush)
1:
movl %cr3, %eax
movl %eax, %cr3
ret
NENTRY(ldr6)
movl 4(%esp), %eax
movl %eax, %dr6
ret
NENTRY(rdr6)
movl %dr6, %eax
ret
NENTRY(rcr2)
movl %cr2, %eax
ret
NENTRY(wbinvd)
wbinvd
ret
NENTRY(x86_disable_intr)
cli
ret
NENTRY(x86_enable_intr)
sti
ret
/*
* void lgdt(struct region_descriptor *rdp);
*
* Load a new GDT pointer (and do any necessary cleanup).
* XXX It's somewhat questionable whether reloading all the segment registers
* is necessary, since the actual descriptor data is not changed except by
* process creation and exit, both of which clean up via task switches. OTOH,
* this only happens at run time when the GDT is resized.
*/
NENTRY(lgdt)
/* Reload the descriptor table. */
movl 4(%esp), %eax
lgdt (%eax)
/* Flush the prefetch queue. */
jmp 1f
nop
1: /* Reload "stale" selectors. */
movl $GSEL(GDATA_SEL, SEL_KPL), %eax
movl %eax, %ds
movl %eax, %es
movl %eax, %gs
movl %eax, %ss
movl $GSEL(GCPU_SEL, SEL_KPL), %eax
movl %eax, %fs
jmp _C_LABEL(x86_flush)

140
sys/arch/i386/i386/identcpu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: identcpu.c,v 1.74 2007/07/25 13:41:53 xtraeme Exp $ */
/* $NetBSD: identcpu.c,v 1.75 2007/09/26 19:48:36 ad Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001 The NetBSD Foundation, Inc.
@ -37,7 +37,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.74 2007/07/25 13:41:53 xtraeme Exp $");
__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.75 2007/09/26 19:48:36 ad Exp $");
#include "opt_cputype.h"
#include "opt_enhanced_speedstep.h"
@ -660,14 +660,14 @@ via_cpu_probe(struct cpu_info *ci)
/*
* Determine the largest extended function value.
*/
CPUID(0x80000000, descs[0], descs[1], descs[2], descs[3]);
x86_cpuid(0x80000000, descs);
lfunc = descs[0];
/*
* Determine the extended feature flags.
*/
if (lfunc >= 0x80000001) {
CPUID(0x80000001, descs[0], descs[1], descs[2], descs[3]);
x86_cpuid(0x80000001, descs);
ci->ci_feature_flags |= descs[3];
}
@ -675,12 +675,12 @@ via_cpu_probe(struct cpu_info *ci)
return;
/* Nehemiah or Esther */
CPUID(0xc0000000, descs[0], descs[1], descs[2], descs[3]);
x86_cpuid(0xc0000000, descs);
lfunc = descs[0];
if (lfunc < 0xc0000001) /* no ACE, no RNG */
return;
CPUID(0xc0000001, descs[0], descs[1], descs[2], descs[3]);
x86_cpuid(0xc0000001, descs);
lfunc = descs[3];
if (model > 0x9 || stepping >= 8) { /* ACE */
if (lfunc & CPUID_VIA_HAS_ACE) {
@ -905,23 +905,24 @@ cpu_probe_base_features(struct cpu_info *ci)
u_int descs[4];
int iterations, i, j;
uint8_t desc;
uint32_t dummy1, dummy2, miscbytes;
uint32_t miscbytes;
uint32_t brand[12];
if (ci->ci_cpuid_level < 0)
return;
CPUID(0, ci->ci_cpuid_level,
ci->ci_vendor[0],
ci->ci_vendor[2],
ci->ci_vendor[1]);
x86_cpuid(0, descs);
ci->ci_cpuid_level = descs[0];
ci->ci_vendor[0] = descs[1];
ci->ci_vendor[2] = descs[2];
ci->ci_vendor[1] = descs[3];
ci->ci_vendor[3] = 0;
CPUID(0x80000000, brand[0], brand[1], brand[2], brand[3]);
x86_cpuid(0x80000000, brand);
if (brand[0] >= 0x80000004) {
CPUID(0x80000002, brand[0], brand[1], brand[2], brand[3]);
CPUID(0x80000003, brand[4], brand[5], brand[6], brand[7]);
CPUID(0x80000004, brand[8], brand[9], brand[10], brand[11]);
x86_cpuid(0x80000002, brand);
x86_cpuid(0x80000003, brand + 4);
x86_cpuid(0x80000004, brand + 8);
for (i = 0; i < 48; i++)
if (((char *) brand)[i] != ' ')
break;
@ -931,8 +932,11 @@ cpu_probe_base_features(struct cpu_info *ci)
if (ci->ci_cpuid_level < 1)
return;
CPUID(1, ci->ci_signature, miscbytes, ci->ci_feature2_flags,
ci->ci_feature_flags);
x86_cpuid(1, descs);
ci->ci_signature = descs[0];
miscbytes = descs[1];
ci->ci_feature2_flags = descs[2];
ci->ci_feature_flags = descs[3];
/* Brand is low order 8 bits of ebx */
ci->ci_brand_id = miscbytes & 0xff;
@ -949,7 +953,7 @@ cpu_probe_base_features(struct cpu_info *ci)
* XXX This is kinda ugly, but hey, so is the architecture...
*/
CPUID(2, descs[0], descs[1], descs[2], descs[3]);
x86_cpuid(2, descs);
iterations = descs[0] & 0xff;
while (iterations-- > 0) {
@ -968,7 +972,7 @@ cpu_probe_base_features(struct cpu_info *ci)
ci->ci_cinfo[cai->cai_index] = *cai;
}
}
CPUID(2, descs[0], descs[1], descs[2], descs[3]);
x86_cpuid(2, descs);
}
if (ci->ci_cpuid_level < 3)
@ -981,9 +985,9 @@ cpu_probe_base_features(struct cpu_info *ci)
if ((ci->ci_feature_flags & CPUID_PN) != 0)
{
ci->ci_cpu_serial[0] = ci->ci_signature;
CPUID(3, dummy1, dummy2,
ci->ci_cpu_serial[2],
ci->ci_cpu_serial[1]);
x86_cpuid(3, descs);
ci->ci_cpu_serial[2] = descs[2];
ci->ci_cpu_serial[1] = descs[3];
}
}
@ -1026,16 +1030,15 @@ cpu_probe_features(struct cpu_info *ci)
void
intel_family_new_probe(struct cpu_info *ci)
{
uint32_t lfunc;
uint32_t descs[4];
CPUID(0x80000000, lfunc, descs[1], descs[2], descs[3]);
x86_cpuid(0x80000000, descs);
/*
* Determine extended feature flags.
*/
if (lfunc >= 0x80000001) {
CPUID(0x80000001, descs[0], descs[1], descs[2], descs[3]);
if (descs[0] >= 0x80000001) {
x86_cpuid(0x80000001, descs);
ci->ci_feature3_flags |= descs[3];
}
}
@ -1043,18 +1046,17 @@ intel_family_new_probe(struct cpu_info *ci)
void
amd_family6_probe(struct cpu_info *ci)
{
uint32_t lfunc;
uint32_t descs[4];
char *p;
int i;
CPUID(0x80000000, lfunc, descs[1], descs[2], descs[3]);
x86_cpuid(0x80000000, descs);
/*
* Determine the extended feature flags.
*/
if (lfunc >= 0x80000001) {
CPUID(0x80000001, descs[0], descs[1], descs[2], descs[3]);
if (descs[0] >= 0x80000001) {
x86_cpuid(0x80000001, descs);
ci->ci_feature_flags |= descs[3];
}
@ -1131,8 +1133,8 @@ tmx86_get_longrun_mode(void)
union msrinfo msrinfo;
u_int low, high, flags, mode;
eflags = read_eflags();
disable_intr();
eflags = x86_read_psl();
x86_disable_intr();
msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
low = LONGRUN_MODE_MASK(msrinfo.regs[0]);
@ -1148,25 +1150,25 @@ tmx86_get_longrun_mode(void)
}
mode = LONGRUN_MODE_UNKNOWN;
out:
write_eflags(eflags);
x86_write_psl(eflags);
return (mode);
}
static u_int
tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage)
{
u_long eflags;
u_int eax, ebx, ecx, edx;
u_long eflags;
u_int descs[4];
eflags = read_eflags();
disable_intr();
eflags = x86_read_psl();
x86_disable_intr();
CPUID(0x80860007, eax, ebx, ecx, edx);
*frequency = eax;
*voltage = ebx;
*percentage = ecx;
x86_cpuid(0x80860007, descs);
*frequency = descs[0];
*voltage = descs[1];
*percentage = descs[2];
write_eflags(eflags);
x86_write_psl(eflags);
return (1);
}
@ -1180,8 +1182,8 @@ tmx86_set_longrun_mode(u_int mode)
return (0);
}
eflags = read_eflags();
disable_intr();
eflags = x86_read_psl();
x86_disable_intr();
/* Write LongRun mode values to Model Specific Register. */
msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
@ -1196,7 +1198,7 @@ tmx86_set_longrun_mode(u_int mode)
msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | longrun_modes[mode][2];
wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr);
write_eflags(eflags);
x86_write_psl(eflags);
return (1);
}
@ -1216,47 +1218,39 @@ tmx86_get_longrun_status_all(void)
static void
transmeta_cpu_info(struct cpu_info *ci)
{
u_int eax, ebx, ecx, edx, nreg = 0;
u_int descs[4], nreg;
CPUID(0x80860000, eax, ebx, ecx, edx);
nreg = eax;
x86_cpuid(0x80860000, descs);
nreg = descs[0];
if (nreg >= 0x80860001) {
CPUID(0x80860001, eax, ebx, ecx, edx);
x86_cpuid(0x80860001, descs);
aprint_verbose("%s: Processor revision %u.%u.%u.%u\n",
ci->ci_dev->dv_xname,
(ebx >> 24) & 0xff,
(ebx >> 16) & 0xff,
(ebx >> 8) & 0xff,
ebx & 0xff);
(descs[1] >> 24) & 0xff,
(descs[1] >> 16) & 0xff,
(descs[1] >> 8) & 0xff,
descs[1] & 0xff);
}
if (nreg >= 0x80860002) {
CPUID(0x80860002, eax, ebx, ecx, edx);
x86_cpuid(0x80860002, descs);
aprint_verbose("%s: Code Morphing Software Rev: %u.%u.%u-%u-%u\n",
ci->ci_dev->dv_xname, (ebx >> 24) & 0xff,
(ebx >> 16) & 0xff,
(ebx >> 8) & 0xff,
ebx & 0xff,
ecx);
ci->ci_dev->dv_xname, (descs[1] >> 24) & 0xff,
(descs[1] >> 16) & 0xff,
(descs[1] >> 8) & 0xff,
descs[1] & 0xff,
descs[2]);
}
if (nreg >= 0x80860006) {
union {
char text[65];
struct
{
u_int eax;
u_int ebx;
u_int ecx;
u_int edx;
} regs[4];
u_int descs[4][4];
} info;
int i;
for (i=0; i<4; i++) {
CPUID(0x80860003 + i,
info.regs[i].eax, info.regs[i].ebx,
info.regs[i].ecx, info.regs[i].edx);
x86_cpuid(0x80860003 + i, info.descs[i]);
}
info.text[64] = 0;
info.text[64] = '\0';
aprint_verbose("%s: %s\n", ci->ci_dev->dv_xname, info.text);
}
@ -1274,10 +1268,10 @@ transmeta_cpu_info(struct cpu_info *ci)
void
transmeta_cpu_setup(struct cpu_info *ci)
{
u_int nreg = 0, dummy;
u_int descs[4];
CPUID(0x80860000, nreg, dummy, dummy, dummy);
if (nreg >= 0x80860007)
x86_cpuid(0x80860000, descs);
if (descs[0] >= 0x80860007)
tmx86_has_longrun = 1;
}

8
sys/arch/i386/i386/ipifuncs.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: ipifuncs.c,v 1.18 2007/08/29 23:38:04 ad Exp $ */
/* $NetBSD: ipifuncs.c,v 1.19 2007/09/26 19:48:36 ad Exp $ */
/*-
* Copyright (c) 2000 The NetBSD Foundation, Inc.
@ -44,7 +44,7 @@
*/
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: ipifuncs.c,v 1.18 2007/08/29 23:38:04 ad Exp $");
__KERNEL_RCSID(0, "$NetBSD: ipifuncs.c,v 1.19 2007/09/26 19:48:36 ad Exp $");
#include "opt_ddb.h"
#include "opt_mtrr.h"
@ -102,11 +102,11 @@ void (*ipifunc[X86_NIPI])(struct cpu_info *) =
void
i386_ipi_halt(struct cpu_info *ci)
{
disable_intr();
x86_disable_intr();
x86_atomic_clearbits_l(&ci->ci_flags, CPUF_RUNNING);
for(;;) {
__asm volatile("hlt");
x86_hlt();
}
}

43
sys/arch/i386/i386/locore.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.S,v 1.50 2007/08/29 23:38:04 ad Exp $ */
/* $NetBSD: locore.S,v 1.51 2007/09/26 19:48:36 ad Exp $ */
/*-
* Copyright (c) 1998, 2000, 2004, 2006, 2007 The NetBSD Foundation, Inc.
@ -629,47 +629,6 @@ NENTRY(sigcode)
.globl _C_LABEL(esigcode)
_C_LABEL(esigcode):
/*
* void lgdt(struct region_descriptor *rdp);
*
* Load a new GDT pointer (and do any necessary cleanup).
* XXX It's somewhat questionable whether reloading all the segment registers
* is necessary, since the actual descriptor data is not changed except by
* process creation and exit, both of which clean up via task switches. OTOH,
* this only happens at run time when the GDT is resized.
*/
NENTRY(lgdt)
/* Reload the descriptor table. */
movl 4(%esp),%eax
lgdt (%eax)
/* Flush the prefetch queue. */
jmp 1f
nop
1: /* Reload "stale" selectors. */
movl $GSEL(GDATA_SEL, SEL_KPL),%eax
movw %ax,%ds
movw %ax,%es
movw %ax,%gs
movw %ax,%ss
movl $GSEL(GCPU_SEL, SEL_KPL),%eax
movw %ax,%fs
/* Reload code selector by doing intersegment return. */
popl %eax
pushl $GSEL(GCODE_SEL, SEL_KPL)
pushl %eax
lret
/*
* void x86_flush()
*
* Flush instruction pipelines by doing an intersegment (far) return.
*/
NENTRY(x86_flush)
popl %eax
pushl $GSEL(GCODE_SEL, SEL_KPL)
pushl %eax
lret
/*
* int setjmp(label_t *)
*

14
sys/arch/i386/i386/machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.607 2007/08/07 11:30:20 ad Exp $ */
/* $NetBSD: machdep.c,v 1.608 2007/09/26 19:48:37 ad Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998, 2000, 2004, 2006 The NetBSD Foundation, Inc.
@ -72,7 +72,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.607 2007/08/07 11:30:20 ad Exp $");
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.608 2007/09/26 19:48:37 ad Exp $");
#include "opt_beep.h"
#include "opt_compat_ibcs2.h"
@ -911,7 +911,7 @@ haltsys:
if (cngetc() == 0) {
/* no console attached, so just hlt */
for(;;) {
__asm volatile("hlt");
x86_hlt();
}
}
cnpollc(0);
@ -2070,7 +2070,7 @@ init386(paddr_t first_avail)
softintr_init();
splraise(IPL_IPI);
enable_intr();
x86_enable_intr();
if (physmem < btoc(2 * 1024 * 1024)) {
printf("warning: too little memory available; "
@ -2186,7 +2186,7 @@ cpu_reset()
{
struct region_descriptor region;
disable_intr();
x86_disable_intr();
#ifdef XBOX
if (arch_i386_is_xbox) {
@ -2218,7 +2218,7 @@ cpu_reset()
* sections 6.3.1, 6.3.2, and 6.4.1.
*/
if (cpu_info_primary.ci_signature == 0x540) {
outl(0xcf8, 0x80009044ul);
outl(0xcf8, 0x80009044);
outl(0xcfc, 0xf);
}
@ -2239,7 +2239,7 @@ cpu_reset()
memset((void *)idt, 0, NIDT * sizeof(idt[0]));
setregion(&region, idt, NIDT * sizeof(idt[0]) - 1);
lidt(&region);
__asm volatile("divl %0,%1" : : "q" (0), "a" (0));
breakpoint();
#if 0
/*

8
sys/arch/i386/i386/mtrr_k6.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mtrr_k6.c,v 1.10 2006/11/16 01:32:38 christos Exp $ */
/* $NetBSD: mtrr_k6.c,v 1.11 2007/09/26 19:48:37 ad Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: mtrr_k6.c,v 1.10 2006/11/16 01:32:38 christos Exp $");
__KERNEL_RCSID(0, "$NetBSD: mtrr_k6.c,v 1.11 2007/09/26 19:48:37 ad Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -105,7 +105,7 @@ k6_mtrr_reload(void)
uint32_t origcr0, cr0;
int i;
disable_intr();
x86_disable_intr();
origcr0 = cr0 = rcr0();
cr0 |= CR0_CD;
@ -122,7 +122,7 @@ k6_mtrr_reload(void)
lcr0(origcr0);
enable_intr();
x86_enable_intr();
}
static void

6
sys/arch/i386/i386/pmap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: pmap.c,v 1.214 2007/09/01 10:47:43 yamt Exp $ */
/* $NetBSD: pmap.c,v 1.215 2007/09/26 19:48:37 ad Exp $ */
/*
*
@ -60,7 +60,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.214 2007/09/01 10:47:43 yamt Exp $");
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.215 2007/09/26 19:48:37 ad Exp $");
#include "opt_cputype.h"
#include "opt_user_ldt.h"
@ -1922,7 +1922,7 @@ pmap_load(void)
/* should be able to take ipis. */
KASSERT(ci->ci_ilevel < IPL_IPI);
KASSERT((read_psl() & PSL_I) != 0);
KASSERT((x86_read_psl() & PSL_I) != 0);
l = ci->ci_curlwp;
KASSERT(l != NULL);

14
sys/arch/i386/i386/pmc.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: pmc.c,v 1.13 2007/04/16 19:12:18 ad Exp $ */
/* $NetBSD: pmc.c,v 1.14 2007/09/26 19:48:37 ad Exp $ */
/*-
* Copyright (c) 2000 Zembu Labs, Inc.
@ -38,7 +38,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: pmc.c,v 1.13 2007/04/16 19:12:18 ad Exp $");
__KERNEL_RCSID(0, "$NetBSD: pmc.c,v 1.14 2007/09/26 19:48:37 ad Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -173,6 +173,7 @@ pmc_startstop(struct lwp *l, struct x86_pmc_startstop_args *uargs,
else if ((pmc_running & mask) == 0 && start == 0)
return (0);
x86_disable_intr();
if (start) {
pmc_running |= mask;
pmc_state[args.counter].pmcs_val = args.val;
@ -215,10 +216,8 @@ pmc_startstop(struct lwp *l, struct x86_pmc_startstop_args *uargs,
(args.compare << PMC6_EVTSEL_COUNTER_MASK_SHIFT);
break;
}
disable_intr();
wrmsr(pmc_state[args.counter].pmcs_ctrmsr,
pmc_state[args.counter].pmcs_val);
enable_intr();
} else {
pmc_running &= ~mask;
pmc_state[args.counter].pmcs_control = 0;
@ -226,30 +225,25 @@ pmc_startstop(struct lwp *l, struct x86_pmc_startstop_args *uargs,
switch (pmc_type) {
case PMC_TYPE_I586:
disable_intr();
wrmsr(MSR_CESR, pmc_state[0].pmcs_control |
(pmc_state[1].pmcs_control << 16));
enable_intr();
break;
case PMC_TYPE_I686:
disable_intr();
if (args.counter == 1)
wrmsr(MSR_EVNTSEL1, pmc_state[1].pmcs_control);
wrmsr(MSR_EVNTSEL0, pmc_state[0].pmcs_control |
(pmc_running ? PMC6_EVTSEL_EN : 0));
enable_intr();
break;
case PMC_TYPE_K7:
disable_intr();
if (args.counter == 1)
wrmsr(MSR_K7_EVNTSEL1, pmc_state[1].pmcs_control);
wrmsr(MSR_K7_EVNTSEL0, pmc_state[0].pmcs_control |
(pmc_running ? K7_EVTSEL_EN : 0));
enable_intr();
break;
}
x86_enable_intr();
return (0);
}

8
sys/arch/i386/i386/powernow_k7.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: powernow_k7.c,v 1.26 2007/04/04 02:50:02 rmind Exp $ */
/* $NetBSD: powernow_k7.c,v 1.27 2007/09/26 19:48:37 ad Exp $ */
/* $OpenBSD: powernow-k7.c,v 1.24 2006/06/16 05:58:50 gwk Exp $ */
/*-
@ -66,7 +66,7 @@
/* AMD POWERNOW K7 driver */
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: powernow_k7.c,v 1.26 2007/04/04 02:50:02 rmind Exp $");
__KERNEL_RCSID(0, "$NetBSD: powernow_k7.c,v 1.27 2007/09/26 19:48:37 ad Exp $");
#include <sys/types.h>
#include <sys/param.h>
@ -219,7 +219,7 @@ k7_powernow_setperf(unsigned int freq)
ctl |= PN7_CTR_SGTC(cstate->sgtc);
if (k7pnow_flag & PN7_FLAG_ERRATA_A0)
disable_intr();
x86_disable_intr();
if (k7pnow_fid_to_mult[fid] < k7pnow_fid_to_mult[cfid]) {
wrmsr(MSR_AMDK7_FIDVID_CTL, ctl | PN7_CTR_FIDC);
@ -232,7 +232,7 @@ k7_powernow_setperf(unsigned int freq)
}
if (k7pnow_flag & PN7_FLAG_ERRATA_A0)
enable_intr();
x86_enable_intr();
status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
cfid = PN7_STA_CFID(status);

8
sys/arch/i386/i386/trap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: trap.c,v 1.219 2007/08/10 22:38:03 dyoung Exp $ */
/* $NetBSD: trap.c,v 1.220 2007/09/26 19:48:37 ad Exp $ */
/*-
* Copyright (c) 1998, 2000, 2005 The NetBSD Foundation, Inc.
@ -75,7 +75,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.219 2007/08/10 22:38:03 dyoung Exp $");
__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.220 2007/09/26 19:48:37 ad Exp $");
#include "opt_ddb.h"
#include "opt_kgdb.h"
@ -335,9 +335,9 @@ trap(frame)
else
printf("unknown trap %d", frame->tf_trapno);
printf(" in %s mode\n", (type & T_USER) ? "user" : "supervisor");
printf("trap type %d code %x eip %x cs %x eflags %x cr2 %x ilevel %x\n",
printf("trap type %d code %x eip %x cs %x eflags %x cr2 %lx ilevel %x\n",
type, frame->tf_err, frame->tf_eip, frame->tf_cs,
frame->tf_eflags, rcr2(), curcpu()->ci_ilevel);
frame->tf_eflags, (long)rcr2(), curcpu()->ci_ilevel);
panic("trap");
/*NOTREACHED*/

40
sys/arch/i386/include/atomic.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: atomic.h,v 1.9 2007/03/24 17:50:17 christos Exp $ */
/* $NetBSD: atomic.h,v 1.10 2007/09/26 19:48:41 ad Exp $ */
/*-
* Copyright (c) 2000 The NetBSD Foundation, Inc.
@ -43,39 +43,11 @@
#ifndef _LOCORE
static __inline unsigned long x86_atomic_testset_ul(volatile uint32_t *,
unsigned long);
static __inline unsigned long
x86_atomic_testset_ul(volatile uint32_t *__ptr, unsigned long __val) {
__asm volatile ("xchgl %0,(%2)" :"=r" (__val):"0" (__val),"r" (__ptr));
return __val;
}
static __inline int x86_atomic_testset_i(volatile int *, int);
static __inline int
x86_atomic_testset_i(volatile int *__ptr, int __val) {
__asm volatile ("xchgl %0,(%2)" :"=r" (__val):"0" (__val),"r" (__ptr));
return __val;
}
static __inline uint8_t x86_atomic_testset_b(volatile uint8_t *, uint8_t);
static __inline uint8_t
x86_atomic_testset_b(volatile uint8_t *__ptr, uint8_t __val) {
__asm volatile ("xchgb %0,(%2)" :"=A" (__val):"0" (__val),"r" (__ptr));
return __val;
}
static __inline void x86_atomic_setbits_l(volatile uint32_t *, unsigned long);
static __inline void
x86_atomic_setbits_l(volatile uint32_t *__ptr, unsigned long __bits) {
__asm volatile("lock ; orl %1,%0" : "=m" (*__ptr) : "ir" (__bits));
}
static __inline void x86_atomic_clearbits_l(volatile uint32_t *, unsigned long);
static __inline void
x86_atomic_clearbits_l(volatile uint32_t *__ptr, unsigned long __bits) {
__asm volatile("lock ; andl %1,%0" : "=m" (*__ptr) : "ir" (~__bits));
}
unsigned long x86_atomic_testset_ul(volatile uint32_t *, unsigned long);
int x86_atomic_testset_i(volatile int *, int);
uint8_t x86_atomic_testset_b(volatile uint8_t *, uint8_t);
void x86_atomic_setbits_l(volatile uint32_t *, unsigned long);
void x86_atomic_clearbits_l(volatile uint32_t *, unsigned long);
#endif
#endif

11
sys/arch/i386/include/byte_swap.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: byte_swap.h,v 1.11 2007/01/24 13:08:13 hubertf Exp $ */
/* $NetBSD: byte_swap.h,v 1.12 2007/09/26 19:48:41 ad Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@ -54,11 +54,7 @@ static __inline uint32_t
__byte_swap_u32_variable(uint32_t x)
{
__asm volatile (
#if defined(_KERNEL) && !defined(_LKM) && !defined(I386_CPU)
"bswap %1"
#else
"rorw $8, %w1\n\trorl $16, %1\n\trorw $8, %w1"
#endif
: "=r" (x) : "0" (x));
return (x);
}
@ -73,6 +69,11 @@ __byte_swap_u16_variable(uint16_t x)
}
__END_DECLS
#elif defined(_KERNEL) || defined(_LKM)
#define __BYTE_SWAP_U32_VARIABLE __byte_swap_u32_variable
#define __BYTE_SWAP_U16_VARIABLE __byte_swap_u16_variable
uint32_t __byte_swap_u32_variable(uint32_t);
uint16_t __byte_swap_u16_variable(uint16_t);
#endif
#endif /* !_I386_BYTE_SWAP_H_ */

46
sys/arch/i386/include/cpu.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.h,v 1.145 2007/09/25 17:08:09 ad Exp $ */
/* $NetBSD: cpu.h,v 1.146 2007/09/26 19:48:41 ad Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
@ -190,18 +190,18 @@ extern struct cpu_info *cpu_info_list;
#define CPU_INFO_FOREACH(cii, ci) cii = 0, ci = cpu_info_list; \
ci != NULL; ci = ci->ci_next
#if defined(MULTIPROCESSOR)
#define X86_MAXPROCS 32 /* because we use a bitmask */
#define CPU_STARTUP(_ci) ((_ci)->ci_func->start(_ci))
#define CPU_STOP(_ci) ((_ci)->ci_func->stop(_ci))
#define CPU_START_CLEANUP(_ci) ((_ci)->ci_func->cleanup(_ci))
static struct cpu_info *curcpu(void);
#if defined(__GNUC__) && defined(_KERNEL)
static struct cpu_info *x86_curcpu(void);
static lwp_t *x86_curlwp(void);
__inline static struct cpu_info * __attribute__((__unused__))
curcpu()
x86_curcpu(void)
{
struct cpu_info *ci;
@ -212,6 +212,23 @@ curcpu()
return ci;
}
__inline static lwp_t * __attribute__((__unused__))
x86_curlwp(void)
{
lwp_t *l;
__asm volatile("movl %%fs:%1, %0" :
"=r" (l) :
"m"
(*(struct cpu_info * const *)offsetof(struct cpu_info, ci_curlwp)));
return l;
}
#else /* __GNUC__ && _KERNEL */
/* For non-GCC and LKMs */
struct cpu_info *x86_curcpu(void);
lwp_t *x86_curlwp(void);
#endif /* __GNUC__ && _KERNEL */
#define cpu_number() (curcpu()->ci_cpuid)
#define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY)
@ -223,25 +240,10 @@ extern struct cpu_info *cpu_info[X86_MAXPROCS];
void cpu_boot_secondary_processors(void);
void cpu_init_idle_lwps(void);
#else /* !MULTIPROCESSOR */
#define X86_MAXPROCS 1
#define curcpu() (&cpu_info_primary)
/*
* definitions of cpu-dependent requirements
* referenced in generic code
*/
#define cpu_number() 0
#define CPU_IS_PRIMARY(ci) 1
#define aston(l) ((l)->l_md.md_astpending = 1)
#endif /* MULTIPROCESSOR */
extern uint32_t cpus_attached;
#define curlwp curcpu()->ci_curlwp
#define curcpu() x86_curcpu()
#define curlwp x86_curlwp()
#define curpcb (&curlwp->l_addr->u_pcb)
/*

353
sys/arch/i386/include/cpufunc.h
View File

@ -1,352 +1,3 @@
/* $NetBSD: cpufunc.h,v 1.38 2007/03/04 05:59:58 christos Exp $ */
/* $NetBSD: cpufunc.h,v 1.39 2007/09/26 19:48:41 ad Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Charles M. Hannum.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _I386_CPUFUNC_H_
#define _I386_CPUFUNC_H_
/*
* Functions to provide access to i386-specific instructions.
*/
#include <sys/cdefs.h>
#include <sys/types.h>
#include <machine/segments.h>
#include <machine/specialreg.h>
#ifdef _KERNEL
void x86_pause(void);
#else
static __inline void
x86_pause(void)
{
__asm volatile("pause");
}
#endif
/*
* XXX it's better to use real lfence insn if available.
*
* memory clobber to avoid compiler reordering.
*/
static __inline void
x86_lfence(void)
{
__asm volatile("lock; addl $0, 0(%%esp)" : : : "memory");
}
static __inline void
x86_sfence(void)
{
__asm volatile("lock; addl $0, 0(%%esp)" : : : "memory");
}
static __inline void
x86_mfence(void)
{
__asm volatile("lock; addl $0, 0(%%esp)" : : : "memory");
}
#ifdef _KERNEL
void x86_flush(void);
void x86_patch(void);
extern unsigned int cpu_feature;
static __inline void
invlpg(u_int addr)
{
__asm volatile("invlpg (%0)" : : "r" (addr) : "memory");
}
static __inline void
lidt(struct region_descriptor *region)
{
__asm volatile("lidt %0" : : "m" (*region));
}
static __inline void
lldt(u_short sel)
{
__asm volatile("lldt %0" : : "r" (sel));
}
static __inline void
ltr(u_short sel)
{
__asm volatile("ltr %0" : : "r" (sel));
}
static __inline void
lcr0(u_int val)
{
__asm volatile("movl %0,%%cr0" : : "r" (val));
}
static __inline u_int
rcr0(void)
{
u_int val;
__asm volatile("movl %%cr0,%0" : "=r" (val));
return val;
}
static __inline u_int
rcr2(void)
{
u_int val;
__asm volatile("movl %%cr2,%0" : "=r" (val));
return val;
}
static __inline void
lcr3(u_int val)
{
__asm volatile("movl %0,%%cr3" : : "r" (val));
}
static __inline u_int
rcr3(void)
{
u_int val;
__asm volatile("movl %%cr3,%0" : "=r" (val));
return val;
}
static __inline void
lcr4(u_int val)
{
__asm volatile("movl %0,%%cr4" : : "r" (val));
}
static __inline u_int
rcr4(void)
{
u_int val;
__asm volatile("movl %%cr4,%0" : "=r" (val));
return val;
}
static __inline void
tlbflush(void)
{
u_int val;
val = rcr3();
lcr3(val);
}
static __inline void
tlbflushg(void)
{
/*
* Big hammer: flush all TLB entries, including ones from PTE's
* with the G bit set. This should only be necessary if TLB
* shootdown falls far behind.
*
* Intel Architecture Software Developer's Manual, Volume 3,
* System Programming, section 9.10, "Invalidating the
* Translation Lookaside Buffers (TLBS)":
* "The following operations invalidate all TLB entries, irrespective
* of the setting of the G flag:
* ...
* "(P6 family processors only): Writing to control register CR4 to
* modify the PSE, PGE, or PAE flag."
*
* (the alternatives not quoted above are not an option here.)
*
* If PGE is not in use, we reload CR3 for the benefit of
* pre-P6-family processors.
*/
#if defined(I686_CPU)
if (cpu_feature & CPUID_PGE) {
u_int cr4 = rcr4();
lcr4(cr4 & ~CR4_PGE);
lcr4(cr4);
} else
#endif
tlbflush();
}
#ifdef notyet
void setidt(int idx, /*XXX*/void *func, int typ, int dpl);
#endif
/* debug register */
void dr0(void *, uint32_t, uint32_t, uint32_t);
static __inline u_int
rdr6(void)
{
u_int val;
__asm volatile("movl %%dr6,%0" : "=r" (val));
return val;
}
static __inline void
ldr6(u_int val)
{
__asm volatile("movl %0,%%dr6" : : "r" (val));
}
/* XXXX ought to be in psl.h with spl() functions */
static __inline void
disable_intr(void)
{
__asm volatile("cli");
}
static __inline void
enable_intr(void)
{
__asm volatile("sti");
}
static __inline u_long
read_eflags(void)
{
u_long ef;
__asm volatile("pushfl; popl %0" : "=r" (ef));
return (ef);
}
static __inline void
write_eflags(u_long ef)
{
__asm volatile("pushl %0; popfl" : : "r" (ef));
}
static __inline uint64_t
rdmsr(u_int msr)
{
uint64_t rv;
__asm volatile("rdmsr" : "=A" (rv) : "c" (msr));
return (rv);
}
static __inline void
wrmsr(u_int msr, uint64_t newval)
{
__asm volatile("wrmsr" : : "A" (newval), "c" (msr));
}
/*
* Some of the undocumented AMD64 MSRs need a 'passcode' to access.
*
* See LinuxBIOSv2: src/cpu/amd/model_fxx/model_fxx_init.c
*/
#define OPTERON_MSR_PASSCODE 0x9c5a203a
static __inline u_int64_t
rdmsr_locked(u_int msr, u_int code)
{
uint64_t rv;
__asm volatile("rdmsr"
: "=A" (rv)
: "c" (msr), "D" (code));
return (rv);
}
static __inline void
wrmsr_locked(u_int msr, u_int code, u_int64_t newval)
{
__asm volatile("wrmsr"
:
: "A" (newval), "c" (msr), "D" (code));
}
static __inline void
wbinvd(void)
{
__asm volatile("wbinvd");
}
static __inline uint64_t
rdtsc(void)
{
uint64_t rv;
__asm volatile("rdtsc" : "=A" (rv));
return (rv);
}
static __inline uint64_t
rdpmc(u_int pmc)
{
uint64_t rv;
__asm volatile("rdpmc" : "=A" (rv) : "c" (pmc));
return (rv);
}
/* Break into DDB/KGDB. */
static __inline void
breakpoint(void)
{
__asm volatile("int $3");
}
#define read_psl() read_eflags()
#define write_psl(x) write_eflags(x)
/*
* XXX Maybe these don't belong here...
*/
extern int (*copyout_func)(const void *, void *, size_t);
extern int (*copyin_func)(const void *, void *, size_t);
int i386_copyout(const void *, void *, size_t);
int i486_copyout(const void *, void *, size_t);
int i386_copyin(const void *, void *, size_t);
#endif /* _KERNEL */
#endif /* !_I386_CPUFUNC_H_ */
#include <x86/cpufunc.h>

4
sys/arch/i386/include/param.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: param.h,v 1.62 2006/12/08 15:05:18 yamt Exp $ */
/* $NetBSD: param.h,v 1.63 2007/09/26 19:48:41 ad Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
@ -66,7 +66,7 @@
* (within reasonable limits).
*
*/
#define ALIGNBYTES (sizeof(int) - 1)
#define ALIGNBYTES (sizeof(double) - 1)
#define ALIGN(p) (((u_int)(u_long)(p) + ALIGNBYTES) &~ \
ALIGNBYTES)
#define ALIGNED_POINTER(p,t) 1

33
sys/arch/i386/isa/npx.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: npx.c,v 1.116 2006/12/08 15:05:18 yamt Exp $ */
/* $NetBSD: npx.c,v 1.117 2007/09/26 19:48:41 ad Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@ -67,7 +67,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: npx.c,v 1.116 2006/12/08 15:05:18 yamt Exp $");
__KERNEL_RCSID(0, "$NetBSD: npx.c,v 1.117 2007/09/26 19:48:41 ad Exp $");
#if 0
#define IPRINTF(x) printf x
@ -125,29 +125,12 @@ __KERNEL_RCSID(0, "$NetBSD: npx.c,v 1.116 2006/12/08 15:05:18 yamt Exp $");
* state is saved.
*/
#define fldcw(addr) __asm("fldcw %0" : : "m" (*addr))
#define fnclex() __asm("fnclex")
#define fninit() __asm("fninit")
#define fnsave(addr) __asm("fnsave %0" : "=m" (*addr))
#define fnstcw(addr) __asm("fnstcw %0" : "=m" (*addr))
#define fnstsw(addr) __asm("fnstsw %0" : "=m" (*addr))
#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fwait")
#define frstor(addr) __asm("frstor %0" : : "m" (*addr))
#define fwait() __asm("fwait")
#define clts() __asm("clts")
#define stts() lcr0(rcr0() | CR0_TS)
static int npxdna_s87(struct cpu_info *);
#ifdef I686_CPU
static int npxdna_xmm(struct cpu_info *);
#endif /* I686_CPU */
static int x86fpflags_to_ksiginfo(uint32_t flags);
#ifdef I686_CPU
#define fxsave(addr) __asm("fxsave %0" : "=m" (*addr))
#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*addr))
#endif /* I686_CPU */
static enum npx_type npx_type;
volatile u_int npx_intrs_while_probing;
volatile u_int npx_traps_while_probing;
@ -205,8 +188,8 @@ npxprobe1(bus_space_tag_t iot, bus_space_handle_t ioh, int irq)
i386_fpu_exception = 1;
return NPX_CPUID;
}
save_eflags = read_eflags();
disable_intr();
save_eflags = x86_read_psl();
x86_disable_intr();
save_idt_npxintr = idt[NRSVIDT + irq];
save_idt_npxtrap = idt[16];
setgate(&idt[NRSVIDT + irq], probeintr, 0, SDT_SYS386IGT, SEL_KPL,
@ -231,7 +214,7 @@ npxprobe1(bus_space_tag_t iot, bus_space_handle_t ioh, int irq)
* We have to turn off the CR0_EM bit temporarily while probing.
*/
lcr0(rcr0() & ~(CR0_EM|CR0_TS));
enable_intr();
x86_enable_intr();
/*
* Finish resetting the coprocessor, if any. If there is an error
@ -282,7 +265,7 @@ npxprobe1(bus_space_tag_t iot, bus_space_handle_t ioh, int irq)
}
}
disable_intr();
x86_disable_intr();
lcr0(rcr0() | (CR0_EM|CR0_TS));
irqmask = i8259_setmask(irqmask);
@ -291,7 +274,7 @@ npxprobe1(bus_space_tag_t iot, bus_space_handle_t ioh, int irq)
idt_allocmap[NRSVIDT + irq] = 1;
idt[16] = save_idt_npxtrap;
write_eflags(save_eflags);
x86_write_psl(save_eflags);
return (rv);
}
@ -586,7 +569,7 @@ npxdna_xmm(struct cpu_info *ci)
* the x87 stack, but we don't care since we're about to call
* fxrstor() anyway.
*/
__asm __volatile("ffree %%st(7)\n\tfld %0" : : "m" (zero));
fldummy(&zero);
fxrstor(&l->l_addr->u_pcb.pcb_savefpu.sv_xmm);
}

6
sys/arch/i386/mca/mca_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mca_machdep.c,v 1.31 2007/02/22 04:38:04 matt Exp $ */
/* $NetBSD: mca_machdep.c,v 1.32 2007/09/26 19:48:42 ad Exp $ */
/*-
* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
@ -43,7 +43,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: mca_machdep.c,v 1.31 2007/02/22 04:38:04 matt Exp $");
__KERNEL_RCSID(0, "$NetBSD: mca_machdep.c,v 1.32 2007/09/26 19:48:42 ad Exp $");
#include <sys/types.h>
#include <sys/param.h>
@ -56,9 +56,9 @@ __KERNEL_RCSID(0, "$NetBSD: mca_machdep.c,v 1.31 2007/02/22 04:38:04 matt Exp $"
#include <machine/bioscall.h>
#include <machine/psl.h>
#include <machine/bus.h>
#include <machine/bus_private.h>
#include <machine/pio.h>
#include <dev/isa/isavar.h>
#include <dev/isa/isareg.h>

8
sys/arch/i386/pnpbios/pnpbios.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: pnpbios.c,v 1.59 2007/07/09 20:52:18 ad Exp $ */
/* $NetBSD: pnpbios.c,v 1.60 2007/09/26 19:48:42 ad Exp $ */
/*
* Copyright (c) 2000 Jason R. Thorpe. All rights reserved.
@ -41,7 +41,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: pnpbios.c,v 1.59 2007/07/09 20:52:18 ad Exp $");
__KERNEL_RCSID(0, "$NetBSD: pnpbios.c,v 1.60 2007/09/26 19:48:42 ad Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -1285,7 +1285,7 @@ pnpbios_io_map(pnpbios_tag_t pbt, struct pnpresources *resc,
io = SIMPLEQ_NEXT(io, next);
*tagp = X86_BUS_SPACE_IO;
return (x86_memio_map(X86_BUS_SPACE_IO, io->minbase, io->len,
return (bus_space_map(X86_BUS_SPACE_IO, io->minbase, io->len,
0, hdlp));
}
@ -1302,7 +1302,7 @@ pnpbios_io_unmap(pnpbios_tag_t pbt, struct pnpresources *resc,
while (idx--)
io = SIMPLEQ_NEXT(io, next);
x86_memio_unmap(tag, hdl, io->len);
bus_space_unmap(tag, hdl, io->len);
}
int

1064
sys/arch/x86/include/bus.h
View File

File diff suppressed because it is too large Load Diff

50
sys/arch/x86/include/bus_private.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: bus_private.h,v 1.8 2007/03/04 06:01:08 christos Exp $ */
/* $NetBSD: bus_private.h,v 1.9 2007/09/26 19:48:38 ad Exp $ */
/* NetBSD: bus.h,v 1.8 2005/03/09 19:04:46 matt Exp */
/*-
@ -198,5 +198,53 @@ _bus_virt_to_bus(struct pmap *pm, vaddr_t va)
#define _BUS_AVAIL_END (avail_end)
#endif
struct x86_bus_dma_tag {
/*
* The `bounce threshold' is checked while we are loading
* the DMA map. If the physical address of the segment
* exceeds the threshold, an error will be returned. The
* caller can then take whatever action is necessary to
* bounce the transfer. If this value is 0, it will be
* ignored.
*/
int _tag_needs_free;
bus_addr_t _bounce_thresh;
bus_addr_t _bounce_alloc_lo;
bus_addr_t _bounce_alloc_hi;
int (*_may_bounce)(bus_dma_tag_t, bus_dmamap_t, int, int *);
/*
* DMA mapping methods.
*/
int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int,
bus_size_t, bus_size_t, int, bus_dmamap_t *);
void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t);
int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *,
bus_size_t, struct proc *, int);
int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t,
struct mbuf *, int);
int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t,
struct uio *, int);
int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t,
bus_dma_segment_t *, int, bus_size_t, int);
void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t);
void (*_dmamap_sync)(bus_dma_tag_t, bus_dmamap_t,
bus_addr_t, bus_size_t, int);
/*
* DMA memory utility functions.
*/
int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t,
bus_size_t, bus_dma_segment_t *, int, int *, int);
void (*_dmamem_free)(bus_dma_tag_t, bus_dma_segment_t *, int);
int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *,
int, size_t, void **, int);
void (*_dmamem_unmap)(bus_dma_tag_t, void *, size_t);
paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *,
int, off_t, int, int);
int (*_dmatag_subregion)(bus_dma_tag_t, bus_addr_t, bus_addr_t,
bus_dma_tag_t *, int);
void (*_dmatag_destroy)(bus_dma_tag_t);
};
#endif /* !defined(_X86_BUS_PRIVATE_H_) */

82
sys/arch/x86/include/busdefs.h Normal file
View File

@ -0,0 +1,82 @@
/* $NetBSD: busdefs.h,v 1.1 2007/09/26 19:48:38 ad Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
* NASA Ames Research Center.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Copyright (c) 1996 Charles M. Hannum. All rights reserved.
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Christopher G. Demetriou
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _X86_BUSDEFS_H_
#define _X86_BUSDEFS_H_
/*
* Values for the x86 bus space tag, not to be used directly by MI code.
*/
#define X86_BUS_SPACE_IO 0 /* space is i/o space */
#define X86_BUS_SPACE_MEM 1 /* space is mem space */
#define __BUS_SPACE_HAS_STREAM_METHODS 1
#endif /* _X86_BUSDEFS_H_ */

141
sys/arch/x86/include/cpufunc.h Normal file
View File

@ -0,0 +1,141 @@
/* $NetBSD: cpufunc.h,v 1.1 2007/09/26 19:48:38 ad Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Charles M. Hannum.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _X86_CPUFUNC_H_
#define _X86_CPUFUNC_H_
/*
* Functions to provide access to x86-specific instructions.
*/
#include <sys/cdefs.h>
#include <sys/types.h>
#include <machine/segments.h>
#include <machine/specialreg.h>
#ifdef _KERNEL
void x86_pause(void);
void x86_lfence(void);
void x86_sfence(void);
void x86_mfence(void);
void x86_flush(void);
void x86_patch(void);
void invlpg(vaddr_t);
void lidt(struct region_descriptor *);
void lldt(u_short);
void ltr(u_short);
void lcr0(u_int);
u_int rcr0(void);
vaddr_t rcr2(void);
void lcr3(vaddr_t);
vaddr_t rcr3(void);
void lcr4(vaddr_t);
vaddr_t rcr4(void);
void lcr8(vaddr_t);
vaddr_t rcr8(void);
void tlbflush(void);
void tlbflushg(void);
void dr0(void *, uint32_t, uint32_t, uint32_t);
vaddr_t rdr6(void);
void ldr6(vaddr_t);
void wbinvd(void);
void breakpoint(void);
void x86_hlt(void);
void x86_stihlt(void);
u_int x86_getss(void);
void fldcw(void *);
void fnclex(void);
void fninit(void);
void fnsave(void *);
void fnstcw(void *);
void fnstsw(void *);
void fp_divide_by_0(void);
void frstor(void *);
void fwait(void);
void clts(void);
void stts(void);
void fldummy(const double *);
void fxsave(void *);
void fxrstor(void *);
void x86_monitor(const void *, uint32_t, uint32_t);
void x86_mwait(uint32_t, uint32_t);
void x86_ldmxcsr(void *);
void x86_cpuid(unsigned, unsigned *);
/* Use read_psl, write_psl when saving and restoring interrupt state. */
void x86_disable_intr(void);
void x86_enable_intr(void);
u_long x86_read_psl(void);
void x86_write_psl(u_long);
/* Use read_flags, write_flags to adjust other members of %eflags. */
u_long x86_read_flags(void);
void x86_write_flags(u_long);
/*
* Some of the undocumented AMD64 MSRs need a 'passcode' to access.
*
* See LinuxBIOSv2: src/cpu/amd/model_fxx/model_fxx_init.c
*/
#define OPTERON_MSR_PASSCODE 0x9c5a203aU
uint64_t rdmsr(u_int);
u_int64_t rdmsr_locked(u_int, u_int);
uint64_t rdtsc(void);
uint64_t rdpmc(u_int);
void wrmsr(u_int, uint64_t);
void wrmsr_locked(u_int, u_int, u_int64_t);
/*
* XXX Maybe these don't belong here...
*/
extern int (*copyout_func)(const void *, void *, size_t);
extern int (*copyin_func)(const void *, void *, size_t);
int i386_copyout(const void *, void *, size_t);
int i486_copyout(const void *, void *, size_t);
int i386_copyin(const void *, void *, size_t);
#endif /* _KERNEL */
#endif /* !_X86_CPUFUNC_H_ */

199
sys/arch/x86/include/pio.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: pio.h,v 1.5 2006/02/16 20:17:15 perry Exp $ */
/* $NetBSD: pio.h,v 1.6 2007/09/26 19:48:38 ad Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@ -41,191 +41,20 @@
/*
* Functions to provide access to x86 programmed I/O instructions.
*
* The in[bwl]() and out[bwl]() functions are split into two varieties: one to
* use a small, constant, 8-bit port number, and another to use a large or
* variable port number. The former can be compiled as a smaller instruction.
*/
u_int8_t inb(unsigned);
void insb(unsigned, void *, int);
uint16_t inw(unsigned);
void insw(unsigned, void *, int);
uint32_t inl(unsigned);
void insl(unsigned, void *, int);
#ifdef __OPTIMIZE__
#define __use_immediate_port(port) \
(__builtin_constant_p((port)) && (port) < 0x100)
#else
#define __use_immediate_port(port) 0
#endif
#define inb(port) \
(/* CONSTCOND */ __use_immediate_port(port) ? __inbc(port) : __inb(port))
static __inline u_int8_t
__inbc(unsigned port)
{
u_int8_t data;
__asm volatile("inb %w1,%0" : "=a" (data) : "id" (port));
return data;
}
static __inline u_int8_t
__inb(unsigned port)
{
u_int8_t data;
__asm volatile("inb %w1,%0" : "=a" (data) : "d" (port));
return data;
}
static __inline void
insb(unsigned port, void *addr, int cnt)
{
void *dummy1;
int dummy2;
__asm volatile("cld\n\trep\n\tinsb" :
"=D" (dummy1), "=c" (dummy2) :
"d" (port), "0" (addr), "1" (cnt) :
"memory");
}
#define inw(port) \
(/* CONSTCOND */ __use_immediate_port(port) ? __inwc(port) : __inw(port))
static __inline u_int16_t
__inwc(unsigned port)
{
u_int16_t data;
__asm volatile("inw %w1,%0" : "=a" (data) : "id" (port));
return data;
}
static __inline u_int16_t
__inw(unsigned port)
{
u_int16_t data;
__asm volatile("inw %w1,%0" : "=a" (data) : "d" (port));
return data;
}
static __inline void
insw(unsigned port, void *addr, int cnt)
{
void *dummy1;
int dummy2;
__asm volatile("cld\n\trep\n\tinsw" :
"=D" (dummy1), "=c" (dummy2) :
"d" (port), "0" (addr), "1" (cnt) :
"memory");
}
#define inl(port) \
(/* CONSTCOND */ __use_immediate_port(port) ? __inlc(port) : __inl(port))
static __inline u_int32_t
__inlc(unsigned port)
{
u_int32_t data;
__asm volatile("inl %w1,%0" : "=a" (data) : "id" (port));
return data;
}
static __inline u_int32_t
__inl(unsigned port)
{
u_int32_t data;
__asm volatile("inl %w1,%0" : "=a" (data) : "d" (port));
return data;
}
static __inline void
insl(unsigned port, void *addr, int cnt)
{
void *dummy1;
int dummy2;
__asm volatile("cld\n\trep\n\tinsl" :
"=D" (dummy1), "=c" (dummy2) :
"d" (port), "0" (addr), "1" (cnt) :
"memory");
}
#define outb(port, data) \
(/* CONSTCOND */__use_immediate_port(port) ? __outbc(port, data) : \
__outb(port, data))
static __inline void
__outbc(unsigned port, u_int8_t data)
{
__asm volatile("outb %0,%w1" : : "a" (data), "id" (port));
}
static __inline void
__outb(unsigned port, u_int8_t data)
{
__asm volatile("outb %0,%w1" : : "a" (data), "d" (port));
}
static __inline void
outsb(unsigned port, const void *addr, int cnt)
{
void *dummy1;
int dummy2;
__asm volatile("cld\n\trep\n\toutsb" :
"=S" (dummy1), "=c" (dummy2) :
"d" (port), "0" (addr), "1" (cnt));
}
#define outw(port, data) \
(/* CONSTCOND */ __use_immediate_port(port) ? __outwc(port, data) : \
__outw(port, data))
static __inline void
__outwc(unsigned port, u_int16_t data)
{
__asm volatile("outw %0,%w1" : : "a" (data), "id" (port));
}
static __inline void
__outw(unsigned port, u_int16_t data)
{
__asm volatile("outw %0,%w1" : : "a" (data), "d" (port));
}
static __inline void
outsw(unsigned port, const void *addr, int cnt)
{
void *dummy1;
int dummy2;
__asm volatile("cld\n\trep\n\toutsw" :
"=S" (dummy1), "=c" (dummy2) :
"d" (port), "0" (addr), "1" (cnt));
}
#define outl(port, data) \
(/* CONSTCOND */ __use_immediate_port(port) ? __outlc(port, data) : \
__outl(port, data))
static __inline void
__outlc(unsigned port, u_int32_t data)
{
__asm volatile("outl %0,%w1" : : "a" (data), "id" (port));
}
static __inline void
__outl(unsigned port, u_int32_t data)
{
__asm volatile("outl %0,%w1" : : "a" (data), "d" (port));
}
static __inline void
outsl(unsigned port, const void *addr, int cnt)
{
void *dummy1;
int dummy2;
__asm volatile("cld\n\trep\n\toutsl" :
"=S" (dummy1), "=c" (dummy2) :
"d" (port), "0" (addr), "1" (cnt));
}
void outb(unsigned, uint8_t);
void outsb(unsigned, void *, int);
void outw(unsigned, uint16_t);
void outsw(unsigned, void *, int);
void outl(unsigned, uint32_t);
void outsl(unsigned, void *, int);
#endif /* _X86_PIO_H_ */

8
sys/arch/x86/include/specialreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: specialreg.h,v 1.18 2007/07/11 11:56:36 njoly Exp $ */
/* $NetBSD: specialreg.h,v 1.19 2007/09/26 19:48:38 ad Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@ -199,12 +199,6 @@
#define CPUID2EXTFAMILY(cpuid) (((cpuid) >> 20) & 0xff)
#define CPUID2EXTMODEL(cpuid) (((cpuid) >> 16) & 0xf)
#define CPUID(code, eax, ebx, ecx, edx) \
__asm("cpuid" \
: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \
: "a" (code));
/*
* Model-specific registers for the i386 family
*/

30
sys/arch/x86/isa/clock.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: clock.c,v 1.9 2007/07/09 20:52:37 ad Exp $ */
/* $NetBSD: clock.c,v 1.10 2007/09/26 19:48:42 ad Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
@ -121,7 +121,7 @@ WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.9 2007/07/09 20:52:37 ad Exp $");
__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.10 2007/09/26 19:48:42 ad Exp $");
/* #define CLOCKDEBUG */
/* #define CLOCK_PARANOIA */
@ -174,14 +174,6 @@ static int ppi_attached;
static pcppi_tag_t ppicookie;
#endif /* PCPPI */
#ifdef __x86_64__
#define READ_FLAGS() read_rflags()
#define WRITE_FLAGS(x) write_rflags(x)
#else /* i386 architecture processor */
#define READ_FLAGS() read_eflags()
#define WRITE_FLAGS(x) write_eflags(x)
#endif
#ifdef CLOCKDEBUG
int clock_debug = 0;
#define DPRINTF(arg) if (clock_debug) printf arg
@ -269,8 +261,8 @@ gettick_broken_latch(void)
int w1, w2, w3;
/* Don't want someone screwing with the counter while we're here. */
flags = READ_FLAGS();
disable_intr();
flags = x86_read_psl();
x86_disable_intr();
v1 = inb(IO_TIMER1+TIMER_CNTR0);
v1 |= inb(IO_TIMER1+TIMER_CNTR0) << 8;
@ -279,7 +271,7 @@ gettick_broken_latch(void)
v3 = inb(IO_TIMER1+TIMER_CNTR0);
v3 |= inb(IO_TIMER1+TIMER_CNTR0) << 8;
WRITE_FLAGS(flags);
x86_write_psl(flags);
#ifdef CLOCK_PARANOIA
if (clock_debug) {
@ -432,8 +424,8 @@ i8254_get_timecount(struct timecounter *tc)
u_long flags;
/* Don't want someone screwing with the counter while we're here. */
flags = READ_FLAGS();
disable_intr();
flags = x86_read_psl();
x86_disable_intr();
__cpu_simple_lock(&tmr_lock);
/* Select timer0 and latch counter value. */
@ -452,7 +444,7 @@ i8254_get_timecount(struct timecounter *tc)
count += i8254_offset;
__cpu_simple_unlock(&tmr_lock);
WRITE_FLAGS(flags);
x86_write_psl(flags);
return (count);
}
@ -467,13 +459,13 @@ gettick(void)
return (gettick_broken_latch());
/* Don't want someone screwing with the counter while we're here. */
flags = READ_FLAGS();
disable_intr();
flags = x86_read_psl();
x86_disable_intr();
/* Select counter 0 and latch it. */
outb(IO_TIMER1+TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
lo = inb(IO_TIMER1+TIMER_CNTR0);
hi = inb(IO_TIMER1+TIMER_CNTR0);
WRITE_FLAGS(flags);
x86_write_psl(flags);
return ((hi << 8) | lo);
}

6
sys/arch/x86/x86/acpi_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: acpi_machdep.c,v 1.13 2007/02/15 18:18:21 ad Exp $ */
/* $NetBSD: acpi_machdep.c,v 1.14 2007/09/26 19:48:42 ad Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: acpi_machdep.c,v 1.13 2007/02/15 18:18:21 ad Exp $");
__KERNEL_RCSID(0, "$NetBSD: acpi_machdep.c,v 1.14 2007/09/26 19:48:42 ad Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -328,7 +328,7 @@ acpi_md_OsWritable(void *Pointer, UINT32 Length)
void
acpi_md_OsDisableInterrupt(void)
{
disable_intr();
x86_disable_intr();
}
void

134
sys/arch/x86/x86/bus_dma.c
View File

@ -1,12 +1,12 @@
/* $NetBSD: bus_dma.c,v 1.36 2007/08/29 23:38:05 ad Exp $ */
/* $NetBSD: bus_dma.c,v 1.37 2007/09/26 19:48:42 ad Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
* Copyright (c) 1996, 1997, 1998, 2007 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
* Simulation Facility, NASA Ames Research Center.
* Simulation Facility NASA Ames Research Center, and by Andrew Doran.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -38,7 +38,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.36 2007/08/29 23:38:05 ad Exp $");
__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.37 2007/09/26 19:48:42 ad Exp $");
/*
* The following is included because _bus_dma_uiomove is derived from
@ -1235,3 +1235,129 @@ _bus_dmatag_destroy(bus_dma_tag_t tag)
(tag->_tag_needs_free)--; /* one less reference */
}
}
void
bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t p, bus_addr_t o, bus_size_t l,
int ops)
{
if (ops & BUS_DMASYNC_POSTREAD)
x86_lfence();
if (t->_dmamap_sync)
(*t->_dmamap_sync)(t, p, o, l, ops);
}
int
bus_dmamap_create(bus_dma_tag_t tag, bus_size_t size, int nsegments,
bus_size_t maxsegsz, bus_size_t boundary, int flags,
bus_dmamap_t *dmamp)
{
return (*tag->_dmamap_create)(tag, size, nsegments, maxsegsz,
boundary, flags, dmamp);
}
void
bus_dmamap_destroy(bus_dma_tag_t tag, bus_dmamap_t dmam)
{
(*tag->_dmamap_destroy)(tag, dmam);
}
int
bus_dmamap_load(bus_dma_tag_t tag, bus_dmamap_t dmam, void *buf,
bus_size_t buflen, struct proc *p, int flags)
{
return (*tag->_dmamap_load)(tag, dmam, buf, buflen, p, flags);
}
int
bus_dmamap_load_mbuf(bus_dma_tag_t tag, bus_dmamap_t dmam,
struct mbuf *chain, int flags)
{
return (*tag->_dmamap_load_mbuf)(tag, dmam, chain, flags);
}
int
bus_dmamap_load_uio(bus_dma_tag_t tag, bus_dmamap_t dmam,
struct uio *uio, int flags)
{
return (*tag->_dmamap_load_uio)(tag, dmam, uio, flags);
}
int
bus_dmamap_load_raw(bus_dma_tag_t tag, bus_dmamap_t dmam,
bus_dma_segment_t *segs, int nsegs,
bus_size_t size, int flags)
{
return (*tag->_dmamap_load_raw)(tag, dmam, segs, nsegs,
size, flags);
}
void
bus_dmamap_unload(bus_dma_tag_t tag, bus_dmamap_t dmam)
{
(*tag->_dmamap_unload)(tag, dmam);
}
int
bus_dmamem_alloc(bus_dma_tag_t tag, bus_size_t size, bus_size_t alignment,
bus_size_t boundary, bus_dma_segment_t *segs, int nsegs,
int *rsegs, int flags)
{
return (*tag->_dmamem_alloc)(tag, size, alignment, boundary, segs,
nsegs, rsegs, flags);
}
void
bus_dmamem_free(bus_dma_tag_t tag, bus_dma_segment_t *segs, int nsegs)
{
(*tag->_dmamem_free)(tag, segs, nsegs);
}
int
bus_dmamem_map(bus_dma_tag_t tag, bus_dma_segment_t *segs, int nsegs,
size_t size, void **kvap, int flags)
{
return (*tag->_dmamem_map)(tag, segs, nsegs, size, kvap, flags);
}
void
bus_dmamem_unmap(bus_dma_tag_t tag, void *kva, size_t size)
{
(*tag->_dmamem_unmap)(tag, kva, size);
}
paddr_t
bus_dmamem_mmap(bus_dma_tag_t tag, bus_dma_segment_t *segs, int nsegs,
off_t off, int prot, int flags)
{
return (*tag->_dmamem_mmap)(tag, segs, nsegs, off, prot, flags);
}
int
bus_dmatag_subregion(bus_dma_tag_t tag, bus_addr_t min_addr,
bus_addr_t max_addr, bus_dma_tag_t *newtag, int flags)
{
return (*tag->_dmatag_subregion)(tag, min_addr, max_addr, newtag,
flags);
}
void
bus_dmatag_destroy(bus_dma_tag_t tag)
{
(*tag->_dmatag_destroy)(tag);
}

331
sys/arch/x86/x86/bus_space.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: bus_space.c,v 1.9 2007/08/29 23:38:05 ad Exp $ */
/* $NetBSD: bus_space.c,v 1.10 2007/09/26 19:48:42 ad Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
@ -38,7 +38,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: bus_space.c,v 1.9 2007/08/29 23:38:05 ad Exp $");
__KERNEL_RCSID(0, "$NetBSD: bus_space.c,v 1.10 2007/09/26 19:48:42 ad Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -50,9 +50,39 @@ __KERNEL_RCSID(0, "$NetBSD: bus_space.c,v 1.9 2007/08/29 23:38:05 ad Exp $");
#include <dev/isa/isareg.h>
#include <machine/bus.h>
#include <machine/pio.h>
#include <machine/isa_machdep.h>
#include <machine/atomic.h>
#ifdef XEN
#include <machine/hypervisor.h>
#include <machine/xenpmap.h>
#define pmap_extract(a, b, c) pmap_extract_ma(a, b, c)
#endif
/*
* Macros for sanity-checking the aligned-ness of pointers passed to
* bus space ops. These are not strictly necessary on the x86, but
* could lead to performance improvements, and help catch problems
* with drivers that would creep up on other architectures.
*/
#ifdef BUS_SPACE_DEBUG
#define BUS_SPACE_ALIGNED_ADDRESS(p, t) \
((((u_long)(p)) & (sizeof(t)-1)) == 0)
#define BUS_SPACE_ADDRESS_SANITY(p, t, d) \
({ \
if (BUS_SPACE_ALIGNED_ADDRESS((p), t) == 0) { \
printf("%s 0x%lx not aligned to %d bytes %s:%d\n", \
d, (u_long)(p), sizeof(t), __FILE__, __LINE__); \
} \
(void) 0; \
})
#else
#define BUS_SPACE_ADDRESS_SANITY(p,t,d) (void) 0
#endif /* BUS_SPACE_DEBUG */
/*
* Extent maps to manage I/O and memory space. Allocate
* storage for 8 regions in each, initially. Later, ioport_malloc_safe
@ -94,6 +124,28 @@ x86_bus_space_init()
iomem_ex = extent_create("iomem", 0x0, 0xffffffff, M_DEVBUF,
(void *)iomem_ex_storage, sizeof(iomem_ex_storage),
EX_NOCOALESCE|EX_NOWAIT);
#ifdef XEN
/* We are privileged guest os - should have IO privileges. */
if (xen_start_info.flags & SIF_PRIVILEGED) {
#ifdef XEN3
struct physdev_op physop;
physop.cmd = PHYSDEVOP_SET_IOPL;
physop.u.set_iopl.iopl = 1;
if (HYPERVISOR_physdev_op(&physop) != 0)
panic("Unable to obtain IOPL, "
"despite being SIF_PRIVILEGED");
#else
dom0_op_t op;
op.cmd = DOM0_IOPL;
op.u.iopl.domain = DOMID_SELF;
op.u.iopl.iopl = 1;
if (HYPERVISOR_dom0_op(&op) != 0)
panic("Unable to obtain IOPL, "
"despite being SIF_PRIVILEGED");
#endif
}
#endif /* XEN */
}
void
@ -104,7 +156,7 @@ x86_bus_space_mallocok()
}
int
x86_memio_map(t, bpa, size, flags, bshp)
bus_space_map(t, bpa, size, flags, bshp)
bus_space_tag_t t;
bus_addr_t bpa;
bus_size_t size;
@ -143,10 +195,12 @@ x86_memio_map(t, bpa, size, flags, bshp)
return (0);
}
#ifndef XEN
if (bpa >= IOM_BEGIN && (bpa + size) <= IOM_END) {
*bshp = (bus_space_handle_t)ISA_HOLE_VADDR(bpa);
return(0);
}
#endif /* !XEN */
/*
* For memory space, map the bus physical address to
@ -194,7 +248,7 @@ _x86_memio_map(t, bpa, size, flags, bshp)
}
int
x86_memio_alloc(t, rstart, rend, size, alignment, boundary, flags,
bus_space_alloc(t, rstart, rend, size, alignment, boundary, flags,
bpap, bshp)
bus_space_tag_t t;
bus_addr_t rstart, rend;
@ -274,6 +328,9 @@ x86_mem_add_mapping(bpa, size, cacheable, bshp)
u_long pa, endpa;
vaddr_t va, sva;
pt_entry_t *pte, xpte;
#ifdef XEN
int32_t cpumask = 0;
#endif
pa = x86_trunc_page(bpa);
endpa = x86_round_page(bpa + size);
@ -283,18 +340,23 @@ x86_mem_add_mapping(bpa, size, cacheable, bshp)
panic("x86_mem_add_mapping: overflow");
#endif
sva = uvm_km_alloc(kernel_map, endpa - pa, 0,
UVM_KMF_VAONLY | UVM_KMF_NOWAIT);
if (sva == 0)
return (ENOMEM);
#ifdef XEN
if (bpa >= IOM_BEGIN && (bpa + size) <= IOM_END) {
sva = (vaddr_t)ISA_HOLE_VADDR(pa);
} else
#endif /* XEN */
{
sva = uvm_km_alloc(kernel_map, endpa - pa, 0,
UVM_KMF_VAONLY | UVM_KMF_NOWAIT);
if (sva == 0)
return (ENOMEM);
}
*bshp = (bus_space_handle_t)(sva + (bpa & PGOFSET));
va = sva;
xpte = 0;
for (; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) {
pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE);
/*
* PG_N doesn't exist on 386's, so we assume that
* the mainboard has wired up device space non-cacheable
@ -303,6 +365,24 @@ x86_mem_add_mapping(bpa, size, cacheable, bshp)
* XXX should hand this bit to pmap_kenter_pa to
* save the extra invalidate!
*/
#ifdef XEN
pmap_kenter_ma(va, pa, VM_PROT_READ | VM_PROT_WRITE);
if (pmap_cpu_has_pg_n()) {
pte = kvtopte(va);
pt_entry_t *maptp;
maptp = (pt_entry_t *)vtomach((vaddr_t)pte);
if (cacheable)
PTE_CLEARBITS(pte, maptp, PG_N);
else
PTE_SETBITS(pte, maptp, PG_N);
pmap_tlb_shootdown(pmap_kernel(), va, *pte,
&cpumask);
}
}
pmap_tlb_shootnow(cpumask);
#else /* XEN */
pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE);
if (pmap_cpu_has_pg_n()) {
pte = kvtopte(va);
if (cacheable)
@ -312,8 +392,8 @@ x86_mem_add_mapping(bpa, size, cacheable, bshp)
xpte |= *pte;
}
}
pmap_tlb_shootdown(pmap_kernel(), sva, sva + (endpa - pa), xpte);
#endif /* XEN */
pmap_update(pmap_kernel());
return 0;
@ -381,7 +461,7 @@ _x86_memio_unmap(t, bsh, size, adrp)
}
void
x86_memio_unmap(t, bsh, size)
bus_space_unmap(t, bsh, size)
bus_space_tag_t t;
bus_space_handle_t bsh;
bus_size_t size;
@ -436,18 +516,18 @@ ok:
}
void
x86_memio_free(t, bsh, size)
bus_space_free(t, bsh, size)
bus_space_tag_t t;
bus_space_handle_t bsh;
bus_size_t size;
{
/* x86_memio_unmap() does all that we need to do. */
x86_memio_unmap(t, bsh, size);
/* bus_space_unmap() does all that we need to do. */
bus_space_unmap(t, bsh, size);
}
int
x86_memio_subregion(bus_space_tag_t t, bus_space_handle_t bsh,
bus_space_subregion(bus_space_tag_t t, bus_space_handle_t bsh,
bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp)
{
@ -456,7 +536,7 @@ x86_memio_subregion(bus_space_tag_t t, bus_space_handle_t bsh,
}
paddr_t
x86_memio_mmap(bus_space_tag_t t, bus_addr_t addr, off_t off, int prot,
bus_space_mmap(bus_space_tag_t t, bus_addr_t addr, off_t off, int prot,
int flags)
{
@ -473,3 +553,220 @@ x86_memio_mmap(bus_space_tag_t t, bus_addr_t addr, off_t off, int prot,
*/
return (x86_btop(addr + off));
}
void
bus_space_set_multi_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
u_int8_t v, size_t c)
{
bus_addr_t addr = h + o;
if (t == X86_BUS_SPACE_IO)
while (c--)
outb(addr, v);
else
while (c--)
*(volatile u_int8_t *)(addr) = v;
}
void
bus_space_set_multi_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
u_int16_t v, size_t c)
{
bus_addr_t addr = h + o;
BUS_SPACE_ADDRESS_SANITY(addr, u_int16_t, "bus addr");
if (t == X86_BUS_SPACE_IO)
while (c--)
outw(addr, v);
else
while (c--)
*(volatile u_int16_t *)(addr) = v;
}
void
bus_space_set_multi_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
u_int32_t v, size_t c)
{
bus_addr_t addr = h + o;
BUS_SPACE_ADDRESS_SANITY(addr, u_int32_t, "bus addr");
if (t == X86_BUS_SPACE_IO)
while (c--)
outl(addr, v);
else
while (c--)
*(volatile u_int32_t *)(addr) = v;
}
void
bus_space_set_region_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
u_int8_t v, size_t c)
{
bus_addr_t addr = h + o;
if (t == X86_BUS_SPACE_IO)
for (; c != 0; c--, addr++)
outb(addr, v);
else
for (; c != 0; c--, addr++)
*(volatile u_int8_t *)(addr) = v;
}
void
bus_space_set_region_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
u_int16_t v, size_t c)
{
bus_addr_t addr = h + o;
BUS_SPACE_ADDRESS_SANITY(addr, u_int16_t, "bus addr");
if (t == X86_BUS_SPACE_IO)
for (; c != 0; c--, addr += 2)
outw(addr, v);
else
for (; c != 0; c--, addr += 2)
*(volatile u_int16_t *)(addr) = v;
}
void
bus_space_set_region_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
u_int32_t v, size_t c)
{
bus_addr_t addr = h + o;
BUS_SPACE_ADDRESS_SANITY(addr, u_int32_t, "bus addr");
if (t == X86_BUS_SPACE_IO)
for (; c != 0; c--, addr += 4)
outl(addr, v);
else
for (; c != 0; c--, addr += 4)
*(volatile u_int32_t *)(addr) = v;
}
void
bus_space_copy_region_1(bus_space_tag_t t, bus_space_handle_t h1,
bus_size_t o1, bus_space_handle_t h2,
bus_size_t o2, size_t c)
{
bus_addr_t addr1 = h1 + o1;
bus_addr_t addr2 = h2 + o2;
if (t == X86_BUS_SPACE_IO) {
if (addr1 >= addr2) {
/* src after dest: copy forward */
for (; c != 0; c--, addr1++, addr2++)
outb(addr2, inb(addr1));
} else {
/* dest after src: copy backwards */
for (addr1 += (c - 1), addr2 += (c - 1);
c != 0; c--, addr1--, addr2--)
outb(addr2, inb(addr1));
}
} else {
if (addr1 >= addr2) {
/* src after dest: copy forward */
for (; c != 0; c--, addr1++, addr2++)
*(volatile u_int8_t *)(addr2) =
*(volatile u_int8_t *)(addr1);
} else {
/* dest after src: copy backwards */
for (addr1 += (c - 1), addr2 += (c - 1);
c != 0; c--, addr1--, addr2--)
*(volatile u_int8_t *)(addr2) =
*(volatile u_int8_t *)(addr1);
}
}
}
void
bus_space_copy_region_2(bus_space_tag_t t, bus_space_handle_t h1,
bus_size_t o1, bus_space_handle_t h2,
bus_size_t o2, size_t c)
{
bus_addr_t addr1 = h1 + o1;
bus_addr_t addr2 = h2 + o2;
BUS_SPACE_ADDRESS_SANITY(addr1, u_int16_t, "bus addr 1");
BUS_SPACE_ADDRESS_SANITY(addr2, u_int16_t, "bus addr 2");
if (t == X86_BUS_SPACE_IO) {
if (addr1 >= addr2) {
/* src after dest: copy forward */
for (; c != 0; c--, addr1 += 2, addr2 += 2)
outw(addr2, inw(addr1));
} else {
/* dest after src: copy backwards */
for (addr1 += 2 * (c - 1), addr2 += 2 * (c - 1);
c != 0; c--, addr1 -= 2, addr2 -= 2)
outw(addr2, inw(addr1));
}
} else {
if (addr1 >= addr2) {
/* src after dest: copy forward */
for (; c != 0; c--, addr1 += 2, addr2 += 2)
*(volatile u_int16_t *)(addr2) =
*(volatile u_int16_t *)(addr1);
} else {
/* dest after src: copy backwards */
for (addr1 += 2 * (c - 1), addr2 += 2 * (c - 1);
c != 0; c--, addr1 -= 2, addr2 -= 2)
*(volatile u_int16_t *)(addr2) =
*(volatile u_int16_t *)(addr1);
}
}
}
void
bus_space_copy_region_4(bus_space_tag_t t, bus_space_handle_t h1,
bus_size_t o1, bus_space_handle_t h2,
bus_size_t o2, size_t c)
{
bus_addr_t addr1 = h1 + o1;
bus_addr_t addr2 = h2 + o2;
BUS_SPACE_ADDRESS_SANITY(addr1, u_int32_t, "bus addr 1");
BUS_SPACE_ADDRESS_SANITY(addr2, u_int32_t, "bus addr 2");
if (t == X86_BUS_SPACE_IO) {
if (addr1 >= addr2) {
/* src after dest: copy forward */
for (; c != 0; c--, addr1 += 4, addr2 += 4)
outl(addr2, inl(addr1));
} else {
/* dest after src: copy backwards */
for (addr1 += 4 * (c - 1), addr2 += 4 * (c - 1);
c != 0; c--, addr1 -= 4, addr2 -= 4)
outl(addr2, inl(addr1));
}
} else {
if (addr1 >= addr2) {
/* src after dest: copy forward */
for (; c != 0; c--, addr1 += 4, addr2 += 4)
*(volatile u_int32_t *)(addr2) =
*(volatile u_int32_t *)(addr1);
} else {
/* dest after src: copy backwards */
for (addr1 += 4 * (c - 1), addr2 += 4 * (c - 1);
c != 0; c--, addr1 -= 4, addr2 -= 4)
*(volatile u_int32_t *)(addr2) =
*(volatile u_int32_t *)(addr1);
}
}
}
void
bus_space_barrier(bus_space_tag_t tag, bus_space_handle_t bsh,
bus_size_t offset, bus_size_t len, int flags)
{
/* Function call is enough to prevent reordering of loads. */
}
void *
bus_space_vaddr(bus_space_tag_t tag, bus_space_handle_t bsh)
{
return tag == X86_BUS_SPACE_MEM ? (void *)bsh : NULL;
}

16
sys/arch/x86/x86/cacheinfo.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cacheinfo.c,v 1.10 2006/08/28 00:20:47 christos Exp $ */
/* $NetBSD: cacheinfo.c,v 1.11 2007/09/26 19:48:42 ad Exp $ */
/*-
* Copyright (c) 2000 The NetBSD Foundation, Inc.
@ -37,7 +37,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: cacheinfo.c,v 1.10 2006/08/28 00:20:47 christos Exp $");
__KERNEL_RCSID(0, "$NetBSD: cacheinfo.c,v 1.11 2007/09/26 19:48:42 ad Exp $");
#include <sys/types.h>
#include <sys/systm.h>
@ -184,7 +184,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
/*
* Determine the largest extended function value.
*/
CPUID(0x80000000, descs[0], descs[1], descs[2], descs[3]);
x86_cpuid(0x80000000, descs);
lfunc = descs[0];
/*
@ -195,7 +195,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
return;
}
CPUID(0x80000005, descs[0], descs[1], descs[2], descs[3]);
x86_cpuid(0x80000005, descs);
/*
* K6-III and higher have large page TLBs.
@ -240,7 +240,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
return;
}
CPUID(0x80000006, descs[0], descs[1], descs[2], descs[3]);
x86_cpuid(0x80000006, descs);
cai = &ci->ci_cinfo[CAI_L2CACHE];
cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]);
@ -270,7 +270,7 @@ via_cpu_cacheinfo(struct cpu_info *ci)
/*
* Determine the largest extended function value.
*/
CPUID(0x80000000, descs[0], descs[1], descs[2], descs[3]);
x86_cpuid(0x80000000, descs);
lfunc = descs[0];
/*
@ -281,7 +281,7 @@ via_cpu_cacheinfo(struct cpu_info *ci)
return;
}
CPUID(0x80000005, descs[0], descs[1], descs[2], descs[3]);
x86_cpuid(0x80000005, descs);
cai = &ci->ci_cinfo[CAI_ITLB];
cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]);
@ -319,7 +319,7 @@ via_cpu_cacheinfo(struct cpu_info *ci)
return;
}
CPUID(0x80000006, descs[0], descs[1], descs[2], descs[3]);
x86_cpuid(0x80000006, descs);
cai = &ci->ci_cinfo[CAI_L2CACHE];
if (model >= 9) {

6
sys/arch/x86/x86/cpu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.c,v 1.2 2007/08/29 23:38:05 ad Exp $ */
/* $NetBSD: cpu.c,v 1.3 2007/09/26 19:48:42 ad Exp $ */
/*-
* Copyright (c) 2000 The NetBSD Foundation, Inc.
@ -71,7 +71,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.2 2007/08/29 23:38:05 ad Exp $");
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.3 2007/09/26 19:48:42 ad Exp $");
#include "opt_ddb.h"
#include "opt_multiprocessor.h"
@ -662,7 +662,7 @@ cpu_hatch(void *v)
#else
lcr8(0);
#endif
enable_intr();
x86_enable_intr();
splx(s);
aprint_debug("%s: CPU %ld running\n", ci->ci_dev->dv_xname,

10
sys/arch/x86/x86/errata.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: errata.c,v 1.8 2007/03/25 20:49:05 tls Exp $ */
/* $NetBSD: errata.c,v 1.9 2007/09/26 19:48:43 ad Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
@ -52,7 +52,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: errata.c,v 1.8 2007/03/25 20:49:05 tls Exp $");
__KERNEL_RCSID(0, "$NetBSD: errata.c,v 1.9 2007/09/26 19:48:43 ad Exp $");
#include "opt_multiprocessor.h"
#ifdef i386
@ -274,7 +274,7 @@ x86_errata_setmsr(struct cpu_info *ci, errata_t *e)
void
x86_errata(struct cpu_info *ci, int vendor)
{
uint32_t code, dummy;
uint32_t descs[4];
errata_t *e, *ex;
cpurev_t rev;
int i, j, upgrade;
@ -283,12 +283,12 @@ x86_errata(struct cpu_info *ci, int vendor)
if (vendor != CPUVENDOR_AMD)
return;
CPUID(0x80000001, code, dummy, dummy, dummy);
x86_cpuid(0x80000001, descs);
for (i = 0;; i += 2) {
if ((rev = cpurevs[i]) == OINK)
return;
if (cpurevs[i + 1] == code)
if (cpurevs[i + 1] == descs[0])
break;
}

8
sys/arch/x86/x86/i8259.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: i8259.c,v 1.10 2006/11/16 01:32:39 christos Exp $ */
/* $NetBSD: i8259.c,v 1.11 2007/09/26 19:48:43 ad Exp $ */
/*
* Copyright 2002 (c) Wasabi Systems, Inc.
@ -70,7 +70,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: i8259.c,v 1.10 2006/11/16 01:32:39 christos Exp $");
__KERNEL_RCSID(0, "$NetBSD: i8259.c,v 1.11 2007/09/26 19:48:43 ad Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -215,7 +215,7 @@ i8259_hwunmask(struct pic *pic, int pin)
unsigned port;
u_int8_t byte;
disable_intr(); /* XXX */
x86_disable_intr(); /* XXX */
i8259_imen &= ~(1 << pin);
#ifdef PIC_MASKDELAY
delay(10);
@ -228,7 +228,7 @@ i8259_hwunmask(struct pic *pic, int pin)
byte = i8259_imen & 0xff;
}
outb(port, byte);
enable_intr();
x86_enable_intr();
}
static void

6
sys/arch/x86/x86/iclockmod.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: iclockmod.c,v 1.7 2007/04/04 01:50:15 rmind Exp $ */
/* $NetBSD: iclockmod.c,v 1.8 2007/09/26 19:48:43 ad Exp $ */
/* $OpenBSD: p4tcc.c,v 1.13 2006/12/20 17:50:40 gwk Exp $ */
/*
@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: iclockmod.c,v 1.7 2007/04/04 01:50:15 rmind Exp $");
__KERNEL_RCSID(0, "$NetBSD: iclockmod.c,v 1.8 2007/09/26 19:48:43 ad Exp $");
#include "opt_intel_odcm.h"
@ -153,7 +153,7 @@ clockmod_init_main(void)
char *freq_names;
int i;
CPUID(1, regs[0], regs[1], regs[2], regs[3]);
x86_cpuid(1, regs);
if ((regs[3] & (CPUID_ACPI|CPUID_TM)) != (CPUID_ACPI|CPUID_TM))
return;

35
sys/arch/x86/x86/idle_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: idle_machdep.c,v 1.3 2007/08/29 23:38:06 ad Exp $ */
/* $NetBSD: idle_machdep.c,v 1.4 2007/09/26 19:48:43 ad Exp $ */
/*-
* Copyright (c)2002, 2006, 2007 YAMAMOTO Takashi,
@ -28,7 +28,7 @@
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: idle_machdep.c,v 1.3 2007/08/29 23:38:06 ad Exp $");
__KERNEL_RCSID(0, "$NetBSD: idle_machdep.c,v 1.4 2007/09/26 19:48:43 ad Exp $");
#include <sys/param.h>
#include <sys/cpu.h>
@ -37,35 +37,15 @@ __KERNEL_RCSID(0, "$NetBSD: idle_machdep.c,v 1.3 2007/08/29 23:38:06 ad Exp $");
#if defined(I686_CPU) || defined(__x86_64__)
static void
monitor(const void *addr)
{
uint32_t hint = 0;
uint32_t ext = 0;
__asm __volatile (".byte 0x0f, 0x01, 0xc8" /* monitor */
:: "a"(addr), "c"(ext), "d"(hint));
}
static void
mwait(void)
{
uint32_t hint = 0;
uint32_t ext = 0;
__asm __volatile (".byte 0x0f, 0x01, 0xc9" /* mwait */
:: "a"(hint), "c"(ext));
}
static void
cpu_idle_mwait(struct cpu_info *ci)
{
monitor(&ci->ci_want_resched);
x86_monitor(&ci->ci_want_resched, 0, 0);
if (__predict_false(ci->ci_want_resched)) {
return;
}
mwait();
x86_mwait(0, 0);
}
#endif /* defined(I686_CPU) || defined(__x86_64__) */
@ -74,12 +54,11 @@ static void
cpu_idle_halt(struct cpu_info *ci)
{
disable_intr();
__insn_barrier();
x86_disable_intr();
if (!__predict_false(ci->ci_want_resched)) {
__asm __volatile ("sti; hlt");
x86_stihlt();
} else {
enable_intr();
x86_enable_intr();
}
}

20
sys/arch/x86/x86/ioapic.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: ioapic.c,v 1.19 2007/05/17 14:51:35 yamt Exp $ */
/* $NetBSD: ioapic.c,v 1.20 2007/09/26 19:48:43 ad Exp $ */
/*-
* Copyright (c) 2000 The NetBSD Foundation, Inc.
@ -72,7 +72,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: ioapic.c,v 1.19 2007/05/17 14:51:35 yamt Exp $");
__KERNEL_RCSID(0, "$NetBSD: ioapic.c,v 1.20 2007/09/26 19:48:43 ad Exp $");
#include "opt_ddb.h"
@ -81,19 +81,17 @@ __KERNEL_RCSID(0, "$NetBSD: ioapic.c,v 1.19 2007/05/17 14:51:35 yamt Exp $");
#include <sys/device.h>
#include <sys/malloc.h>
#include <uvm/uvm_extern.h>
#include <machine/bus.h>
#include <machine/isa_machdep.h> /* XXX intrhand */
#include <uvm/uvm_extern.h>
#include <machine/i82093reg.h>
#include <machine/i82093var.h>
#include <machine/i82489reg.h>
#include <machine/i82489var.h>
#include <machine/pmap.h>
#include <machine/mpbiosvar.h>
#include <machine/pio.h>
#include <machine/pmap.h>
#include "acpi.h"
#include "opt_mpbios.h"
@ -132,8 +130,8 @@ ioapic_lock(struct ioapic_softc *sc)
{
u_long flags;
flags = read_psl();
disable_intr();
flags = x86_read_psl();
x86_disable_intr();
__cpu_simple_lock(&sc->sc_pic.pic_lock);
return flags;
}
@ -142,7 +140,7 @@ static inline void
ioapic_unlock(struct ioapic_softc *sc, u_long flags)
{
__cpu_simple_unlock(&sc->sc_pic.pic_lock);
write_psl(flags);
x86_write_psl(flags);
}
#ifndef _IOAPIC_CUSTOM_RW

8
sys/arch/x86/x86/lapic.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: lapic.c,v 1.22 2007/08/29 23:38:06 ad Exp $ */
/* $NetBSD: lapic.c,v 1.23 2007/09/26 19:48:43 ad Exp $ */
/*-
* Copyright (c) 2000 The NetBSD Foundation, Inc.
@ -39,7 +39,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: lapic.c,v 1.22 2007/08/29 23:38:06 ad Exp $");
__KERNEL_RCSID(0, "$NetBSD: lapic.c,v 1.23 2007/09/26 19:48:43 ad Exp $");
#include "opt_ddb.h"
#include "opt_mpbios.h" /* for MPDEBUG */
@ -107,7 +107,7 @@ lapic_map(lapic_base)
pt_entry_t *pte;
vaddr_t va = (vaddr_t)&local_apic;
disable_intr();
x86_disable_intr();
s = lapic_tpr;
/*
@ -128,7 +128,7 @@ lapic_map(lapic_base)
#endif
lapic_tpr = s;
enable_intr();
x86_enable_intr();
}
/*

5
sys/arch/x86/x86/mpbios.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mpbios.c,v 1.37 2007/08/07 11:25:40 ad Exp $ */
/* $NetBSD: mpbios.c,v 1.38 2007/09/26 19:48:43 ad Exp $ */
/*-
* Copyright (c) 2000 The NetBSD Foundation, Inc.
@ -103,7 +103,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: mpbios.c,v 1.37 2007/08/07 11:25:40 ad Exp $");
__KERNEL_RCSID(0, "$NetBSD: mpbios.c,v 1.38 2007/09/26 19:48:43 ad Exp $");
#include "acpi.h"
#include "lapic.h"
@ -123,6 +123,7 @@ __KERNEL_RCSID(0, "$NetBSD: mpbios.c,v 1.37 2007/08/07 11:25:40 ad Exp $");
#include <machine/cpuvar.h>
#include <machine/bus.h>
#include <machine/mpbiosvar.h>
#include <machine/pio.h>
#include <machine/i82093reg.h>
#include <machine/i82093var.h>

8
sys/arch/x86/x86/mtrr_i686.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mtrr_i686.c,v 1.9 2007/03/20 18:05:25 drochner Exp $ */
/* $NetBSD: mtrr_i686.c,v 1.10 2007/09/26 19:48:43 ad Exp $ */
/*-
* Copyright (c) 2000 The NetBSD Foundation, Inc.
@ -37,7 +37,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: mtrr_i686.c,v 1.9 2007/03/20 18:05:25 drochner Exp $");
__KERNEL_RCSID(0, "$NetBSD: mtrr_i686.c,v 1.10 2007/09/26 19:48:43 ad Exp $");
#include "opt_multiprocessor.h"
@ -166,7 +166,7 @@ i686_mtrr_reload(int synch)
* 2. Disable interrupts
*/
disable_intr();
x86_disable_intr();
#ifdef MULTIPROCESSOR
if (synch) {
@ -281,7 +281,7 @@ i686_mtrr_reload(int synch)
/*
* 15. Enable interrupts.
*/
enable_intr();
x86_enable_intr();
}
static void

10
sys/arch/x86/x86/patch.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: patch.c,v 1.3 2007/05/17 14:51:35 yamt Exp $ */
/* $NetBSD: patch.c,v 1.4 2007/09/26 19:48:43 ad Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
@ -41,7 +41,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: patch.c,v 1.3 2007/05/17 14:51:35 yamt Exp $");
__KERNEL_RCSID(0, "$NetBSD: patch.c,v 1.4 2007/09/26 19:48:43 ad Exp $");
#include "opt_multiprocessor.h"
#include "opt_lockdebug.h"
@ -104,8 +104,8 @@ patchfunc(void *from_s, void *from_e, void *to_s, void *to_e,
(uintptr_t)to_e - (uintptr_t)to_s)
panic("patchfunc: sizes do not match (from=%p)", from_s);
psl = read_psl();
disable_intr();
psl = x86_read_psl();
x86_disable_intr();
memcpy(to_s, from_s, (uintptr_t)to_e - (uintptr_t)to_s);
if (pcrel != NULL) {
ptr = pcrel;
@ -120,7 +120,7 @@ patchfunc(void *from_s, void *from_e, void *to_s, void *to_e,
((uint32_t)(uintptr_t)from_s - (uint32_t)(uintptr_t)to_s);
}
x86_flush();
write_psl(psl);
x86_write_psl(psl);
}
static inline void __attribute__ ((__unused__))

8
sys/arch/x86/x86/powernow_common.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: powernow_common.c,v 1.5 2007/09/10 10:35:52 cube Exp $ */
/* $NetBSD: powernow_common.c,v 1.6 2007/09/26 19:48:43 ad Exp $ */
/*
* Copyright (c) 2006 The NetBSD Foundation.
@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: powernow_common.c,v 1.5 2007/09/10 10:35:52 cube Exp $");
__KERNEL_RCSID(0, "$NetBSD: powernow_common.c,v 1.6 2007/09/26 19:48:43 ad Exp $");
#include <sys/types.h>
#include <sys/param.h>
@ -45,12 +45,12 @@ powernow_probe(struct cpu_info *ci)
uint32_t regs[4];
char line[80];
CPUID(0x80000000, regs[0], regs[1], regs[2], regs[3]);
x86_cpuid(0x80000000, regs);
/* We need CPUID(0x80000007) */
if (regs[0] < 0x80000007)
return 0;
CPUID(0x80000007, regs[0], regs[1], regs[2], regs[3]);
x86_cpuid(0x80000007, regs);
bitmask_snprintf(regs[3], "\20\6STC\5TM\4TTP\3VID\2FID\1TS", line,
sizeof line);

18
sys/arch/x86/x86/x86_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: x86_machdep.c,v 1.11 2007/08/29 23:38:06 ad Exp $ */
/* $NetBSD: x86_machdep.c,v 1.12 2007/09/26 19:48:44 ad Exp $ */
/*-
* Copyright (c) 2005 The NetBSD Foundation, Inc.
@ -37,7 +37,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: x86_machdep.c,v 1.11 2007/08/29 23:38:06 ad Exp $");
__KERNEL_RCSID(0, "$NetBSD: x86_machdep.c,v 1.12 2007/09/26 19:48:44 ad Exp $");
#include <sys/types.h>
#include <sys/param.h>
@ -115,20 +115,6 @@ check_pa_acc(paddr_t pa, vm_prot_t prot)
KAUTH_MACHDEP_UNMANAGEDMEM, NULL, NULL, NULL, NULL);
}
/*
* Issue the pause instruction (rep; nop) which acts as a hint to
* HyperThreading processors that we are spinning on a lock.
*
* Not defined as an inline, because even if the CPU does not support
* HT the delay resulting from a function call is useful for spin lock
* back off.
*/
void
x86_pause(void)
{
__asm volatile("pause");
}
/*
* This function is to initialize the mutex used by x86/msr_ipifuncs.c.
*/

7
sys/arch/xen/conf/files.xen
View File

@ -1,4 +1,4 @@
# $NetBSD: files.xen,v 1.63 2007/07/07 05:13:17 tsutsui Exp $
# $NetBSD: files.xen,v 1.64 2007/09/26 19:48:44 ad Exp $
# NetBSD: files.x86,v 1.10 2003/10/08 17:30:00 bouyer Exp
# NetBSD: files.i386,v 1.254 2004/03/25 23:32:10 jmc Exp
@ -33,6 +33,8 @@ defflag opt_pcifixup.h PCI_ADDR_FIXUP PCI_BUS_FIXUP
defparam PCI_CONF_MODE
file arch/xen/i386/autoconf.c
file arch/i386/i386/busfunc.S
file arch/i386/i386/cpufunc.S
file arch/i386/i386/db_dbgreg.S ddb | kstack_check_dr0
file arch/i386/i386/db_disasm.c ddb
file arch/i386/i386/db_interface.c ddb
@ -58,6 +60,7 @@ file arch/xen/i386/trap.c
file arch/i386/i386/vm_machdep.c
file arch/xen/i386/xen_machdep.c
file arch/xen/i386/xen_intr.c
file arch/xen/i386/xenfunc.c
file arch/i386/i386/lock_stubs.S
file arch/xen/xen/xen_debug.c
@ -98,7 +101,7 @@ file dev/md_root.c memory_disk_hooks
file arch/x86/x86/bus_dma.c pci
file arch/xen/x86/xen_bus_dma.c pci
file arch/xen/x86/bus_space.c pci
file arch/x86/x86/bus_space.c pci
file arch/x86/x86/cacheinfo.c
file arch/xen/x86/consinit.c
file arch/xen/x86/intr.c

28
sys/arch/xen/i386/cpu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.c,v 1.11 2007/05/17 14:51:35 yamt Exp $ */
/* $NetBSD: cpu.c,v 1.12 2007/09/26 19:48:38 ad Exp $ */
/* NetBSD: cpu.c,v 1.18 2004/02/20 17:35:01 yamt Exp */
/*-
@ -72,7 +72,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.11 2007/05/17 14:51:35 yamt Exp $");
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.12 2007/09/26 19:48:38 ad Exp $");
#include "opt_ddb.h"
#include "opt_multiprocessor.h"
@ -155,25 +155,19 @@ CFATTACH_DECL(vcpu, sizeof(struct cpu_softc),
* CPU, on uniprocessors). The CPU info list is initialized to
* point at it.
*/
#ifdef TRAPLOG
struct tlog tlog_primary;
struct cpu_info cpu_info_primary = {
0,
&cpu_info_primary,
(uint8_t *)&cpu_info_primary + 0x150,
&tlog_primary
.ci_self = &cpu_info_primary,
.ci_self150 = (uint8_t *)&cpu_info_primary + 0x150,
.ci_curlwp = &lwp0,
#ifdef TRAPLOG
.ci_tlog = &tlog_primary,
#endif
};
#else /* TRAPLOG */
struct cpu_info cpu_info_primary = {
0,
&cpu_info_primary,
(uint8_t *)&cpu_info_primary + 0x150,
};
#endif /* !TRAPLOG */
struct cpu_info phycpu_info_primary = {
0,
&phycpu_info_primary,
(uint8_t *)&cpu_info_primary + 0x150,
.ci_self = &phycpu_info_primary,
.ci_self150 = (uint8_t *)&phycpu_info_primary + 0x150,
.ci_curlwp = &lwp0,
};
struct cpu_info *cpu_info_list = &cpu_info_primary;

9
sys/arch/xen/i386/genassym.cf
View File

@ -1,4 +1,4 @@
# $NetBSD: genassym.cf,v 1.14 2007/09/25 17:08:09 ad Exp $
# $NetBSD: genassym.cf,v 1.15 2007/09/26 19:48:38 ad Exp $
# NetBSD: genassym.cf,v 1.40 2004/02/20 17:35:01 yamt Exp
#
@ -108,6 +108,7 @@ include <machine/pmap.h>
include <machine/vmparam.h>
include <machine/intr.h>
include <machine/types.h>
include <machine/specialreg.h>
ifdef XEN3
include <machine/xen3-public/sched.h>
@ -134,6 +135,8 @@ endif
include <machine/tlog.h>
include <x86/busdefs.h>
define PAGE_SIZE PAGE_SIZE
define LSRUN LSRUN
@ -353,3 +356,7 @@ endif
define HYPERVISOR_sched_op __HYPERVISOR_sched_op
define SCHEDOP_yield SCHEDOP_yield
define OPTERON_MSR_PASSCODE OPTERON_MSR_PASSCODE
define X86_BUS_SPACE_IO X86_BUS_SPACE_IO

125
sys/arch/xen/i386/identcpu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: identcpu.c,v 1.13 2007/02/22 06:48:54 thorpej Exp $ */
/* $NetBSD: identcpu.c,v 1.14 2007/09/26 19:48:39 ad Exp $ */
/* NetBSD: identcpu.c,v 1.16 2004/04/05 02:09:41 mrg Exp */
/*-
@ -38,7 +38,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.13 2007/02/22 06:48:54 thorpej Exp $");
__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.14 2007/09/26 19:48:39 ad Exp $");
#include "opt_cputype.h"
@ -605,14 +605,14 @@ via_cpu_probe(struct cpu_info *ci)
/*
* Determine the largest extended function value.
*/
CPUID(0x80000000, descs[0], descs[1], descs[2], descs[3]);
x86_cpuid(0x80000000, descs);
lfunc = descs[0];
/*
* Determine the extended feature flags.
*/
if (lfunc >= 0x80000001) {
CPUID(0x80000001, descs[0], descs[1], descs[2], descs[3]);
x86_cpuid(0x80000001, descs);
ci->ci_feature_flags |= descs[3];
}
}
@ -693,21 +693,25 @@ cpu_probe_base_features(struct cpu_info *ci)
u_int descs[4];
int iterations, i, j;
u_int8_t desc;
u_int32_t dummy1, dummy2, miscbytes;
u_int32_t miscbytes;
if (ci->ci_cpuid_level < 0)
return;
CPUID(0, ci->ci_cpuid_level,
ci->ci_vendor[0],
ci->ci_vendor[2],
ci->ci_vendor[1]);
x86_cpuid(0, descs);
ci->ci_cpuid_level = descs[0];
ci->ci_vendor[0] = descs[1];
ci->ci_vendor[2] = descs[2];
ci->ci_vendor[1] = descs[3];
ci->ci_vendor[3] = 0;
if (ci->ci_cpuid_level < 1)
return;
CPUID(1, ci->ci_signature, miscbytes, dummy1, ci->ci_feature_flags);
x86_cpuid(1, descs);
ci->ci_signature = descs[0];
miscbytes = descs[1];
ci->ci_feature_flags = descs[3];
/* Brand is low order 8 bits of ebx */
ci->ci_brand_id = miscbytes & 0xff;
@ -724,7 +728,7 @@ cpu_probe_base_features(struct cpu_info *ci)
* XXX This is kinda ugly, but hey, so is the architecture...
*/
CPUID(2, descs[0], descs[1], descs[2], descs[3]);
x86_cpuid(2, descs);
iterations = descs[0] & 0xff;
while (iterations-- > 0) {
@ -743,7 +747,7 @@ cpu_probe_base_features(struct cpu_info *ci)
ci->ci_cinfo[cai->cai_index] = *cai;
}
}
CPUID(2, descs[0], descs[1], descs[2], descs[3]);
x86_cpuid(2, descs);
}
if (ci->ci_cpuid_level < 3)
@ -756,9 +760,9 @@ cpu_probe_base_features(struct cpu_info *ci)
if ((ci->ci_feature_flags & CPUID_PN) != 0)
{
ci->ci_cpu_serial[0] = ci->ci_signature;
CPUID(3, dummy1, dummy2,
ci->ci_cpu_serial[2],
ci->ci_cpu_serial[1]);
x86_cpuid(3, descs);
ci->ci_cpu_serial[2] = descs[2];
ci->ci_cpu_serial[1] = descs[3];
}
}
@ -807,22 +811,23 @@ amd_family6_probe(struct cpu_info *ci)
char *p;
int i;
CPUID(0x80000000, lfunc, descs[1], descs[2], descs[3]);
x86_cpuid(0x80000000, descs);
lfunc = descs[0];
/*
* Determine the extended feature flags.
*/
if (lfunc >= 0x80000001) {
CPUID(0x80000001, descs[0], descs[1], descs[2], descs[3]);
x86_cpuid(0x80000001, descs);
ci->ci_feature_flags |= descs[3];
}
if (lfunc < 0x80000004)
return;
CPUID(0x80000002, brand[0], brand[1], brand[2], brand[3]);
CPUID(0x80000003, brand[4], brand[5], brand[6], brand[7]);
CPUID(0x80000004, brand[8], brand[9], brand[10], brand[11]);
x86_cpuid(0x80000002, brand);
x86_cpuid(0x80000003, brand + 4);
x86_cpuid(0x80000004, brand + 8);
for (i = 1; i < sizeof(amd_brand) / sizeof(amd_brand[0]); i++)
if ((p = strstr((char *)brand, amd_brand[i])) != NULL) {
@ -890,12 +895,12 @@ u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = {
u_int
tmx86_get_longrun_mode(void)
{
u_long eflags;
u_long psl;
union msrinfo msrinfo;
u_int low, high, flags, mode;
eflags = read_eflags();
disable_intr();
psl = x86_read_psl();
x86_disable_intr();
msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
low = LONGRUN_MODE_MASK(msrinfo.regs[0]);
@ -911,40 +916,40 @@ tmx86_get_longrun_mode(void)
}
mode = LONGRUN_MODE_UNKNOWN;
out:
write_eflags(eflags);
x86_write_psl(psl);
return (mode);
}
static u_int
tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage)
{
u_long eflags;
u_int eax, ebx, ecx, edx;
u_long psl;
u_int descs[4];
eflags = read_eflags();
disable_intr();
psl = x86_read_psl();
x86_disable_intr();
CPUID(0x80860007, eax, ebx, ecx, edx);
*frequency = eax;
*voltage = ebx;
*percentage = ecx;
x86_cpuid(0x80860007, descs);
*frequency = descs[0];
*voltage = descs[1];
*percentage = descs[2];
write_eflags(eflags);
x86_write_psl(psl);
return (1);
}
u_int
tmx86_set_longrun_mode(u_int mode)
{
u_long eflags;
u_long psl;
union msrinfo msrinfo;
if (mode >= LONGRUN_MODE_UNKNOWN) {
return (0);
}
eflags = read_eflags();
disable_intr();
psl = x86_read_psl();
x86_disable_intr();
/* Write LongRun mode values to Model Specific Register. */
msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
@ -959,7 +964,7 @@ tmx86_set_longrun_mode(u_int mode)
msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | longrun_modes[mode][2];
wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr);
write_eflags(eflags);
x86_write_psl(psl);
return (1);
}
@ -980,45 +985,37 @@ tmx86_get_longrun_status_all(void)
static void
transmeta_cpu_info(struct cpu_info *ci)
{
u_int eax, ebx, ecx, edx, nreg = 0;
u_int descs[4], nreg;
CPUID(0x80860000, eax, ebx, ecx, edx);
nreg = eax;
x86_cpuid(0x80860000, descs);
nreg = descs[0];
if (nreg >= 0x80860001) {
CPUID(0x80860001, eax, ebx, ecx, edx);
x86_cpuid(0x80860001, descs);
printf("%s: Processor revision %u.%u.%u.%u\n",
ci->ci_dev->dv_xname,
(ebx >> 24) & 0xff,
(ebx >> 16) & 0xff,
(ebx >> 8) & 0xff,
ebx & 0xff);
(descs[1] >> 24) & 0xff,
(descs[1] >> 16) & 0xff,
(descs[1] >> 8) & 0xff,
descs[1] & 0xff);
}
if (nreg >= 0x80860002) {
CPUID(0x80860002, eax, ebx, ecx, edx);
x86_cpuid(0x80860002, descs);
printf("%s: Code Morphing Software Rev: %u.%u.%u-%u-%u\n",
ci->ci_dev->dv_xname, (ebx >> 24) & 0xff,
(ebx >> 16) & 0xff,
(ebx >> 8) & 0xff,
ebx & 0xff,
ecx);
ci->ci_dev->dv_xname, (descs[1] >> 24) & 0xff,
(descs[1] >> 16) & 0xff,
(descs[1] >> 8) & 0xff,
descs[1] & 0xff,
descs[2]);
}
if (nreg >= 0x80860006) {
union {
char text[65];
struct
{
u_int eax;
u_int ebx;
u_int ecx;
u_int edx;
} regs[4];
u_int regs[4][4];
} info;
int i;
for (i=0; i<4; i++) {
CPUID(0x80860003 + i,
info.regs[i].eax, info.regs[i].ebx,
info.regs[i].ecx, info.regs[i].edx);
x86_cpuid(0x80860003 + i, info.regs[i]);
}
info.text[64] = 0;
printf("%s: %s\n", ci->ci_dev->dv_xname, info.text);
@ -1038,10 +1035,10 @@ transmeta_cpu_info(struct cpu_info *ci)
void
transmeta_cpu_setup(struct cpu_info *ci)
{
u_int nreg = 0, dummy;
u_int descs[4];
CPUID(0x80860000, nreg, dummy, dummy, dummy);
if (nreg >= 0x80860007)
x86_cpuid(0x80860000, descs);
if (descs[0] >= 0x80860007)
tmx86_has_longrun = 1;
}

9
sys/arch/xen/i386/idle_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: idle_machdep.c,v 1.3 2007/06/25 19:57:32 bouyer Exp $ */
/* $NetBSD: idle_machdep.c,v 1.4 2007/09/26 19:48:39 ad Exp $ */
/*-
* Copyright (c)2002, 2006, 2007 YAMAMOTO Takashi,
@ -28,7 +28,7 @@
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: idle_machdep.c,v 1.3 2007/06/25 19:57:32 bouyer Exp $");
__KERNEL_RCSID(0, "$NetBSD: idle_machdep.c,v 1.4 2007/09/26 19:48:39 ad Exp $");
#include <sys/param.h>
#include <sys/cpu.h>
@ -40,12 +40,11 @@ cpu_idle(void)
{
struct cpu_info *ci = curcpu();
disable_intr();
__insn_barrier();
x86_disable_intr();
if (!__predict_false(ci->ci_want_resched)) {
idle_block();
} else {
enable_intr();
x86_enable_intr();
}
ci->ci_want_resched = 0;
}

8
sys/arch/xen/i386/machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.42 2007/09/24 18:34:01 bouyer Exp $ */
/* $NetBSD: machdep.c,v 1.43 2007/09/26 19:48:39 ad Exp $ */
/* NetBSD: machdep.c,v 1.559 2004/07/22 15:12:46 mycroft Exp */
/*-
@ -73,7 +73,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.42 2007/09/24 18:34:01 bouyer Exp $");
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.43 2007/09/26 19:48:39 ad Exp $");
#include "opt_beep.h"
#include "opt_compat_ibcs2.h"
@ -2040,7 +2040,7 @@ init386(paddr_t first_avail)
XENPRINTF(("splraise(IPL_IPI)\n"));
splraise(IPL_IPI);
XENPRINTF(("enable_intr\n"));
enable_intr();
x86_enable_intr();
XENPRINTF(("physmem %lu\n", ptoa(physmem)));
if (physmem < btoc(2 * 1024 * 1024)) {
@ -2155,7 +2155,7 @@ void
cpu_reset()
{
disable_intr();
x86_disable_intr();
#if 0
/*

6
sys/arch/xen/i386/pmap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: pmap.c,v 1.30 2007/09/04 13:50:26 yamt Exp $ */
/* $NetBSD: pmap.c,v 1.31 2007/09/26 19:48:39 ad Exp $ */
/* NetBSD: pmap.c,v 1.179 2004/10/10 09:55:24 yamt Exp */
/*
@ -61,7 +61,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.30 2007/09/04 13:50:26 yamt Exp $");
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.31 2007/09/26 19:48:39 ad Exp $");
#include "opt_cputype.h"
#include "opt_user_ldt.h"
@ -2186,7 +2186,7 @@ pmap_load()
/* should be able to take ipis. */
KASSERT(ci->ci_ilevel < IPL_IPI);
KASSERT(read_psl() == 0);
KASSERT(x86_read_psl() == 0);
l = ci->ci_curlwp;
KASSERT(l != NULL);

25
sys/arch/xen/i386/trap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: trap.c,v 1.16 2007/05/17 14:51:36 yamt Exp $ */
/* $NetBSD: trap.c,v 1.17 2007/09/26 19:48:39 ad Exp $ */
/* NetBSD: trap.c,v 1.200 2004/03/14 01:08:48 cl Exp */
/*-
@ -76,7 +76,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.16 2007/05/17 14:51:36 yamt Exp $");
__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.17 2007/09/26 19:48:39 ad Exp $");
#include "opt_ddb.h"
#include "opt_kgdb.h"
@ -241,10 +241,10 @@ trap(frame)
}
#ifdef DEBUG
if (trapdebug) {
printf("trap %d code %x eip %x cs %x/%x eflags %x cr2 %x cpl %x\n",
printf("trap %d code %x eip %x cs %x/%x eflags %x cr2 %lx cpl %x\n",
frame->tf_trapno, frame->tf_err, frame->tf_eip,
frame->tf_cs, IDXSEL(frame->tf_cs),
frame->tf_eflags, rcr2(), curcpu()->ci_ilevel);
frame->tf_eflags, (long)rcr2(), curcpu()->ci_ilevel);
printf("curlwp %p%s", curlwp, curlwp ? " " : "\n");
if (curlwp)
printf("pid %d lid %d\n", l->l_proc->p_pid, l->l_lid);
@ -262,6 +262,14 @@ trap(frame)
default:
we_re_toast:
if (frame->tf_trapno < trap_types)
printf("fatal %s", trap_type[frame->tf_trapno]);
else
printf("unknown trap %d", frame->tf_trapno);
printf(" in %s mode\n", (type & T_USER) ? "user" : "supervisor");
printf("trap type %d code %x eip %x cs %x eflags %x cr2 %lx ilevel %x\n",
type, frame->tf_err, frame->tf_eip, frame->tf_cs,
frame->tf_eflags, (long)rcr2(), curcpu()->ci_ilevel);
#ifdef KSTACK_CHECK_DR0
if (type == T_TRCTRAP) {
u_int mask, dr6 = rdr6();
@ -295,15 +303,6 @@ trap(frame)
}
}
#endif
if (frame->tf_trapno < trap_types)
printf("fatal %s", trap_type[frame->tf_trapno]);
else
printf("unknown trap %d", frame->tf_trapno);
printf(" in %s mode\n", (type & T_USER) ? "user" : "supervisor");
printf("trap type %d code %x eip %x cs %x eflags %x cr2 %x ilevel %x\n",
type, frame->tf_err, frame->tf_eip, frame->tf_cs,
frame->tf_eflags, rcr2(), curcpu()->ci_ilevel);
panic("trap");
/*NOTREACHED*/

41
sys/arch/xen/i386/xen_intr.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: xen_intr.c,v 1.4 2007/06/26 19:41:11 bouyer Exp $ */
/* $NetBSD: xen_intr.c,v 1.5 2007/09/26 19:48:39 ad Exp $ */
/*-
* Copyright (c) 1998, 2001 The NetBSD Foundation, Inc.
@ -37,7 +37,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: xen_intr.c,v 1.4 2007/06/26 19:41:11 bouyer Exp $");
__KERNEL_RCSID(0, "$NetBSD: xen_intr.c,v 1.5 2007/09/26 19:48:39 ad Exp $");
#include <sys/param.h>
@ -74,14 +74,14 @@ spllower(int nlevel)
__insn_barrier();
imask = IUNMASK(ci, nlevel);
psl = read_psl();
disable_intr();
psl = x86_read_psl();
x86_disable_intr();
if (ci->ci_ipending & imask) {
Xspllower(nlevel);
/* Xspllower does enable_intr() */
} else {
ci->ci_ilevel = nlevel;
write_psl(psl);
x86_write_psl(psl);
}
}
@ -99,3 +99,34 @@ softintr(int sir)
__asm volatile("orl %1, %0" : "=m"(ci->ci_ipending) : "ir" (1 << sir));
}
void
x86_disable_intr(void)
{
__cli();
}
void
x86_enable_intr(void)
{
__sti();
}
u_long
x86_read_psl(void)
{
return (HYPERVISOR_shared_info->vcpu_info[0].evtchn_upcall_mask);
}
void
x86_write_psl(u_long psl)
{
HYPERVISOR_shared_info->vcpu_info[0].evtchn_upcall_mask = psl;
x86_lfence();
if (HYPERVISOR_shared_info->vcpu_info[0].evtchn_upcall_pending &&
psl == 0) {
hypervisor_force_callback();
}
}

11
sys/arch/xen/i386/xen_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: xen_machdep.c,v 1.19 2007/07/08 21:14:14 bouyer Exp $ */
/* $NetBSD: xen_machdep.c,v 1.20 2007/09/26 19:48:39 ad Exp $ */
/*
* Copyright (c) 2006 Manuel Bouyer.
@ -63,7 +63,7 @@
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: xen_machdep.c,v 1.19 2007/07/08 21:14:14 bouyer Exp $");
__KERNEL_RCSID(0, "$NetBSD: xen_machdep.c,v 1.20 2007/09/26 19:48:39 ad Exp $");
#include "opt_xen.h"
@ -153,13 +153,6 @@ xen_set_ldt(vaddr_t base, uint32_t entries)
splx(s);
}
void
lgdt(struct region_descriptor *rdp)
{
panic("lgdt %p %08x\n", (void *)rdp->rd_base, rdp->rd_limit);
}
void
xen_parse_cmdline(int what, union xen_cmdline_parseinfo *xcp)
{

155
sys/arch/xen/i386/xenfunc.c Normal file
View File

@ -0,0 +1,155 @@
/* $NetBSD: xenfunc.c,v 1.1 2007/09/26 19:48:38 ad Exp $ */
/*
*
* Copyright (c) 2004 Christian Limpach.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Christian Limpach.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/param.h>
#include <uvm/uvm_extern.h>
#include <machine/intr.h>
#include <machine/vmparam.h>
#include <machine/pmap.h>
#include <machine/xen.h>
#include <machine/hypervisor.h>
#include <machine/evtchn.h>
#include <machine/xenpmap.h>
#include <machine/pte.h>
#ifdef XENDEBUG_LOW
#define __PRINTK(x) printk x
#else
#define __PRINTK(x)
#endif
void xen_set_ldt(vaddr_t, uint32_t);
void xen_update_descriptor(union descriptor *, union descriptor *);
void
invlpg(vaddr_t addr)
{
int s = splvm();
xpq_queue_invlpg(addr);
xpq_flush_queue();
splx(s);
}
void
lldt(u_short sel)
{
/* __PRINTK(("ldt %x\n", IDXSELN(sel))); */
if (sel == GSEL(GLDT_SEL, SEL_KPL))
xen_set_ldt((vaddr_t)ldt, NLDT);
else
xen_set_ldt(cpu_info_primary.ci_gdt[IDXSELN(sel)].ld.ld_base,
cpu_info_primary.ci_gdt[IDXSELN(sel)].ld.ld_entries);
}
void
ltr(u_short sel)
{
__PRINTK(("XXX ltr not supported\n"));
}
void
lcr0(u_int val)
{
__PRINTK(("XXX lcr0 not supported\n"));
}
u_int
rcr0(void)
{
__PRINTK(("XXX rcr0 not supported\n"));
return 0;
}
void
lcr3(vaddr_t val)
{
int s = splvm();
xpq_queue_pt_switch(xpmap_ptom(val) & PG_FRAME);
xpq_flush_queue();
splx(s);
}
void
tlbflush(void)
{
int s = splvm();
xpq_queue_tlb_flush();
xpq_flush_queue();
splx(s);
}
void
tlbflushg(void)
{
tlbflush();
}
vaddr_t
rdr6(void)
{
u_int val;
val = HYPERVISOR_get_debugreg(6);
return val;
}
void
ldr6(vaddr_t val)
{
HYPERVISOR_set_debugreg(6, val);
}
void
wbinvd(void)
{
xpq_flush_cache();
}
vaddr_t
rcr2(void)
{
return 0; /* XXX Why? */
}
void
lgdt(struct region_descriptor *rdp)
{
panic("lgdt %p %08x\n", (void *)rdp->rd_base, rdp->rd_limit);
}

340
sys/arch/xen/include/cpufunc.h
View File

@ -1,340 +1,4 @@
/* $NetBSD: cpufunc.h,v 1.16 2007/09/23 16:54:07 bouyer Exp $ */
/* NetBSD: cpufunc.h,v 1.28 2004/01/14 11:31:55 yamt Exp */
/* $NetBSD: cpufunc.h,v 1.17 2007/09/26 19:48:44 ad Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Charles M. Hannum.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <x86/cpufunc.h>
#ifndef _I386_CPUFUNC_H_
#define _I386_CPUFUNC_H_
/*
* Functions to provide access to i386-specific instructions.
*/
#include <sys/cdefs.h>
#include <sys/types.h>
#include <machine/segments.h>
#include <machine/specialreg.h>
#include <machine/xen.h>
#include <machine/hypervisor.h>
#ifdef _KERNEL
void x86_pause(void);
#else
static __inline void
x86_pause(void)
{
__asm volatile("pause");
}
#endif
static __inline void
x86_lfence(void)
{
/*
* XXX it's better to use real lfence insn if available.
*/
__asm volatile("lock; addl $0, 0(%%esp)" : : : "memory");
}
static __inline void
x86_sfence(void)
{
/*
* nothing to do at the CPU level, just put a barrier for compiler
*/
__insn_barrier();
}
static __inline void
x86_mfence(void)
{
/*
* XXX it's better to use real mfence insn if available.
*/
__asm volatile("lock; addl $0, 0(%%esp)" : : : "memory");
}
#ifdef _KERNEL
extern unsigned int cpu_feature;
#if 0
static __inline void
invlpg(u_int addr)
{
__asm volatile("invlpg (%0)" : : "r" (addr) : "memory");
}
#endif
static __inline void
lidt(struct region_descriptor *region)
{
__asm volatile("lidt %0" : : "m" (*region));
}
#if 0
static __inline void
lldt(u_short sel)
{
__asm volatile("lldt %0" : : "r" (sel));
}
#endif
#if 0
static __inline void
ltr(u_short sel)
{
__asm volatile("ltr %0" : : "r" (sel));
}
static __inline void
lcr0(u_int val)
{
__asm volatile("movl %0,%%cr0" : : "r" (val));
}
static __inline u_int
rcr0(void)
{
u_int val;
__asm volatile("movl %%cr0,%0" : "=r" (val));
return val;
}
#endif
static __inline u_int
rcr2(void)
{
return 0;
}
#if 0
static __inline void
lcr3(u_int val)
{
__asm volatile("movl %0,%%cr3" : : "r" (val));
}
#endif
static __inline u_int
rcr3(void)
{
u_int val;
__asm volatile("movl %%cr3,%0" : "=r" (val));
return val;
}
static __inline void
lcr4(u_int val)
{
__asm volatile("movl %0,%%cr4" : : "r" (val));
}
static __inline u_int
rcr4(void)
{
u_int val;
__asm volatile("movl %%cr4,%0" : "=r" (val));
return val;
}
#if 0
static __inline void
tlbflush(void)
{
u_int val;
val = rcr3();
lcr3(val);
}
static __inline void
tlbflushg(void)
{
/*
* Big hammer: flush all TLB entries, including ones from PTE's
* with the G bit set. This should only be necessary if TLB
* shootdown falls far behind.
*
* Intel Architecture Software Developer's Manual, Volume 3,
* System Programming, section 9.10, "Invalidating the
* Translation Lookaside Buffers (TLBS)":
* "The following operations invalidate all TLB entries, irrespective
* of the setting of the G flag:
* ...
* "(P6 family processors only): Writing to control register CR4 to
* modify the PSE, PGE, or PAE flag."
*
* (the alternatives not quoted above are not an option here.)
*
* If PGE is not in use, we reload CR3 for the benefit of
* pre-P6-family processors.
*/
#if defined(I686_CPU)
if (cpu_feature & CPUID_PGE) {
u_int cr4 = rcr4();
lcr4(cr4 & ~CR4_PGE);
lcr4(cr4);
} else
#endif
tlbflush();
}
#endif
#ifdef notyet
void setidt(int idx, /*XXX*/void *func, int typ, int dpl);
#endif
/* debug register */
void dr0(void *, u_int32_t, u_int32_t, u_int32_t);
#if 0
static __inline u_int
rdr6(void)
{
u_int val;
__asm volatile("movl %%dr6,%0" : "=r" (val));
return val;
}
static __inline void
ldr6(u_int val)
{
__asm volatile("movl %0,%%dr6" : : "r" (val));
}
#endif
/* XXXX ought to be in psl.h with spl() functions */
static __inline void
disable_intr(void)
{
__cli();
}
static __inline void
enable_intr(void)
{
__sti();
}
static __inline u_long
read_eflags(void)
{
u_long ef;
__asm volatile("pushfl; popl %0" : "=r" (ef));
return (ef);
}
static __inline void
write_eflags(u_long ef)
{
__asm volatile("pushl %0; popfl" : : "r" (ef));
}
static __inline u_int64_t
rdmsr(u_int msr)
{
u_int64_t rv;
__asm volatile("rdmsr" : "=A" (rv) : "c" (msr));
return (rv);
}
static __inline void
wrmsr(u_int msr, u_int64_t newval)
{
__asm volatile("wrmsr" : : "A" (newval), "c" (msr));
}
static __inline u_int64_t
rdtsc(void)
{
u_int64_t rv;
__asm volatile("rdtsc" : "=A" (rv));
return (rv);
}
static __inline u_int64_t
rdpmc(u_int pmc)
{
u_int64_t rv;
__asm volatile("rdpmc" : "=A" (rv) : "c" (pmc));
return (rv);
}
/* Break into DDB/KGDB. */
static __inline void
breakpoint(void)
{
__asm volatile("int $3");
}
#define read_psl() (HYPERVISOR_shared_info->vcpu_info[0].evtchn_upcall_mask)
#define write_psl(x) do { \
__insn_barrier(); \
HYPERVISOR_shared_info->vcpu_info[0].evtchn_upcall_mask = (x) ; \
x86_lfence(); \
if ((x) == 0 && HYPERVISOR_shared_info->vcpu_info[0].evtchn_upcall_pending) \
hypervisor_force_callback(); \
} while (0)
/*
* XXX Maybe these don't belong here...
*/
extern int (*copyout_func)(const void *, void *, size_t);
extern int (*copyin_func)(const void *, void *, size_t);
int i386_copyout(const void *, void *, size_t);
int i486_copyout(const void *, void *, size_t);
int i386_copyin(const void *, void *, size_t);
#endif /* _KERNEL */
#endif /* !_I386_CPUFUNC_H_ */

5
sys/arch/xen/include/intr.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: intr.h,v 1.16 2007/05/17 14:51:36 yamt Exp $ */
/* $NetBSD: intr.h,v 1.17 2007/09/26 19:48:44 ad Exp $ */
/* NetBSD intr.h,v 1.15 2004/10/31 10:39:34 yamt Exp */
/*-
@ -41,6 +41,9 @@
#define _XEN_INTR_H_
#include <machine/intrdefs.h>
#include <machine/xen.h>
#include <machine/hypervisor.h>
#include <machine/evtchn.h>
#ifndef _LOCORE
#include <machine/cpu.h>

8
sys/arch/xen/include/xen.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: xen.h,v 1.22 2007/09/23 16:54:08 bouyer Exp $ */
/* $NetBSD: xen.h,v 1.23 2007/09/26 19:48:44 ad Exp $ */
/*
*
@ -296,11 +296,7 @@ xen_atomic_clear_bit(volatile void *ptr, int bitno)
#undef XATOMIC_T
static __inline void
wbinvd(void)
{
xpq_flush_cache();
}
void wbinvd(void);
#endif /* !__ASSEMBLY__ */

80
sys/arch/xen/include/xenfunc.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: xenfunc.h,v 1.10 2006/02/16 20:17:15 perry Exp $ */
/* $NetBSD: xenfunc.h,v 1.11 2007/09/26 19:48:44 ad Exp $ */
/*
*
@ -50,82 +50,4 @@
void xen_set_ldt(vaddr_t, uint32_t);
void xen_update_descriptor(union descriptor *, union descriptor *);
static __inline void
invlpg(u_int addr)
{
int s = splvm();
xpq_queue_invlpg(addr);
xpq_flush_queue();
splx(s);
}
static __inline void
lldt(u_short sel)
{
/* __PRINTK(("ldt %x\n", IDXSELN(sel))); */
if (sel == GSEL(GLDT_SEL, SEL_KPL))
xen_set_ldt((vaddr_t)ldt, NLDT);
else
xen_set_ldt(cpu_info_primary.ci_gdt[IDXSELN(sel)].ld.ld_base,
cpu_info_primary.ci_gdt[IDXSELN(sel)].ld.ld_entries);
}
static __inline void
ltr(u_short sel)
{
__PRINTK(("XXX ltr not supported\n"));
}
static __inline void
lcr0(u_int val)
{
__PRINTK(("XXX lcr0 not supported\n"));
}
static __inline u_int
rcr0(void)
{
__PRINTK(("XXX rcr0 not supported\n"));
return 0;
}
#define lcr3(_v) _lcr3((_v), __FILE__, __LINE__)
static __inline void
_lcr3(u_int val, const char *file, int line)
{
int s = splvm();
/* __PRINTK(("lcr3 %08x at %s:%d\n", val, file, line)); */
xpq_queue_pt_switch(xpmap_ptom(val) & PG_FRAME);
xpq_flush_queue();
splx(s);
}
static __inline void
tlbflush(void)
{
int s = splvm();
xpq_queue_tlb_flush();
xpq_flush_queue();
splx(s);
}
#define tlbflushg() tlbflush() /* we don't use PGE */
static __inline u_int
rdr6(void)
{
u_int val;
val = HYPERVISOR_get_debugreg(6);
return val;
}
static __inline void
ldr6(u_int val)
{
HYPERVISOR_set_debugreg(6, val);
}
#endif /* _XEN_XENFUNC_H_ */

511
sys/arch/xen/x86/bus_space.c
View File

@ -1,511 +0,0 @@
/* $NetBSD: bus_space.c,v 1.8 2007/03/04 06:01:10 christos Exp $ */
/* NetBSD: bus_space.c,v 1.2 2003/03/14 18:47:53 christos Exp */
/*-
* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
* Simulation Facility, NASA Ames Research Center.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: bus_space.c,v 1.8 2007/03/04 06:01:10 christos Exp $");
#include "opt_xen.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/malloc.h>
#include <sys/extent.h>
#include <uvm/uvm_extern.h>
#include <machine/bus.h>
#include <dev/isa/isareg.h>
#include <machine/isa_machdep.h>
#include <machine/hypervisor.h>
#include <machine/xenpmap.h>
/*
* Extent maps to manage I/O and memory space. Allocate
* storage for 8 regions in each, initially. Later, ioport_malloc_safe
* will indicate that it's safe to use malloc() to dynamically allocate
* region descriptors.
*
* N.B. At least two regions are _always_ allocated from the iomem
* extent map; (0 -> ISA hole) and (end of ISA hole -> end of RAM).
*
* The extent maps are not static! Machine-dependent ISA and EISA
* routines need access to them for bus address space allocation.
*/
static long ioport_ex_storage[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)];
static long iomem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)];
struct extent *ioport_ex;
struct extent *iomem_ex;
static int ioport_malloc_safe;
int x86_mem_add_mapping __P((bus_addr_t, bus_size_t,
int, bus_space_handle_t *));
void
x86_bus_space_init()
{
/*
* Initialize the I/O port and I/O mem extent maps.
* Note: we don't have to check the return value since
* creation of a fixed extent map will never fail (since
* descriptor storage has already been allocated).
*
* N.B. The iomem extent manages _all_ physical addresses
* on the machine. When the amount of RAM is found, the two
* extents of RAM are allocated from the map (0 -> ISA hole
* and end of ISA hole -> end of RAM).
*/
ioport_ex = extent_create("ioport", 0x0, 0xffff, M_DEVBUF,
(void *)ioport_ex_storage, sizeof(ioport_ex_storage),
EX_NOCOALESCE|EX_NOWAIT);
iomem_ex = extent_create("iomem", 0x0, 0xffffffff, M_DEVBUF,
(void *)iomem_ex_storage, sizeof(iomem_ex_storage),
EX_NOCOALESCE|EX_NOWAIT);
/* We are privileged guest os - should have IO privileges. */
if (xen_start_info.flags & SIF_PRIVILEGED) {
#ifdef XEN3
struct physdev_op physop;
physop.cmd = PHYSDEVOP_SET_IOPL;
physop.u.set_iopl.iopl = 1;
if (HYPERVISOR_physdev_op(&physop) != 0)
panic("Unable to obtain IOPL, "
"despite being SIF_PRIVILEGED");
#else
dom0_op_t op;
op.cmd = DOM0_IOPL;
op.u.iopl.domain = DOMID_SELF;
op.u.iopl.iopl = 1;
if (HYPERVISOR_dom0_op(&op) != 0)
panic("Unable to obtain IOPL, "
"despite being SIF_PRIVILEGED");
#endif
}
}
void
x86_bus_space_mallocok()
{
ioport_malloc_safe = 1;
}
int
x86_memio_map(t, bpa, size, flags, bshp)
bus_space_tag_t t;
bus_addr_t bpa;
bus_size_t size;
int flags;
bus_space_handle_t *bshp;
{
int error;
struct extent *ex;
/*
* Pick the appropriate extent map.
*/
if (t == X86_BUS_SPACE_IO) {
if (flags & BUS_SPACE_MAP_LINEAR)
return (EOPNOTSUPP);
ex = ioport_ex;
} else if (t == X86_BUS_SPACE_MEM)
ex = iomem_ex;
else
panic("x86_memio_map: bad bus space tag");
/*
* Before we go any further, let's make sure that this
* region is available.
*/
error = extent_alloc_region(ex, bpa, size,
EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0));
if (error)
return (error);
/*
* For I/O space, that's all she wrote.
*/
if (t == X86_BUS_SPACE_IO) {
*bshp = bpa;
return (0);
}
/*
* For memory space, map the bus physical address to
* a kernel virtual address.
*/
error = x86_mem_add_mapping(bpa, size,
(flags & BUS_SPACE_MAP_CACHEABLE) != 0, bshp);
if (error) {
if (extent_free(ex, bpa, size, EX_NOWAIT |
(ioport_malloc_safe ? EX_MALLOCOK : 0))) {
printf("x86_memio_map: pa 0x%lx, size 0x%lx\n",
bpa, size);
printf("x86_memio_map: can't free region\n");
}
}
return (error);
}
int
_x86_memio_map(t, bpa, size, flags, bshp)
bus_space_tag_t t;
bus_addr_t bpa;
bus_size_t size;
int flags;
bus_space_handle_t *bshp;
{
/*
* For I/O space, just fill in the handle.
*/
if (t == X86_BUS_SPACE_IO) {
if (flags & BUS_SPACE_MAP_LINEAR)
return (EOPNOTSUPP);
*bshp = bpa;
return (0);
}
/*
* For memory space, map the bus physical address to
* a kernel virtual address.
*/
return (x86_mem_add_mapping(bpa, size,
(flags & BUS_SPACE_MAP_CACHEABLE) != 0, bshp));
}
int
x86_memio_alloc(t, rstart, rend, size, alignment, boundary, flags,
bpap, bshp)
bus_space_tag_t t;
bus_addr_t rstart, rend;
bus_size_t size, alignment, boundary;
int flags;
bus_addr_t *bpap;
bus_space_handle_t *bshp;
{
struct extent *ex;
u_long bpa;
int error;
/*
* Pick the appropriate extent map.
*/
if (t == X86_BUS_SPACE_IO) {
if (flags & BUS_SPACE_MAP_LINEAR)
return (EOPNOTSUPP);
ex = ioport_ex;
} else if (t == X86_BUS_SPACE_MEM)
ex = iomem_ex;
else
panic("x86_memio_alloc: bad bus space tag");
/*
* Sanity check the allocation against the extent's boundaries.
*/
if (rstart < ex->ex_start || rend > ex->ex_end)
panic("x86_memio_alloc: bad region start/end");
/*
* Do the requested allocation.
*/
error = extent_alloc_subregion(ex, rstart, rend, size, alignment,
boundary,
EX_FAST | EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0),
&bpa);
if (error)
return (error);
/*
* For I/O space, that's all she wrote.
*/
if (t == X86_BUS_SPACE_IO) {
*bshp = *bpap = bpa;
return (0);
}
/*
* For memory space, map the bus physical address to
* a kernel virtual address.
*/
error = x86_mem_add_mapping(bpa, size,
(flags & BUS_SPACE_MAP_CACHEABLE) != 0, bshp);
if (error) {
if (extent_free(iomem_ex, bpa, size, EX_NOWAIT |
(ioport_malloc_safe ? EX_MALLOCOK : 0))) {
printf("x86_memio_alloc: pa 0x%lx, size 0x%lx\n",
bpa, size);
printf("x86_memio_alloc: can't free region\n");
}
}
*bpap = bpa;
return (error);
}
int
x86_mem_add_mapping(bpa, size, cacheable, bshp)
bus_addr_t bpa;
bus_size_t size;
int cacheable;
bus_space_handle_t *bshp;
{
u_long pa, endpa;
vaddr_t va;
pt_entry_t *pte;
pt_entry_t *maptp;
int32_t cpumask = 0;
pa = x86_trunc_page(bpa);
endpa = x86_round_page(bpa + size);
#ifdef DIAGNOSTIC
if (endpa <= pa)
panic("x86_mem_add_mapping: overflow");
#endif
if (bpa >= IOM_BEGIN && (bpa + size) <= IOM_END) {
va = (vaddr_t)ISA_HOLE_VADDR(pa);
} else {
va = uvm_km_alloc(kernel_map, endpa - pa, 0,
UVM_KMF_VAONLY | UVM_KMF_NOWAIT);
if (va == 0)
return (ENOMEM);
}
*bshp = (bus_space_handle_t)(va + (bpa & PGOFSET));
for (; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) {
pmap_kenter_ma(va, pa, VM_PROT_READ | VM_PROT_WRITE);
/*
* PG_N doesn't exist on 386's, so we assume that
* the mainboard has wired up device space non-cacheable
* on those machines.
*
* Note that it's not necessary to use atomic ops to
* fiddle with the PTE here, because we don't care
* about mod/ref information.
*
* XXX should hand this bit to pmap_kenter_pa to
* save the extra invalidate!
*
* XXX extreme paranoia suggests tlb shootdown belongs here.
*/
if (pmap_cpu_has_pg_n()) {
pte = kvtopte(va);
maptp = (pt_entry_t *)vtomach((vaddr_t)pte);
if (cacheable)
PTE_CLEARBITS(pte, maptp, PG_N);
else
PTE_SETBITS(pte, maptp, PG_N);
pmap_tlb_shootdown(pmap_kernel(), va, *pte,
&cpumask);
}
}
pmap_tlb_shootnow(cpumask);
pmap_update(pmap_kernel());
return 0;
}
/*
* void _x86_memio_unmap(bus_space_tag bst, bus_space_handle bsh,
* bus_size_t size, bus_addr_t *adrp)
*
* This function unmaps memory- or io-space mapped by the function
* _x86_memio_map(). This function works nearly as same as
* x86_memio_unmap(), but this function does not ask kernel
* built-in extents and returns physical address of the bus space,
* for the convenience of the extra extent manager.
*/
void
_x86_memio_unmap(t, bsh, size, adrp)
bus_space_tag_t t;
bus_space_handle_t bsh;
bus_size_t size;
bus_addr_t *adrp;
{
u_long va, endva;
bus_addr_t bpa;
/*
* Find the correct extent and bus physical address.
*/
if (t == X86_BUS_SPACE_IO) {
bpa = bsh;
} else if (t == X86_BUS_SPACE_MEM) {
if (bsh >= atdevbase && (bsh + size) <= (atdevbase + IOM_SIZE)) {
bpa = (bus_addr_t)ISA_PHYSADDR(bsh);
} else {
va = x86_trunc_page(bsh);
endva = x86_round_page(bsh + size);
#ifdef DIAGNOSTIC
if (endva <= va) {
panic("_x86_memio_unmap: overflow");
}
#endif
if (pmap_extract_ma(pmap_kernel(), va, &bpa) == false) {
panic("_x86_memio_unmap:"
" wrong virtual address");
}
bpa += (bsh & PGOFSET);
pmap_kremove(va, endva - va);
/*
* Free the kernel virtual mapping.
*/
uvm_km_free(kernel_map, va, endva - va, UVM_KMF_VAONLY);
}
} else {
panic("_x86_memio_unmap: bad bus space tag");
}
if (adrp != NULL) {
*adrp = bpa;
}
}
void
x86_memio_unmap(t, bsh, size)
bus_space_tag_t t;
bus_space_handle_t bsh;
bus_size_t size;
{
struct extent *ex;
u_long va, endva;
bus_addr_t bpa;
/*
* Find the correct extent and bus physical address.
*/
if (t == X86_BUS_SPACE_IO) {
ex = ioport_ex;
bpa = bsh;
} else if (t == X86_BUS_SPACE_MEM) {
ex = iomem_ex;
if (bsh >= atdevbase &&
(bsh + size) <= (atdevbase + IOM_SIZE)) {
bpa = (bus_addr_t)ISA_PHYSADDR(bsh);
goto ok;
}
va = x86_trunc_page(bsh);
endva = x86_round_page(bsh + size);
#ifdef DIAGNOSTIC
if (endva <= va)
panic("x86_memio_unmap: overflow");
#endif
(void) pmap_extract_ma(pmap_kernel(), va, &bpa);
bpa += (bsh & PGOFSET);
pmap_kremove(va, endva - va);
/*
* Free the kernel virtual mapping.
*/
uvm_km_free(kernel_map, va, endva - va, UVM_KMF_VAONLY);
} else
panic("x86_memio_unmap: bad bus space tag");
ok:
if (extent_free(ex, bpa, size,
EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0))) {
printf("x86_memio_unmap: %s 0x%lx, size 0x%lx\n",
(t == X86_BUS_SPACE_IO) ? "port" : "pa", bpa, size);
printf("x86_memio_unmap: can't free region\n");
}
}
void
x86_memio_free(t, bsh, size)
bus_space_tag_t t;
bus_space_handle_t bsh;
bus_size_t size;
{
/* x86_memio_unmap() does all that we need to do. */
x86_memio_unmap(t, bsh, size);
}
int
x86_memio_subregion(t, bsh, offset, size, nbshp)
bus_space_tag_t t;
bus_space_handle_t bsh;
bus_size_t offset, size;
bus_space_handle_t *nbshp;
{
*nbshp = bsh + offset;
return (0);
}
paddr_t
x86_memio_mmap(t, addr, off, prot, flags)
bus_space_tag_t t;
bus_addr_t addr;
off_t off;
int prot;
int flags;
{
/* Can't mmap I/O space. */
if (t == X86_BUS_SPACE_IO)
return (-1);
/*
* "addr" is the base address of the device we're mapping.
* "off" is the offset into that device.
*
* Note we are called for each "page" in the device that
* the upper layers want to map.
*/
return (x86_btop(addr + off));
}

6
sys/arch/xen/xen/evtchn.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: evtchn.c,v 1.21 2007/09/23 16:54:09 bouyer Exp $ */
/* $NetBSD: evtchn.c,v 1.22 2007/09/26 19:48:45 ad Exp $ */
/*
* Copyright (c) 2006 Manuel Bouyer.
@ -64,7 +64,7 @@
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: evtchn.c,v 1.21 2007/09/23 16:54:09 bouyer Exp $");
__KERNEL_RCSID(0, "$NetBSD: evtchn.c,v 1.22 2007/09/26 19:48:45 ad Exp $");
#include "opt_xen.h"
#include "isa.h"
@ -175,7 +175,7 @@ init_events()
ctrl_if_init();
#endif
enable_intr(); /* at long last... */
x86_enable_intr(); /* at long last... */
}
unsigned int

8
sys/dev/acpi/acpi_timer.c
View File

@ -1,7 +1,7 @@
/* $NetBSD: acpi_timer.c,v 1.8 2006/11/16 01:32:47 christos Exp $ */
/* $NetBSD: acpi_timer.c,v 1.9 2007/09/26 19:48:45 ad Exp $ */
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: acpi_timer.c,v 1.8 2006/11/16 01:32:47 christos Exp $");
__KERNEL_RCSID(0, "$NetBSD: acpi_timer.c,v 1.9 2007/09/26 19:48:45 ad Exp $");
#include <sys/types.h>
#include <dev/acpi/acpi_timer.h>
@ -111,7 +111,7 @@ acpitimer_test()
minl = 10000000;
maxl = 0;
disable_intr();
x86_disable_intr();
AcpiGetTimer(&last);
for (n = 0; n < N; n++) {
AcpiGetTimer(&this);
@ -122,7 +122,7 @@ acpitimer_test()
minl = delta;
last = this;
}
enable_intr();
x86_enable_intr();
if (maxl - minl > 2 )
n = 0;

331
sys/sys/bus_proto.h Normal file
View File

@ -0,0 +1,331 @@
/* $NetBSD: bus_proto.h,v 1.1 2007/09/26 19:48:39 ad Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998, 2001, 2007 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
* NASA Ames Research Center, and by Andrew Doran.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Copyright (c) 1996 Charles M. Hannum. All rights reserved.
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Christopher G. Demetriou
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _SYS_BUS_PROTO_H_
#define _SYS_BUS_PROTO_H_
/*
* Forwards needed by prototypes below.
*/
struct mbuf;
struct uio;
/*
* bus_space(9)
*/
/* Map types. */
#define BUS_SPACE_MAP_CACHEABLE 0x01
#define BUS_SPACE_MAP_LINEAR 0x02
#define BUS_SPACE_MAP_PREFETCHABLE 0x04
/* Bus read/write barrier methods. */
#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
int bus_space_map(bus_space_tag_t, bus_addr_t, bus_size_t, int,
bus_space_handle_t *);
void bus_space_unmap(bus_space_tag_t, bus_space_handle_t, bus_size_t);
int bus_space_subregion(bus_space_tag_t, bus_space_handle_t,
bus_size_t, bus_size_t, bus_space_handle_t *);
int bus_space_alloc(bus_space_tag_t, bus_addr_t, bus_addr_t,
bus_size_t, bus_size_t, bus_size_t,
int, bus_addr_t *, bus_space_handle_t *);
void bus_space_free(bus_space_tag_t, bus_space_handle_t, bus_size_t);
paddr_t bus_space_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int);
void *bus_space_vaddr(bus_space_tag_t, bus_space_handle_t);
void bus_space_barrier(bus_space_tag_t tag, bus_space_handle_t bsh,
bus_size_t offset, bus_size_t len, int flags);
/*
* bus_space(9) accessors
*/
uint8_t bus_space_read_1(bus_space_tag_t, bus_space_handle_t,
bus_size_t);
uint8_t bus_space_read_stream_1(bus_space_tag_t, bus_space_handle_t,
bus_size_t);
uint16_t bus_space_read_2(bus_space_tag_t, bus_space_handle_t,
bus_size_t);
uint16_t bus_space_read_stream_2(bus_space_tag_t, bus_space_handle_t,
bus_size_t);
uint32_t bus_space_read_4(bus_space_tag_t, bus_space_handle_t,
bus_size_t);
uint32_t bus_space_read_stream_4(bus_space_tag_t, bus_space_handle_t,
bus_size_t);
uint64_t bus_space_read_8(bus_space_tag_t, bus_space_handle_t,
bus_size_t);
uint64_t bus_space_read_stream_8(bus_space_tag_t, bus_space_handle_t,
bus_size_t);
void bus_space_read_multi_1(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint8_t *, bus_size_t);
void bus_space_read_multi_stream_1(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint8_t *, bus_size_t);
void bus_space_read_region_1(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint8_t *, bus_size_t);
void bus_space_read_region_stream_1(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint8_t *, bus_size_t);
void bus_space_read_multi_2(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint16_t *, bus_size_t);
void bus_space_read_multi_stream_2(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint16_t *, bus_size_t);
void bus_space_read_region_2(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint16_t *, bus_size_t);
void bus_space_read_region_stream_2(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint16_t *, bus_size_t);
void bus_space_read_multi_4(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint32_t *, bus_size_t);
void bus_space_read_multi_stream_4(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint32_t *, bus_size_t);
void bus_space_read_region_4(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint32_t *, bus_size_t);
void bus_space_read_region_stream_4(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint32_t *, bus_size_t);
void bus_space_read_multi_8(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint32_t *, bus_size_t);
void bus_space_read_multi_stream_8(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint32_t *, bus_size_t);
void bus_space_read_region_8(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint64_t *, bus_size_t);
void bus_space_read_region_stream_8(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint64_t *, bus_size_t);
void bus_space_write_1(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint8_t);
void bus_space_write_stream_1(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint8_t);
void bus_space_write_2(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint16_t);
void bus_space_write_stream_2(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint16_t);
void bus_space_write_4(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint32_t);
void bus_space_write_stream_4(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint32_t);
void bus_space_write_8(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint64_t);
void bus_space_write_stream_8(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint64_t);
void bus_space_write_multi_1(bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint8_t *,
bus_size_t);
void bus_space_write_multi_stream_1(bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint8_t *,
bus_size_t);
void bus_space_write_region_1(bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint8_t *,
bus_size_t);
void bus_space_write_region_stream_1(bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint8_t *,
bus_size_t);
void bus_space_write_multi_2(bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint16_t *,
bus_size_t);
void bus_space_write_multi_stream_2(bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint16_t *,
bus_size_t);
void bus_space_write_region_2(bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint16_t *,
bus_size_t);
void bus_space_write_region_stream_2(bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint16_t *,
bus_size_t);
void bus_space_write_multi_4(bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint32_t *,
bus_size_t);
void bus_space_write_multi_stream_4(bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint32_t *,
bus_size_t);
void bus_space_write_region_4(bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint32_t *,
bus_size_t);
void bus_space_write_region_stream_4(bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint32_t *,
bus_size_t);
void bus_space_write_multi_8(bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint32_t *,
bus_size_t);
void bus_space_write_multi_stream_8(bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint32_t *,
bus_size_t);
void bus_space_write_region_8(bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint64_t *,
bus_size_t);
void bus_space_write_region_stream_8(bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint64_t *,
bus_size_t);
void bus_space_set_multi_1(bus_space_tag_t, bus_space_handle_t,
bus_size_t, u_int8_t, size_t);
void bus_space_set_multi_2(bus_space_tag_t, bus_space_handle_t,
bus_size_t, u_int16_t, size_t);
void bus_space_set_multi_4(bus_space_tag_t, bus_space_handle_t,
bus_size_t, u_int32_t, size_t);
void bus_space_set_multi_8(bus_space_tag_t, bus_space_handle_t,
bus_size_t, u_int64_t, size_t);
void bus_space_set_region_1(bus_space_tag_t, bus_space_handle_t,
bus_size_t, u_int8_t, size_t);
void bus_space_set_region_2(bus_space_tag_t, bus_space_handle_t,
bus_size_t, u_int16_t, size_t);
void bus_space_set_region_4(bus_space_tag_t, bus_space_handle_t,
bus_size_t, u_int32_t, size_t);
void bus_space_set_region_8(bus_space_tag_t, bus_space_handle_t,
bus_size_t, u_int64_t, size_t);
void bus_space_copy_region_1(bus_space_tag_t, bus_space_handle_t,
bus_size_t, bus_space_handle_t,
bus_size_t, size_t);
void bus_space_copy_region_2(bus_space_tag_t, bus_space_handle_t,
bus_size_t, bus_space_handle_t,
bus_size_t, size_t);
void bus_space_copy_region_4(bus_space_tag_t, bus_space_handle_t,
bus_size_t, bus_space_handle_t,
bus_size_t, size_t);
void bus_space_copy_region_8(bus_space_tag_t, bus_space_handle_t,
bus_size_t, bus_space_handle_t,
bus_size_t, size_t);
/*
* bus_dma(9)
*/
/* Flags used in various bus DMA methods. */
#define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */
#define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */
#define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */
#define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */
#define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */
#define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */
#define BUS_DMA_BUS2 0x020
#define BUS_DMA_BUS3 0x040
#define BUS_DMA_BUS4 0x080
#define BUS_DMA_READ 0x100 /* mapping is device -> memory only */
#define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */
#define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */
/* Operations performed by bus_dmamap_sync(). */
#define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */
#define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */
#define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */
#define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */
int bus_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t,
bus_size_t, int, bus_dmamap_t *);
void bus_dmamap_destroy(bus_dma_tag_t, bus_dmamap_t);
int bus_dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *, bus_size_t,
struct proc *, int);
int bus_dmamap_load_mbuf(bus_dma_tag_t, bus_dmamap_t,
struct mbuf *, int);
int bus_dmamap_load_uio(bus_dma_tag_t, bus_dmamap_t,
struct uio *, int);
int bus_dmamap_load_raw(bus_dma_tag_t, bus_dmamap_t,
bus_dma_segment_t *, int, bus_size_t, int);
void bus_dmamap_unload(bus_dma_tag_t, bus_dmamap_t);
void bus_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
bus_size_t, int);
int bus_dmamem_alloc(bus_dma_tag_t, bus_size_t, bus_size_t,
bus_size_t, bus_dma_segment_t *,
int, int *, int);
void bus_dmamem_free(bus_dma_tag_t, bus_dma_segment_t *, int);
int bus_dmamem_map(bus_dma_tag_t, bus_dma_segment_t *, int,
size_t, void **, int);
void bus_dmamem_unmap(bus_dma_tag_t, void *kva, size_t);
paddr_t bus_dmamem_mmap(bus_dma_tag_t, bus_dma_segment_t *, int,
off_t, int, int);
int bus_dmatag_subregion(bus_dma_tag_t, bus_addr_t, bus_addr_t,
bus_dma_tag_t *, int);
void bus_dmatag_destroy(bus_dma_tag_t);
#endif /* _SYS_BUS_PROTO_H_ */