Use psci_fdt_bootstrap for MP spinup on Tegra210.

This commit is contained in:
jmcneill 2018-07-08 11:37:50 +00:00
parent 886b6dfbaa
commit 9b4fa6e5ac
3 changed files with 5 additions and 91 deletions

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@ -1,4 +1,4 @@
# $NetBSD: files.tegra,v 1.48 2018/04/01 04:35:04 ryo Exp $
# $NetBSD: files.tegra,v 1.49 2018/07/08 11:37:50 jmcneill Exp $
#
# Configuration info for NVIDIA Tegra ARM Peripherals
#
@ -13,9 +13,6 @@ device tegra124cpu
attach tegra124cpu at cpu with tegra124_cpu
file arch/arm/nvidia/tegra124_cpu.c tegra124_cpu
# Tegra T210 (X1) support
file arch/arm/nvidia/soc_tegra210.c soc_tegra210
# Interrupt controller
device tegralic
attach tegralic at fdt with tegra_lic

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@ -1,83 +0,0 @@
/* $NetBSD: soc_tegra210.c,v 1.2 2018/07/07 20:16:16 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared D. McNeill <jmcneill@invisible.ca>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include "opt_tegra.h"
#include "opt_multiprocessor.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: soc_tegra210.c,v 1.2 2018/07/07 20:16:16 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/cpu.h>
#include <sys/device.h>
#include <sys/atomic.h>
#include <uvm/uvm_extern.h>
#include <dev/fdt/fdtvar.h>
#include <arm/cpufunc.h>
#include <arm/locore.h>
#include <arm/nvidia/tegra_reg.h>
#include <arm/nvidia/tegra_pmcreg.h>
#include <arm/nvidia/tegra_var.h>
#define EVP_RESET_VECTOR_0_REG 0x100
void
tegra210_mpinit(void)
{
#if defined(MULTIPROCESSOR)
extern void cortex_mpstart(void);
bus_space_tag_t bst = &arm_generic_bs_tag;
bus_space_handle_t bsh;
bus_space_subregion(bst, tegra_ppsb_bsh,
TEGRA_EVP_OFFSET, TEGRA_EVP_SIZE, &bsh);
arm_cpu_max = 4;
bus_space_write_4(bst, bsh, EVP_RESET_VECTOR_0_REG,
(uint32_t)cortex_mpstart);
bus_space_barrier(bst, bsh, EVP_RESET_VECTOR_0_REG, 4,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
uint32_t started = 0;
tegra_pmc_power(PMC_PARTID_CPU1, true); started |= __BIT(1);
tegra_pmc_power(PMC_PARTID_CPU2, true); started |= __BIT(2);
tegra_pmc_power(PMC_PARTID_CPU3, true); started |= __BIT(3);
for (u_int i = 0x10000000; i > 0; i--) {
membar_consumer();
if (arm_cpu_hatched == started)
break;
}
#endif
}

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@ -1,4 +1,4 @@
/* $NetBSD: tegra_platform.c,v 1.12 2018/07/07 20:16:16 jmcneill Exp $ */
/* $NetBSD: tegra_platform.c,v 1.13 2018/07/08 11:37:50 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared D. McNeill <jmcneill@invisible.ca>
@ -33,7 +33,7 @@
#include "ukbd.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: tegra_platform.c,v 1.12 2018/07/07 20:16:16 jmcneill Exp $");
__KERNEL_RCSID(0, "$NetBSD: tegra_platform.c,v 1.13 2018/07/08 11:37:50 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@ -108,8 +108,8 @@ tegra210_platform_bootstrap(void)
{
tegra_bootstrap();
#ifdef MULTIPROCESSOR
tegra210_mpinit();
#if defined(MULTIPROCESSOR) && defined(__aarch64__)
psci_fdt_bootstrap();
#endif
}
#endif