Run the MicroSPARC IIep PCI bus without endianness translation.
This allows us to run X without any additional code changes.
This commit is contained in:
macallan
parent
c7f8eb7c46
commit
9a8bbeeb14
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@ -1,4 +1,4 @@
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/* $NetBSD: autoconf.c,v 1.211 2005/09/23 23:22:57 uwe Exp $ */
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/* $NetBSD: autoconf.c,v 1.212 2005/09/24 22:30:15 macallan Exp $ */
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/*
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* Copyright (c) 1996
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@ -48,7 +48,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.211 2005/09/23 23:22:57 uwe Exp $");
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__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.212 2005/09/24 22:30:15 macallan Exp $");
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#include "opt_ddb.h"
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#include "opt_kgdb.h"
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@ -466,20 +466,12 @@ bootstrapIIep()
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MSIIEP_PCIC_VA, &bh) != 0)
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panic("bootstrap: unable to map ms-IIep pcic registers");
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/* verify that it's PCIC (it's still little-endian at this point) */
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id = le32toh(mspcic_read_4(pcic_id));
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/* verify that it's PCIC */
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id = mspcic_read_4(pcic_id);
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if (PCI_VENDOR(id) != PCI_VENDOR_SUN
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&& PCI_PRODUCT(id) != PCI_PRODUCT_SUN_MS_IIep)
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panic("bootstrap: PCI id %08x", id);
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/* turn on automagic endian-swapping for PCI accesses */
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msiiep_swap_endian(1);
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/* sanity check (it's big-endian now!) */
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id = mspcic_read_4(pcic_id);
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if (PCI_VENDOR(id) != PCI_VENDOR_SUN
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&& PCI_PRODUCT(id) != PCI_PRODUCT_SUN_MS_IIep)
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panic("bootstrap: PCI id %08x (big-endian mode)", id);
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}
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#undef msiiep
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@ -1024,10 +1016,6 @@ void
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sync_crash()
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{
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#if defined(MSIIEP)
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/* we are back from prom */
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msiiep_swap_endian(1);
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#endif
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panic("PROM sync command");
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: intr.c,v 1.89 2005/09/23 23:22:57 uwe Exp $ */
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/* $NetBSD: intr.c,v 1.90 2005/09/24 22:30:15 macallan Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -41,7 +41,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.89 2005/09/23 23:22:57 uwe Exp $");
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__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.90 2005/09/24 22:30:15 macallan Exp $");
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#include "opt_multiprocessor.h"
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#include "opt_sparc_arch.h"
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@ -434,8 +434,6 @@ nmi_hard_msiiep(void)
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fatal = 0;
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}
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byteswap = mspcic_read_1(pcic_pio_ctrl) & MSIIEP_PIO_CTRL_BIG_ENDIAN;
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if (si & MSIIEP_SYS_IPR_SERR) { /* XXX */
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printf("serr#\n");
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fatal = 0;
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@ -444,9 +442,6 @@ nmi_hard_msiiep(void)
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if (si & MSIIEP_SYS_IPR_DMA_ERR) {
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uint32_t iotlb_err_addr = mspcic_read_4(pcic_iotlb_err_addr);
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if (byteswap)
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iotlb_err_addr = bswap32(iotlb_err_addr);
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printf("dma: %08x\n", iotlb_err_addr);
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fatal = 0;
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}
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@ -454,9 +449,6 @@ nmi_hard_msiiep(void)
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if (si & MSIIEP_SYS_IPR_PIO_ERR) {
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uint32_t pio_err_addr = mspcic_read_4(pcic_pio_err_addr);
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if (byteswap)
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pio_err_addr = bswap32(pio_err_addr);
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printf("pio: addr=%08x, cmd=%x\n",
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pio_err_addr, mspcic_read_1(pcic_pio_err_cmd));
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fatal = 0;
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.s,v 1.217 2005/09/10 01:27:54 uwe Exp $ */
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/* $NetBSD: locore.s,v 1.218 2005/09/24 22:30:15 macallan Exp $ */
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/*
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* Copyright (c) 1996 Paul Kranenburg
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@ -2628,19 +2628,20 @@ _ENTRY(_C_LABEL(sparc_interrupt4m))
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#else /* MSIIEP */
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sethi %hi(MSIIEP_PCIC_VA), %l6
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mov 1, %l4
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xor %l3, 0x18, %l7 ! change endianness of the resulting bit mask
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ld [%l6 + PCIC_PROC_IPR_REG], %l5 ! get pending interrupts
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sll %l4, %l3, %l4 ! hw intr bits are in the lower halfword
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sll %l4, %l7, %l4 ! hw intr bits are in the upper halfword
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! because the register is little-endian
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btst %l4, %l5 ! has pending hw intr at this level?
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bnz sparc_interrupt_common
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nop
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srl %l4, 16, %l4 ! move the mask bit into the lower 16 bit
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! so we can use it to clear a sw interrupt
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#ifdef DIAGNOSTIC
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! softint pending bits are in the upper halfword, but softint
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! clear bits are in the lower halfword so we want the bit in %l4
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! kept in the lower half and instead shift pending bits right
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srl %l5, 16, %l7
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btst %l4, %l7 ! make sure softint pending bit is set
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! check if there's really a sw interrupt pending
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btst %l4, %l5 ! make sure softint pending bit is set
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bnz softintr_common
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sth %l4, [%l6 + PCIC_SOFT_INTR_CLEAR_REG]
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/* FALLTHROUGH to sparc_interrupt4m_bogus */
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@ -3207,10 +3208,10 @@ nmi_sun4m:
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* Level 15 interrupts are nonmaskable, so with traps off,
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* disable all interrupts to prevent recursion.
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*/
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set MSIIEP_SYS_ITMR_ALL, %l4
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mov 0x80, %l4 ! htole32(MSIIEP_SYS_ITMR_ALL)
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st %l4, [%l6 + PCIC_SYS_ITMR_SET_REG]
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set (1 << 15), %l4
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set (1 << 23), %l4 ! htole32(1 << 15)
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btst %l4, %l5 ! has pending level 15 hw intr?
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bz 1f
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nop
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@ -3221,6 +3222,7 @@ nmi_sun4m:
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or %o3, %lo(_C_LABEL(nmi_hard_msiiep)), %o3
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1: /* soft level 15 interrupt */
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set (1 << 7), %l4 ! htole16(1 << 15)
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sth %l4, [%l6 + PCIC_SOFT_INTR_CLEAR_REG]
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set _C_LABEL(nmi_soft_msiiep), %o3
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2:
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@ -3250,7 +3252,7 @@ nmi_sun4m:
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! enable interrupts again (safe, we disabled traps again above)
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sethi %hi(MSIIEP_PCIC_VA), %o0
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set MSIIEP_SYS_ITMR_ALL, %o1
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mov 0x80, %o1 ! htole32(MSIIEP_SYS_ITMR_ALL)
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st %o1, [%o0 + PCIC_SYS_ITMR_CLR_REG]
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b return_from_trap
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@ -6406,6 +6408,7 @@ ENTRY(raise)
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st %o2, [%o1]
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#else /* MSIIEP - ignore %o0, only one CPU ever */
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mov 1, %o2
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xor %o1, 8, %o1 ! change 'endianness' of the shift distance
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sethi %hi(MSIIEP_PCIC_VA), %o0
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sll %o2, %o1, %o2
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retl
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@ -6600,22 +6603,38 @@ ENTRY(microtime)
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2:
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ldd [%g2+%lo(_C_LABEL(time))], %o2 ! time.tv_sec & time.tv_usec
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ld [%g3], %o4 ! system (timer) counter
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ld [%g3], %o4 ! system (timer) counter, little endian
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ldd [%g2+%lo(_C_LABEL(time))], %g4 ! see if time values changed
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cmp %g4, %o2
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bne 2b ! if time.tv_sec changed
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cmp %g5, %o3
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bne 2b ! if time.tv_usec changed
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tst %o4
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btst 0x80, %o4 ! test overflow flag, LE
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!! %o2 - time.tv_sec; %o3 - time.tv_usec; %o4 - timer counter
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!!! BEGIN ms-IIep specific code
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bpos 3f ! if limit not reached yet
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bz 3f ! if limit not reached yet
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clr %g4 ! then use timer as is
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! now we're sure we need the timer value so let's endian-swap it
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! %o4 = le32toh(%o4)
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! since we're going to overwrite %g4 anyway we can use it
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! for intermediate values here
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mov %o4, %o2
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set 0xff00ff, %g4
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sll %o4, 16, %o4 ! first swap the upper and lower 16 bit
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srl %o2, 16, %o2
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or %o2, %o4, %o4 ! result in %o4
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and %o4, %g4, %o2 ! now grab byte 0 and 2
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andn %o4, %g4, %o4 ! %o4 now contains byte 1 and 3
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srl %o4, 8, %o4 ! shift them so they swap positions
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sll %o2, 8, %o2
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or %o2, %o4, %o4 ! put them back together.
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set 0x80000000, %g5
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sethi %hi(_C_LABEL(tick)), %g4
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bclr %g5, %o4 ! cleat limit reached flag
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bclr %g5, %o4 ! clear limit reached flag
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ld [%g4+%lo(_C_LABEL(tick))], %g4
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!! %g4 - either 0 or tick (if timer has hit the limit)
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@ -1,4 +1,4 @@
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/* $NetBSD: msiiep.c,v 1.27 2005/09/24 00:49:23 uwe Exp $ */
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/* $NetBSD: msiiep.c,v 1.28 2005/09/24 22:30:15 macallan Exp $ */
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/*
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* Copyright (c) 2001 Valeriy E. Ushakov
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@ -27,7 +27,7 @@
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: msiiep.c,v 1.27 2005/09/24 00:49:23 uwe Exp $");
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__KERNEL_RCSID(0, "$NetBSD: msiiep.c,v 1.28 2005/09/24 22:30:15 macallan Exp $");
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#include <sys/param.h>
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#include <sys/malloc.h>
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@ -167,8 +167,18 @@ static struct sparc_bus_dma_tag mspcic_dma_tag = {
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_bus_dmamem_mmap
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};
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static uint16_t mspcic_bus_read_2(bus_space_tag_t, bus_space_handle_t,
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bus_size_t);
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static uint32_t mspcic_bus_read_4(bus_space_tag_t, bus_space_handle_t,
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bus_size_t);
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static uint64_t mspcic_bus_read_8(bus_space_tag_t, bus_space_handle_t,
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bus_size_t);
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static void mspcic_bus_write_2(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint16_t);
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static void mspcic_bus_write_4(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint32_t);
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static void mspcic_bus_write_8(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint64_t);
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static int
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@ -184,8 +194,7 @@ msiiep_match(struct device *parent, struct cfdata *cf, void *aux)
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/*
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* Verify that PCIC was successfully mapped by bootstrap code.
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* Since PCIC contains all the registers vital to the kernel,
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* bootstrap code maps them at a fixed va, MSIIEP_PCIC_VA, and
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* switches the endian-swapping mode on.
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* bootstrap code maps them at a fixed va, MSIIEP_PCIC_VA
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*/
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id = mspcic_read_4(pcic_id);
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if (PCI_VENDOR(id) != PCI_VENDOR_SUN
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@ -201,7 +210,10 @@ msiiep_attach(struct device *parent, struct device *self, void *aux)
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{
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struct mainbus_attach_args *ma = aux;
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struct msiiep_attach_args msa;
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bus_space_handle_t hmid;
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struct cpu_info *cur;
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uint32_t mid;
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aprint_normal("\n");
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/* pass on real mainbus_attach_args */
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@ -245,6 +257,56 @@ msiiep_swap_endian(int on)
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*
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* Real ms-IIep PCIC driver.
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*/
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static uint16_t
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mspcic_bus_read_2(bus_space_tag_t space, bus_space_handle_t handle,
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bus_size_t offset)
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{
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uint16_t val = *(volatile uint16_t *)(handle + offset);
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return le16toh(val);
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}
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static uint32_t
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mspcic_bus_read_4(bus_space_tag_t space, bus_space_handle_t handle,
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bus_size_t offset)
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{
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uint32_t val = *(volatile uint32_t *)(handle + offset);
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return le32toh(val);
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}
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static uint64_t
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mspcic_bus_read_8(bus_space_tag_t space, bus_space_handle_t handle,
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bus_size_t offset)
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{
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uint64_t val = *(volatile uint64_t *)(handle + offset);
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return le64toh(val);
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}
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static void
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mspcic_bus_write_2(bus_space_tag_t space, bus_space_handle_t handle,
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bus_size_t offset, uint16_t value)
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{
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(*(volatile uint16_t *)(handle + offset)) = htole16(value);
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}
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static void
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mspcic_bus_write_4(bus_space_tag_t space, bus_space_handle_t handle,
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bus_size_t offset, uint32_t value)
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{
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(*(volatile uint32_t *)(handle + offset)) = htole32(value);
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}
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static void
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mspcic_bus_write_8(bus_space_tag_t space, bus_space_handle_t handle,
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bus_size_t offset, uint64_t value)
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{
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(*(volatile uint64_t *)(handle + offset)) = htole64(value);
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}
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static int
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mspcic_match(struct device *parent, struct cfdata *cf, void *aux)
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@ -289,6 +351,13 @@ mspcic_attach(struct device *parent, struct device *self, void *aux)
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mspcic_io_tag.sparc_bus_mmap = mspcic_bus_mmap;
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mspcic_io_tag.sparc_intr_establish = mspcic_intr_establish;
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mspcic_io_tag.parent = sc->sc_bustag;
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mspcic_io_tag.sparc_read_2 = mspcic_bus_read_2;
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mspcic_io_tag.sparc_read_4 = mspcic_bus_read_4;
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mspcic_io_tag.sparc_read_8 = mspcic_bus_read_8;
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mspcic_io_tag.sparc_write_2 = mspcic_bus_write_2;
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mspcic_io_tag.sparc_write_4 = mspcic_bus_write_4;
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mspcic_io_tag.sparc_write_8 = mspcic_bus_write_8;
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mspcic_mem_tag = *sc->sc_bustag;
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mspcic_mem_tag.cookie = &mspcic_mem_cookie;
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@ -299,6 +368,13 @@ mspcic_attach(struct device *parent, struct device *self, void *aux)
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mspcic_mem_tag.sparc_intr_establish = mspcic_intr_establish;
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mspcic_mem_tag.parent = sc->sc_bustag;
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mspcic_mem_tag.sparc_read_2 = mspcic_bus_read_2;
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mspcic_mem_tag.sparc_read_4 = mspcic_bus_read_4;
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mspcic_mem_tag.sparc_read_8 = mspcic_bus_read_8;
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mspcic_mem_tag.sparc_write_2 = mspcic_bus_write_2;
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mspcic_mem_tag.sparc_write_4 = mspcic_bus_write_4;
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mspcic_mem_tag.sparc_write_8 = mspcic_bus_write_8;
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mspcic_dma_tag._cookie = sc;
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mspcic_pc_tag.cookie = sc;
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@ -401,7 +477,7 @@ mspcic_init_maps(void)
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mspcic_read_1(pcic_iosize));
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#endif
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nmem = nio = 1;
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m0 = &mspcic_pci_memmap[nmem];
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mspcic_pci_map_from_reg(m0,
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mspcic_read_1(pcic_smbar0), mspcic_read_1(pcic_pmbar0),
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@ -1,4 +1,4 @@
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/* $NetBSD: msiiepreg.h,v 1.5 2005/09/24 00:12:20 uwe Exp $ */
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/* $NetBSD: msiiepreg.h,v 1.6 2005/09/24 22:30:15 macallan Exp $ */
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/*
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* Copyright (c) 2001 Valeriy E. Ushakov
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@ -49,6 +49,11 @@
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*/
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#define MSIIEP_PCIC_PA ((paddr_t)0x300c0000)
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#define MSIIEP_MID_PA ((paddr_t)0x10002000)
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#define MID_IOA_ENABLE 0x10000 /* IO arbitration */
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#define MID_STANDBY 0x0800 /* put CPU into power saving mode */
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#define MID_MASK 0x000108fc /* bits masked out are reserved */
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struct msiiep_pcic_reg {
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/* PCI_ID_REG */
|
||||
|
|
@ -226,19 +231,20 @@ struct msiiep_pcic_reg {
|
|||
};
|
||||
|
||||
|
||||
|
||||
/* XXX: these are temporary hacks to for the conversion of the sources */
|
||||
#define mspcic_read_1(reg) \
|
||||
(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg)
|
||||
#define mspcic_read_2(reg) \
|
||||
(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg)
|
||||
(le16toh(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg))
|
||||
#define mspcic_read_4(reg) \
|
||||
(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg)
|
||||
(le32toh(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg))
|
||||
|
||||
#define mspcic_write_1(reg, val) \
|
||||
(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg) = (val)
|
||||
#define mspcic_write_2(reg, val) \
|
||||
(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg) = (val)
|
||||
(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg) = (htole16(val))
|
||||
#define mspcic_write_4(reg, val) \
|
||||
(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg) = (val)
|
||||
(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg) = (htole32(val))
|
||||
|
||||
#endif /* _SPARC_MSIIEP_REG_H_ */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: openfirm.c,v 1.10 2005/05/31 00:54:57 christos Exp $ */
|
||||
/* $NetBSD: openfirm.c,v 1.11 2005/09/24 22:30:15 macallan Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (C) 1995, 1996 Wolfgang Solfrank.
|
||||
|
|
@ -32,7 +32,7 @@
|
|||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: openfirm.c,v 1.10 2005/05/31 00:54:57 christos Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: openfirm.c,v 1.11 2005/09/24 22:30:15 macallan Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
|
|
@ -583,13 +583,7 @@ OF_enter(void)
|
|||
args.name = ADR2CELL("enter");
|
||||
args.nargs = 0;
|
||||
args.nreturns = 0;
|
||||
#if defined(MSIIEP)
|
||||
msiiep_swap_endian(0);
|
||||
#endif
|
||||
openfirmware(&args);
|
||||
#if defined(MSIIEP)
|
||||
msiiep_swap_endian(1);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -604,13 +598,7 @@ OF_exit(void)
|
|||
args.name = ADR2CELL("exit");
|
||||
args.nargs = 0;
|
||||
args.nreturns = 0;
|
||||
#if defined(MSIIEP)
|
||||
msiiep_swap_endian(0);
|
||||
#endif
|
||||
openfirmware(&args);
|
||||
#if defined(MSIIEP)
|
||||
msiiep_swap_endian(1);
|
||||
#endif
|
||||
panic("OF_exit failed");
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: pci_machdep.c,v 1.10 2005/09/24 01:07:25 uwe Exp $ */
|
||||
/* $NetBSD: pci_machdep.c,v 1.11 2005/09/24 22:30:15 macallan Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1999, 2000 Matthew R. Green
|
||||
|
|
@ -35,7 +35,7 @@
|
|||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.10 2005/09/24 01:07:25 uwe Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.11 2005/09/24 22:30:15 macallan Exp $");
|
||||
|
||||
#if defined(DEBUG) && !defined(SPARC_PCI_DEBUG)
|
||||
#define SPARC_PCI_DEBUG
|
||||
|
|
@ -305,12 +305,8 @@ pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
|
|||
mode1_data_reg_pa = PCI_MODE1_DATA_REG_PA
|
||||
| (reg & PCI_MODE1_DATA_REG_MASK);
|
||||
|
||||
/*
|
||||
* NB: we run in endian-swapping mode, so we don't need to
|
||||
* convert mode1_addr and val.
|
||||
*/
|
||||
sta(PCI_MODE1_ADDRESS_REG_PA, ASI_BYPASS, mode1_addr);
|
||||
val = lda(mode1_data_reg_pa, ASI_BYPASS);
|
||||
sta(PCI_MODE1_ADDRESS_REG_PA, ASI_BYPASS, htole32(mode1_addr));
|
||||
val = le32toh(lda(mode1_data_reg_pa, ASI_BYPASS));
|
||||
|
||||
DPRINTF(SPDB_CONF, ("reading %08x\n", val));
|
||||
|
||||
|
|
@ -348,12 +344,8 @@ pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
|
|||
|
||||
DPRINTF(SPDB_CONF, ("writing %08x\n", data));
|
||||
|
||||
/*
|
||||
* NB: we run in endian-swapping mode, so we don't need to
|
||||
* convert mode1_addr and data.
|
||||
*/
|
||||
sta(PCI_MODE1_ADDRESS_REG_PA, ASI_BYPASS, mode1_addr);
|
||||
sta(mode1_data_reg_pa, ASI_BYPASS, data);
|
||||
sta(PCI_MODE1_ADDRESS_REG_PA, ASI_BYPASS, htole32(mode1_addr));
|
||||
sta(mode1_data_reg_pa, ASI_BYPASS, htole32(data));
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue