Remove un-necessary write buffer drains. (From Neil Carson).
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@ -1,4 +1,4 @@
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/* $NetBSD: cpufunc_asm.S,v 1.6 1998/06/09 01:02:14 mark Exp $ */
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/* $NetBSD: cpufunc_asm.S,v 1.7 1998/07/08 00:13:41 mark Exp $ */
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/*
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* arm8 support code Copyright (c) 1997 ARM Limited
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@ -256,12 +256,10 @@ ENTRY(arm8_tlb_flushID_SE)
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#ifdef CPU_SA110
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ENTRY(sa110_tlb_flushID)
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mcr 15, 0, r0, c7, c10, 4 /* drain write buffer */ /* XXX */
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mcr 15, 0, r0, c8, c7, 0 /* flush I+D tlb */
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mov pc, lr
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ENTRY(sa110_tlb_flushID_SE)
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mcr 15, 0, r0, c7, c10, 4 /* drain write buffer */ /* XXX */
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mcr 15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
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mcr 15, 0, r0, c8, c5, 0 /* flush I tlb */
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mov pc, lr
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@ -271,7 +269,6 @@ ENTRY(sa110_tlb_flushI)
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mov pc, lr
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ENTRY(sa110_tlb_flushD)
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mcr 15, 0, r0, c7, c10, 4 /* drain write buffer */ /* XXX */
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mcr 15, 0, r0, c8, c6, 0 /* flush D tlb */
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mov pc, lr
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@ -500,7 +497,6 @@ Lsa110_cache_cleanD_loop:
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subs r1, r1, #32
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bne Lsa110_cache_cleanD_loop
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mcr 15, 0, r0, c7, c10, 4 /* drain write buffer */
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msr cpsr_all , r3
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mov pc, lr
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@ -519,7 +515,6 @@ Lsa110_cache_purgeID_loop:
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subs r1, r1, #32
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bne Lsa110_cache_purgeID_loop
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mcr 15, 0, r0, c7, c10, 4 /* drain write buffer */
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mcr 15, 0, r0, c7, c5, 0 /* flush I cache (D flushed above) */
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msr cpsr_all , r3
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mov pc, lr
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@ -538,21 +533,17 @@ Lsa110_cache_purgeD_loop:
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subs r1, r1, #32
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bne Lsa110_cache_purgeD_loop
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mcr 15, 0, r0, c7, c10, 4 /* drain write buffer */
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/* mcr 15, 0, r0, c7, c6, 0*/ /* flush D cache */
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msr cpsr_all , r3
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mov pc, lr
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ENTRY(sa110_cache_purgeID_E)
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mcr 15, 0, r0, c7, c10, 1 /* clean dcache entry */
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mcr 15, 0, r0, c7, c10, 4 /* drain write buffer */
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mcr 15, 0, r0, c7, c5, 0 /* flush I cache */
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mcr 15, 0, r0, c7, c6, 1 /* flush D cache single entry */
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mov pc, lr
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ENTRY(sa110_cache_purgeD_E)
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mcr 15, 0, r0, c7, c10, 1 /* clean dcache entry */
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mcr 15, 0, r0, c7, c10, 4 /* drain write buffer */
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mcr 15, 0, r0, c7, c6, 1 /* flush D cache single entry */
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mov pc, lr
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#endif /* CPU_SA110 */
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@ -572,10 +563,6 @@ ENTRY(sa110_drain_writebuf)
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*/
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#ifdef CPU_SA110
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/*
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* These functions need to be written. Until then act on the whole cache
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*/
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ENTRY(sa110_cache_syncI)
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mrs r3, cpsr_all
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orr r0, r3, #(I32_bit | F32_bit)
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@ -590,7 +577,6 @@ Lsa110_cache_syncI_loop:
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subs r1, r1, #32
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bne Lsa110_cache_syncI_loop
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mcr 15, 0, r0, c7, c10, 4 /* drain write buffer */
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mcr 15, 0, r0, c7, c5, 0 /* flush I cache */
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msr cpsr_all , r3
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mov pc, lr
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@ -610,8 +596,6 @@ sa110_cache_cleanD_rng_loop:
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subs r1, r1, #32
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bpl sa110_cache_cleanD_rng_loop
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mcr 15, 0, r0, c7, c10, 4 /* drain write buffer */
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mov pc, lr
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ENTRY(sa110_cache_purgeID_rng)
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@ -629,7 +613,6 @@ sa110_cache_purgeID_rng_loop:
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subs r1, r1, #32
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bpl sa110_cache_purgeID_rng_loop
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mcr 15, 0, r0, c7, c10, 4 /* drain write buffer */
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mcr 15, 0, r0, c7, c5, 0 /* flush I cache */
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mov pc, lr
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@ -649,8 +632,6 @@ sa110_cache_purgeD_rng_loop:
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subs r1, r1, #32
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bpl sa110_cache_purgeD_rng_loop
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mcr 15, 0, r0, c7, c10, 4 /* drain write buffer */
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mov pc, lr
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ENTRY(sa110_cache_syncI_rng)
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@ -667,7 +648,6 @@ sa110_cache_syncI_rng_loop:
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subs r1, r1, #32
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bpl sa110_cache_syncI_rng_loop
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mcr 15, 0, r0, c7, c10, 4 /* drain write buffer */
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mcr 15, 0, r0, c7, c5, 0 /* flush I cache */
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mov pc, lr
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@ -688,21 +668,21 @@ ENTRY(arm67_context_switch)
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/* Switch the memory to the new process */
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/* For good measure we will flush the IDC as well */
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mcr 15, 0, r0, c7, c0, 0 /* flush cache */
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mcr 15, 0, r0, c7, c0, 0 /* flush cache */
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/* Write the TTB */
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mcr 15, 0, r0, c2, c0, 0
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mcr 15, 0, r0, c2, c0, 0
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/* If we have updated the TTB we must flush the TLB */
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mcr 15, 0, r0, c5, c0, 0
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mcr 15, 0, r0, c5, c0, 0
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/* For good measure we will flush the IDC as well */
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mcr 15, 0, r0, c7, c0, 0
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/* mcr 15, 0, r0, c7, c0, 0*/
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/* Make sure that pipeline is emptied */
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mov r0, r0
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mov r0, r0
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mov pc, r14
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mov r0, r0
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mov r0, r0
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mov pc, r14
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#endif
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#ifdef CPU_ARM8
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@ -713,18 +693,18 @@ ENTRY(arm8_context_switch)
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mcr 15, 0, r0, c7, c7, 0 /* flush i+d cache */
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/* Write the TTB */
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mcr 15, 0, r0, c2, c0, 0
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mcr 15, 0, r0, c2, c0, 0
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/* If we have updated the TTB we must flush the TLB */
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mcr 15, 0, r0, c8, c7, 0 /* flush the i+d tlb */
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mcr 15, 0, r0, c8, c7, 0 /* flush the i+d tlb */
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/* For good measure we will flush the IDC as well */
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mcr 15, 0, r0, c7, c7, 0 /* flush the i+d cache */
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/* mcr 15, 0, r0, c7, c7, 0*/ /* flush the i+d cache */
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/* Make sure that pipeline is emptied */
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mov r0, r0
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mov r0, r0
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mov pc, r14
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mov r0, r0
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mov r0, r0
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mov pc, r14
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#endif /* CPU_ARM8 */
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#ifdef CPU_SA110
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@ -737,23 +717,16 @@ ENTRY(sa110_context_switch)
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* and the instruction cache will contain only kernel code
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*/
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/* For good measure we will flush the IDC as well */
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/* mcr 15, 0, r0, c7, c10, 4*/ /* drain write buffer */
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/* mcr 15, 0, r0, c7, c7, 0*/ /* flush i+d cache */
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/* Write the TTB */
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mcr 15, 0, r0, c2, c0, 0
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mcr 15, 0, r0, c2, c0, 0
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/* If we have updated the TTB we must flush the TLB */
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mcr 15, 0, r0, c8, c7, 0 /* flush the i+d tlb */
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/* For good measure we will flush the IDC as well */
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/* mcr 15, 0, r0, c7, c7, 0*/ /* flush the i+d cache */
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mcr 15, 0, r0, c8, c7, 0 /* flush the i+d tlb */
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/* Make sure that pipeline is emptied */
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mov r0, r0
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mov r0, r0
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mov pc, r14
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mov r0, r0
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mov r0, r0
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mov pc, r14
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#endif
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/*
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