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Rename DVMA constants.

This commit is contained in:
pk 1998-08-23 09:53:03 +00:00
parent 32a1e28254
commit 9a2b941ecb
2 changed files with 33 additions and 17 deletions
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17
sys/arch/sparc/sparc/iommu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: iommu.c,v 1.21 1998/08/21 14:13:54 pk Exp $ */
/* $NetBSD: iommu.c,v 1.22 1998/08/23 09:53:47 pk Exp $ */
/*
* Copyright (c) 1996
@ -241,7 +241,7 @@ iommu_attach(parent, self, aux)
* changes.
*/
kvm_uncache((caddr_t)sc->sc_ptes,
(((0 - DVMA4M_BASE)/sc->sc_pagesize) * sizeof(iopte_t)) / NBPG);
(((0 - IOMMU_DVMA_BASE)/sc->sc_pagesize) * sizeof(iopte_t)) / NBPG);
/*
* Ok. We've got to read in the original table using MMU bypass,
@ -257,14 +257,14 @@ iommu_attach(parent, self, aux)
((mmupcrsave = lda(SRMMU_PCR, ASI_SRMMU)) | VIKING_PCR_AC));
}
for (tpte_p = &sc->sc_ptes[((0 - DVMA4M_BASE)/NBPG) - 1],
for (tpte_p = &sc->sc_ptes[((0 - IOMMU_DVMA_BASE)/NBPG) - 1],
pa = (u_int)pbase - sizeof(iopte_t) +
((u_int)sc->sc_range/NBPG)*sizeof(iopte_t);
tpte_p >= &sc->sc_ptes[0] && pa >= (u_int)pbase;
tpte_p--, pa -= sizeof(iopte_t)) {
IOMMU_FLUSHPAGE(sc,
(tpte_p - &sc->sc_ptes[0])*NBPG + DVMA4M_BASE);
(tpte_p - &sc->sc_ptes[0])*NBPG + IOMMU_DVMA_BASE);
*tpte_p = lda(pa, ASI_BYPASS);
}
if (cpuinfo.cpu_impl == 4 && cpuinfo.mxcc) {
@ -275,8 +275,8 @@ iommu_attach(parent, self, aux)
/*
* Now we can install our new pagetable into the IOMMU
*/
sc->sc_range = 0 - DVMA4M_BASE;
sc->sc_dvmabase = DVMA4M_BASE;
sc->sc_range = 0 - IOMMU_DVMA_BASE;
sc->sc_dvmabase = IOMMU_DVMA_BASE;
/* calculate log2(sc->sc_range/16MB) */
i = ffs(sc->sc_range/(1 << 24)) - 1;
@ -305,8 +305,11 @@ iommu_attach(parent, self, aux)
else
bp = NULL;
iommu_dvmamap = extent_create("iommudvma", DVMA4M_BASE, DVMA4M_END,
iommu_dvmamap = extent_create("iommudvma",
IOMMU_DVMA_BASE, IOMMU_DVMA_END,
M_DEVBUF, 0, 0, EX_NOWAIT);
if (iommu_dvmamap == NULL)
panic("iommu: unable to allocate DVMA map");
/*
* Loop through ROM children (expect Sbus among them).

33
sys/arch/sparc/sparc/vaddrs.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: vaddrs.h,v 1.8 1997/03/10 23:54:41 pk Exp $ */
/* $NetBSD: vaddrs.h,v 1.9 1998/08/23 09:53:03 pk Exp $ */
/*
* Copyright (c) 1996
@ -89,16 +89,27 @@
#define IODEV_BASE ( SI_INTR_VA + _MAXNBPG)
#define IODEV_END 0xff000000 /* 16 MB of iospace */
#define DVMA_BASE 0xfff00000
#define DVMA_END 0xfffc0000
/*
* DVMA range for 24 bit devices.
*/
#define D24_DVMA_BASE 0xff000000
#define D24_DVMA_END VME4_DVMA_BASE
/*
* DMA on sun4 VME devices use the last MB of virtual space, which
* is mapped by hardware onto the first MB of VME space.
* The DVMA area ends before the PROM mappings appear in the address space.
*/
#define VME4_DVMA_BASE 0xfff00000
#define VME4_DVMA_END 0xfffc0000
/*
* The next constant defines the amount of reserved DVMA space on the
* Sun4m. The amount of space *must* be a multiple of 16MB, and thus
* (((u_int)0) - DVMA4M_BASE) must be divisible by 16*1024*1024!
* (((u_int)0) - IOMMU_DVMA_BASE) must be divisible by 16*1024*1024!
* Note that pagetables must be allocated at a cost of 1k per MB of DVMA
* space, plus severe alignment restrictions. So don't make DVMA4M_BASE too
* low (max space = 2G).
* space, plus severe alignment restrictions. So don't make IOMMU_DVMA_BASE
* too low (max space = 2G).
*
* Since DVMA space overlaps with normal kernel address space (notably
* the device mappings and the PROM), we don't want to put any DVMA
@ -111,10 +122,12 @@
* avoid consistency problems, DVMA addresses must map to the same place
* in both processor and IOMMU space.
*/
#define DVMA4M_BASE 0xfc000000 /* can change subject to above rule */
#define DVMA4M_TOP 0xffffffff /* do not modify */
#define DVMA4M_START 0xfd000000 /* 16M of DVMA */
#define DVMA4M_END 0xfe000000 /* XXX is this enough? */
#define IOMMU_DVMA_BASE 0xfc000000 /* can change subject to above rule */
#if 0
#define IOMMU_DVMA_TOP 0xffffffff /* do not modify */
#define IOMMU_DVMA_START 0xfd000000 /* 16M of DVMA */
#endif
#define IOMMU_DVMA_END 0xfe000000 /* XXX is this enough? */
/*
* Virtual address of the per cpu `cpu_softc' structure.