Move the RTL8029 register definitions to <dev/ic/rtl80x9reg.h>, and add
the registers/bits present in the RTL8019 (ISA version).
This commit is contained in:
thorpej
parent
de14bf4f80
commit
992f2906ba
@ -1,4 +1,4 @@
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/* $NetBSD: if_ne_pcireg.h,v 1.1 1998/10/27 22:30:56 thorpej Exp $ */
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/* $NetBSD: rtl80x9reg.h,v 1.1 1998/10/31 00:27:43 thorpej Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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@ -38,21 +38,26 @@
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*/
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/*
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* Register description for NE2000-compatible PCI Ethernet interfaces.
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*/
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/*
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* Registers on RealTek 8029 NE2000-compatible network interfaces.
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* Registers on RealTek 8019 and 8029 NE2000-compatible network interfaces.
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*
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* Data sheets for this chip can be found at:
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* Data sheets for these chips can be found at:
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*
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* http://www.realtek.com.tw
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*/
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/*
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* Page 0 register offsets.
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*/
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#define NERTL_RTL0_8019ID0 0x0a /* 8019 ID Register 0 */
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#define RTL0_8019ID0 'P'
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#define NERTL_RTL0_8019ID1 0x0b /* 8019 ID Register 1 */
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#define RTL0_8019ID1 'p'
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/*
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* Page 3 register offsets.
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*/
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#define NEPCI_RTL3_EECR 0x01 /* EEPROM Command Register */
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#define NERTL_RTL3_EECR 0x01 /* EEPROM Command Register */
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#define RTL3_EECR_EEM1 0x80 /* EEPROM Operating Mode */
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#define RTL3_EECR_EEM0 0x40
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/* 0 0 Normal operation */
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@ -64,26 +69,70 @@
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#define RTL3_EECR_EEDI 0x02 /* EEPROM Data In */
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#define RTL3_EECR_EEDO 0x01 /* EEPROM Data Out */
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#define NEPCI_RTL3_CONFIG0 0x03 /* Configuration 0 (ro) */
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#define NERTL_RTL3_BPAGE 0x02 /* BROM Page Regiseter (8019) */
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#define NERTL_RTL3_CONFIG0 0x03 /* Configuration 0 (ro) */
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#define RTL3_CONFIG0_JP 0x08 /* jumper mode (8019) */
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#define RTL3_CONFIG0_BNC 0x04 /* BNC is active */
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#define NEPCI_RTL3_CONFIG2 0x05 /* Configuration 2 */
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#define NERTL_RTL3_CONFIG1 0x04 /* Configuration 1 (8019) */
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#define RTL3_CONFIG1_IRQEN 0x80 /* IRQ Enable */
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#define RTL3_CONFIG1_IRQS2 0x40 /* IRQ Select */
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#define RTL3_CONFIG1_IRQS1 0x20
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#define RTL3_CONFIG1_IRQS0 0x10
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/* 0 0 0 int 0 irq 2/9 */
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/* 0 0 1 int 1 irq 3 */
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/* 0 1 0 int 2 irq 4 */
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/* 0 1 1 int 3 irq 5 */
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/* 1 0 0 int 4 irq 10 */
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/* 1 0 1 int 5 irq 11 */
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/* 1 1 0 int 6 irq 12 */
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/* 1 1 1 int 7 irq 15 */
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#define RTL_CONFIG1_IOS3 0x08 /* I/O base Select */
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#define RTL_CONFIG1_IOS2 0x04
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#define RTL_CONFIG1_IOS1 0x02
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#define RTL_CONFIG1_IOS0 0x01
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/* 0 0 0 0 0x300 */
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/* 0 0 0 1 0x320 */
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/* 0 0 1 0 0x340 */
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/* 0 0 1 1 0x360 */
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/* 0 1 0 0 0x380 */
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/* 0 1 0 1 0x3a0 */
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/* 0 1 1 0 0x3c0 */
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/* 0 1 1 1 0x3e0 */
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/* 1 0 0 0 0x200 */
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/* 1 0 0 1 0x220 */
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/* 1 0 1 0 0x240 */
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/* 1 0 1 1 0x260 */
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/* 1 1 0 0 0x280 */
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/* 1 1 0 1 0x2a0 */
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/* 1 1 1 0 0x2c0 */
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/* 1 1 1 1 0x2e0 */
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#define NERTL_RTL3_CONFIG2 0x05 /* Configuration 2 */
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#define RTL3_CONFIG2_PL1 0x80 /* Network media type */
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#define RTL3_CONFIG2_PL0 0x40
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/* 0 0 TP/CX auto-detect */
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/* 0 1 10baseT */
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/* 1 0 10base5 */
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/* 1 1 10base2 */
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#define RTL3_CONFIG2_FCE 0x20 /* Flow Control Enable */
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#define RTL3_CONFIG2_PF 0x10 /* Pause Flag */
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#define RTL3_CONFIG2_BS1 0x02 /* Boot Rom Size */
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#define RTL3_CONFIG2_BS0 0x01
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#define RTL3_CONFIG2_8029FCE 0x20 /* Flow Control Enable */
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#define RTL3_CONFIG2_8029PF 0x10 /* Pause Flag */
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#define RTL3_CONFIG2_8029BS1 0x02 /* Boot Rom Size */
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#define RTL3_CONFIG2_8029BS0 0x01
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/* 0 0 No Boot Rom */
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/* 0 1 8k */
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/* 1 0 16k */
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/* 1 1 32k */
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#define RTL3_CONFIG2_8019BSELB 0x20 /* BROM disable */
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#define RTL3_CONFIG2_8019BS4 0x10 /* BROM size/base */
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#define RTL3_CONFIG2_8019BS3 0x08
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#define RTL3_CONFIG2_8019BS2 0x04
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#define RTL3_CONFIG2_8019BS1 0x02
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#define RTL3_CONFIG2_8019BS0 0x01
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#define NEPCI_RTL3_CONFIG3 0x06 /* Configuration 3 */
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#define NERTL_RTL3_CONFIG3 0x06 /* Configuration 3 */
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#define RTL3_CONFIG3_8019PNP 0x80 /* PnP Mode */
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#define RTL3_CONFIG3_FUDUP 0x40 /* Full Duplex */
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#define RTL3_CONFIG3_LEDS1 0x20 /* LED1/2 pin configuration */
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/* 0 LED1 == LED_RX, LED2 == LED_TX */
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@ -93,11 +142,16 @@
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/* 1 LED0 pin == LED_LINK */
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#define RTL3_CONFIG3_SLEEP 0x04 /* Sleep mode */
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#define RTL3_CONFIG3_PWRDN 0x02 /* Power Down */
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#define RTL3_CONFIG3_8019ACTIVEB 0x01 /* inverse of bit 0 in PnP Act Reg */
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#define NEPCI_RTL3_HLTCLK 0x09 /* Halt Clock */
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#define NERTL_RTL3_CSNSAV 0x08 /* CSN Save Register (8019) */
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#define NERTL_RTL3_HLTCLK 0x09 /* Halt Clock */
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#define RTL3_HLTCLK_RUNNING 'R' /* clock runs in power down */
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#define RTL3_HLTCLK_HALTED 'H' /* clock halted in power down */
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#define NEPCI_RTL3_ID0 0x0e /* ID register 0 */
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#define NERTL_RTL3_INTR 0x0b /* ISA bus states of INT7-0 (8019) */
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#define NEPCI_RTL3_ID1 0x0f /* ID register 1 */
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#define NERTL_RTL3_8029ID0 0x0e /* ID register 0 */
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#define NERTL_RTL3_8029ID1 0x0f /* ID register 1 */
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@ -1,4 +1,4 @@
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/* $NetBSD: if_ne_pci.c,v 1.11 1998/10/28 00:15:54 thorpej Exp $ */
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/* $NetBSD: if_ne_pci.c,v 1.12 1998/10/31 00:27:41 thorpej Exp $ */
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/*-
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* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
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@ -69,7 +69,7 @@
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#include <dev/ic/ne2000reg.h>
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#include <dev/ic/ne2000var.h>
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#include <dev/pci/if_ne_pcireg.h>
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#include <dev/ic/rtl80x9reg.h>
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struct ne_pci_softc {
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struct ne2000_softc sc_ne2000; /* real "ne2000" softc */
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@ -318,12 +318,12 @@ ne_pci_rtl8029_mediastatus(sc, ifmr)
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/* Set NIC to page 3 registers. */
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NIC_PUT(sc->sc_regt, sc->sc_regh, ED_P0_CR, cr_proto | ED_CR_PAGE_3);
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if (NIC_GET(sc->sc_regt, sc->sc_regh, NEPCI_RTL3_CONFIG0) &
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if (NIC_GET(sc->sc_regt, sc->sc_regh, NERTL_RTL3_CONFIG0) &
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RTL3_CONFIG0_BNC)
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ifmr->ifm_active = IFM_ETHER|IFM_10_2;
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else {
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ifmr->ifm_active = IFM_ETHER|IFM_10_T;
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if (NIC_GET(sc->sc_regt, sc->sc_regh, NEPCI_RTL3_CONFIG3) &
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if (NIC_GET(sc->sc_regt, sc->sc_regh, NERTL_RTL3_CONFIG3) &
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RTL3_CONFIG3_FUDUP)
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ifmr->ifm_active |= IFM_FDX;
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}
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@ -346,7 +346,7 @@ ne_pci_rtl8029_init_card(sc)
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NIC_PUT(sc->sc_regt, sc->sc_regh, ED_P0_CR, cr_proto | ED_CR_PAGE_3);
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/* First, set basic media type. */
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reg = NIC_GET(sc->sc_regt, sc->sc_regh, NEPCI_RTL3_CONFIG2);
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reg = NIC_GET(sc->sc_regt, sc->sc_regh, NERTL_RTL3_CONFIG2);
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reg &= ~(RTL3_CONFIG2_PL1|RTL3_CONFIG2_PL0);
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switch (IFM_SUBTYPE(ifm->ifm_cur->ifm_media)) {
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case IFM_AUTO:
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@ -361,15 +361,15 @@ ne_pci_rtl8029_init_card(sc)
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reg |= RTL3_CONFIG2_PL1|RTL3_CONFIG2_PL0;
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break;
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}
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NIC_PUT(sc->sc_regt, sc->sc_regh, NEPCI_RTL3_CONFIG2, reg);
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NIC_PUT(sc->sc_regt, sc->sc_regh, NERTL_RTL3_CONFIG2, reg);
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/* Now, set duplex mode. */
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reg = NIC_GET(sc->sc_regt, sc->sc_regh, NEPCI_RTL3_CONFIG3);
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reg = NIC_GET(sc->sc_regt, sc->sc_regh, NERTL_RTL3_CONFIG3);
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if (ifm->ifm_cur->ifm_media & IFM_FDX)
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reg |= RTL3_CONFIG3_FUDUP;
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else
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reg &= ~RTL3_CONFIG3_FUDUP;
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NIC_PUT(sc->sc_regt, sc->sc_regh, NEPCI_RTL3_CONFIG3, reg);
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NIC_PUT(sc->sc_regt, sc->sc_regh, NERTL_RTL3_CONFIG3, reg);
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/* Set NIC to page 0 registers. */
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NIC_PUT(sc->sc_regt, sc->sc_regh, ED_P0_CR, cr_proto | ED_CR_PAGE_0);
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