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Remove hacks for now removed spllowersoftclock(9).

This commit is contained in:
tsutsui 2007-02-16 13:27:00 +00:00
parent 937ff586b1
commit 990a39ff81
4 changed files with 9 additions and 90 deletions
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21
sys/arch/arc/arc/interrupt.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: interrupt.c,v 1.1 2006/06/25 16:11:41 tsutsui Exp $ */
/* $NetBSD: interrupt.c,v 1.2 2007/02/16 13:27:00 tsutsui Exp $ */
/* $OpenBSD: trap.c,v 1.22 1999/05/24 23:08:59 jason Exp $ */
/*
@ -78,7 +78,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.1 2006/06/25 16:11:41 tsutsui Exp $");
__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.2 2007/02/16 13:27:00 tsutsui Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -171,23 +171,6 @@ cpu_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
*/
inttab = &cpu_int_tab[ARC_INTPRI_TIMER_INT];
if (inttab->int_mask & ipending) {
if ((ipending & MIPS_INT_MASK & ~inttab->int_mask) == 0) {
/*
* If all interrupts were enabled and there is no
* pending interrupts, set MIPS_SR_INT_IE so that
* spllowerclock() in hardclock() works properly.
*/
#if 0 /* MIPS_SR_INT_IE is enabled above */
_splset(MIPS_SR_INT_IE);
#endif
} else {
/*
* If there are any pending interrputs, clear
* MIPS_SR_INT_IE in cf.sr so that spllowerclock()
* in hardclock() will not happen.
*/
cf.sr &= ~MIPS_SR_INT_IE;
}
cause &= (*inttab->int_hand)(ipending, &cf);
}
_splset((status & ~cause & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);

27
sys/arch/cobalt/cobalt/machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.76 2006/12/21 15:55:22 yamt Exp $ */
/* $NetBSD: machdep.c,v 1.77 2007/02/16 13:27:00 tsutsui Exp $ */
/*
* Copyright (c) 2006 Izumi Tsutsui.
@ -53,7 +53,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.76 2006/12/21 15:55:22 yamt Exp $");
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.77 2007/02/16 13:27:00 tsutsui Exp $");
#include "opt_ddb.h"
#include "opt_kgdb.h"
@ -669,32 +669,9 @@ cpu_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
uvmexp.intrs++;
if (ipending & MIPS_INT_MASK_5) {
/* call the common MIPS3 clock interrupt handler */
cf.pc = pc;
cf.sr = status;
if ((status & MIPS_INT_MASK) == MIPS_INT_MASK) {
if ((ipending & MIPS_INT_MASK &
~MIPS_INT_MASK_5) == 0) {
/*
* If all interrupts were enabled and
* there is no pending interrupts,
* set MIPS_SR_INT_IE so that
* spllowersoftclock(9) in hardclock(9)
* works properly.
*/
_splset(MIPS_SR_INT_IE);
} else {
/*
* If there are any pending interrputs,
* clear MIPS_SR_INT_IE in cf.sr so that
* spllowersoftclock(9) in hardclock(9) will
* not happen.
*/
cf.sr &= ~MIPS_SR_INT_IE;
}
}
mips3_clockintr(&cf);
cause &= ~MIPS_INT_MASK_5;

25
sys/arch/ews4800mips/ews4800mips/tr2_intr.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: tr2_intr.c,v 1.3 2006/09/08 17:04:17 tsutsui Exp $ */
/* $NetBSD: tr2_intr.c,v 1.4 2007/02/16 13:27:01 tsutsui Exp $ */
/*-
* Copyright (c) 2004, 2005 The NetBSD Foundation, Inc.
@ -37,7 +37,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: tr2_intr.c,v 1.3 2006/09/08 17:04:17 tsutsui Exp $");
__KERNEL_RCSID(0, "$NetBSD: tr2_intr.c,v 1.4 2007/02/16 13:27:01 tsutsui Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -179,27 +179,6 @@ tr2_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
*PICNIC_INT5_STATUS_REG = 0;
r = *PICNIC_INT5_STATUS_REG;
if ((status & MIPS_INT_MASK) == MIPS_INT_MASK) {
if ((ipending & MIPS_INT_MASK & ~MIPS_INT_MASK_5) ==
0) {
/*
* If all interrupts were enabled and
* there isno pending interrupts,
* set MIPS_SR_INT_IE so that
* spllowerclock() in hardclock()
* works properly.
*/
_splset(MIPS_SR_INT_IE);
} else {
/*
* If there are any pending interrputs,
* clear MIPS_SR_INT_IE in cf.sr so that
* spllowerclock() in hardclock() will
* not happen.
*/
cf.sr &= ~MIPS_SR_INT_IE;
}
}
hardclock(&cf);
timer_tr2_ev.ev_count++;
cause &= ~MIPS_INT_MASK_5;

26
sys/arch/ews4800mips/ews4800mips/tr2a_intr.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: tr2a_intr.c,v 1.4 2006/09/08 17:04:17 tsutsui Exp $ */
/* $NetBSD: tr2a_intr.c,v 1.5 2007/02/16 13:27:01 tsutsui Exp $ */
/*-
* Copyright (c) 2004, 2005 The NetBSD Foundation, Inc.
@ -37,7 +37,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: tr2a_intr.c,v 1.4 2006/09/08 17:04:17 tsutsui Exp $");
__KERNEL_RCSID(0, "$NetBSD: tr2a_intr.c,v 1.5 2007/02/16 13:27:01 tsutsui Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -218,27 +218,7 @@ tr2a_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
tr2a_wbflush();
*INTC_CLEAR_REG = 0x7c;
*INTC_STATUS_REG;
if ((status & MIPS_INT_MASK) == MIPS_INT_MASK) {
if ((ipending & MIPS_INT_MASK & ~MIPS_INT_MASK_5) ==
0) {
/*
* If all interrupts were enabled and
* there is no pending interrupts,
* set MIPS_SR_INT_IE so that
* spllowerclock() in hardclock()
* works properly.
*/
_splset(MIPS_SR_INT_IE);
} else {
/*
* If there are any pending interrputs,
* clear MIPS_SR_INT_IE in cf.sr so that
* spllowerclock() in hardclock() will
* not happen.
*/
cf.sr &= ~MIPS_SR_INT_IE;
}
}
hardclock(&cf);
timer_tr2a_ev.ev_count++;
cause &= ~MIPS_INT_MASK_5;