Add support for the Silicon Image 3114 SATALink 4-port SATA controller.
This commit is contained in:
thorpej
parent
fc04f37975
commit
98d14a3f5f
@ -1,4 +1,4 @@
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/* $NetBSD: pciide_sii3112_reg.h,v 1.1 2003/03/20 04:22:50 thorpej Exp $ */
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/* $NetBSD: pciide_sii3112_reg.h,v 1.2 2003/12/20 03:51:27 thorpej Exp $ */
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/*
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* Copyright (c) 2003 Wasabi Systems, Inc.
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@ -73,9 +73,16 @@
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#define SCS_CMD_FF0_RESET (1U << 5) /* IDE0 FIFO reset */
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#define SCS_CMD_IDE1_RESET (1U << 6) /* IDE1 module reset */
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#define SCS_CMD_IDE0_RESET (1U << 7) /* IDE0 module reset */
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#define SCS_CMD_BA5_EN (1U << 16) /* BA5 is enabled */
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#define SCS_CMD_FF3_RESET (1U << 8) /* IDE3 FIFO reset (3114) */
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#define SCS_CMD_FF2_RESET (1U << 9) /* IDE2 FIFO reset (3114) */
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#define SCS_CMD_IDE3_RESET (1U << 10) /* IDE3 module reset (3114) */
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#define SCS_CMD_IDE2_RESET (1U << 11) /* IDE2 module reset (3114) */
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#define SCS_CMD_BA5_EN (1U << 16) /* BA5 is enabled (3112) */
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#define SCS_CMD_M66EN (1U << 16) /* 1=66MHz, 0=33MHz (3114) */
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#define SCS_CMD_IDE0_INT_BLOCK (1U << 22) /* IDE0 interrupt block */
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#define SCS_CMD_IDE1_INT_BLOCK (1U << 23) /* IDE1 interrupt block */
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#define SCS_CMD_IDE2_INT_BLOCK (1U << 24) /* IDE2 interrupt block */
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#define SCS_CMD_IDE3_INT_BLOCK (1U << 25) /* IDE3 interrupt block */
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#define SII3112_SSDR 0x8c /* System SW Data Register */
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@ -1,4 +1,4 @@
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/* $NetBSD: satalink.c,v 1.4 2003/12/19 03:33:52 thorpej Exp $ */
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/* $NetBSD: satalink.c,v 1.5 2003/12/20 03:51:27 thorpej Exp $ */
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/*-
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* Copyright (c) 2003 The NetBSD Foundation, Inc.
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@ -85,8 +85,13 @@ static const struct {
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bus_addr_t ba5_SControl;
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bus_addr_t ba5_SStatus;
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bus_addr_t ba5_SError;
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bus_addr_t ba5_SActive; /* 3114 */
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bus_addr_t ba5_SMisc;
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bus_addr_t ba5_PHY_CONFIG;
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bus_addr_t ba5_SIEN;
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bus_addr_t ba5_SFISCfg;
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} satalink_ba5_regmap[] = {
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{
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{ /* Channel 0 */
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.ba5_IDEDMA_CMD = 0x000,
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.ba5_IDEDMA_CTL = 0x002,
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.ba5_IDEDMA_TBL = 0x004,
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@ -120,8 +125,13 @@ static const struct {
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.ba5_SControl = 0x100,
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.ba5_SStatus = 0x104,
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.ba5_SError = 0x108,
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.ba5_SActive = 0x10c,
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.ba5_SMisc = 0x140,
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.ba5_PHY_CONFIG = 0x144,
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.ba5_SIEN = 0x148,
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.ba5_SFISCfg = 0x14c,
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},
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{
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{ /* Channel 1 */
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.ba5_IDEDMA_CMD = 0x008,
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.ba5_IDEDMA_CTL = 0x00a,
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.ba5_IDEDMA_TBL = 0x00c,
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@ -155,9 +165,99 @@ static const struct {
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.ba5_SControl = 0x180,
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.ba5_SStatus = 0x184,
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.ba5_SError = 0x188,
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}
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.ba5_SActive = 0x18c,
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.ba5_SMisc = 0x1c0,
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.ba5_PHY_CONFIG = 0x1c4,
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.ba5_SIEN = 0x1c8,
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.ba5_SFISCfg = 0x1cc,
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},
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{ /* Channel 2 (3114) */
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.ba5_IDEDMA_CMD = 0x200,
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.ba5_IDEDMA_CTL = 0x202,
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.ba5_IDEDMA_TBL = 0x204,
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.ba5_IDEDMA_CMD2 = 0x210,
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.ba5_IDEDMA_CTL2 = 0x212,
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.ba5_IDE_TF0 = 0x280, /* wd_data */
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.ba5_IDE_TF1 = 0x281, /* wd_error */
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.ba5_IDE_TF2 = 0x282, /* wd_seccnt */
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.ba5_IDE_TF3 = 0x283, /* wd_sector */
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.ba5_IDE_TF4 = 0x284, /* wd_cyl_lo */
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.ba5_IDE_TF5 = 0x285, /* wd_cyl_hi */
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.ba5_IDE_TF6 = 0x286, /* wd_sdh */
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.ba5_IDE_TF7 = 0x287, /* wd_command */
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.ba5_IDE_TF8 = 0x28a, /* wd_altsts */
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.ba5_IDE_RAD = 0x28c,
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.ba5_IDE_TF9 = 0x291, /* Features 2 */
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.ba5_IDE_TF10 = 0x292, /* Sector Count 2 */
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.ba5_IDE_TF11 = 0x293, /* Start Sector 2 */
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.ba5_IDE_TF12 = 0x294, /* Cylinder Low 2 */
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.ba5_IDE_TF13 = 0x295, /* Cylinder High 2 */
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.ba5_IDE_TF14 = 0x296, /* Device/Head 2 */
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.ba5_IDE_TF15 = 0x297, /* Cmd Sts 2 */
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.ba5_IDE_TF16 = 0x298, /* Sector Count 2 ext */
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.ba5_IDE_TF17 = 0x299, /* Start Sector 2 ext */
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.ba5_IDE_TF18 = 0x29a, /* Cyl Low 2 ext */
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.ba5_IDE_TF19 = 0x29b, /* Cyl High 2 ext */
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.ba5_IDE_RABC = 0x29c,
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.ba5_IDE_CMD_STS = 0x2a0,
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.ba5_IDE_CFG_STS = 0x2a1,
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.ba5_IDE_DTM = 0x2b4,
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.ba5_SControl = 0x300,
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.ba5_SStatus = 0x304,
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.ba5_SError = 0x308,
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.ba5_SActive = 0x30c,
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.ba5_SMisc = 0x340,
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.ba5_PHY_CONFIG = 0x344,
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.ba5_SIEN = 0x348,
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.ba5_SFISCfg = 0x34c,
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},
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{ /* Channel 3 (3114) */
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.ba5_IDEDMA_CMD = 0x208,
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.ba5_IDEDMA_CTL = 0x20a,
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.ba5_IDEDMA_TBL = 0x20c,
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.ba5_IDEDMA_CMD2 = 0x218,
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.ba5_IDEDMA_CTL2 = 0x21a,
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.ba5_IDE_TF0 = 0x2c0, /* wd_data */
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.ba5_IDE_TF1 = 0x2c1, /* wd_error */
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.ba5_IDE_TF2 = 0x2c2, /* wd_seccnt */
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.ba5_IDE_TF3 = 0x2c3, /* wd_sector */
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.ba5_IDE_TF4 = 0x2c4, /* wd_cyl_lo */
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.ba5_IDE_TF5 = 0x2c5, /* wd_cyl_hi */
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.ba5_IDE_TF6 = 0x2c6, /* wd_sdh */
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.ba5_IDE_TF7 = 0x2c7, /* wd_command */
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.ba5_IDE_TF8 = 0x2ca, /* wd_altsts */
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.ba5_IDE_RAD = 0x2cc,
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.ba5_IDE_TF9 = 0x2d1, /* Features 2 */
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.ba5_IDE_TF10 = 0x2d2, /* Sector Count 2 */
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.ba5_IDE_TF11 = 0x2d3, /* Start Sector 2 */
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.ba5_IDE_TF12 = 0x2d4, /* Cylinder Low 2 */
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.ba5_IDE_TF13 = 0x2d5, /* Cylinder High 2 */
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.ba5_IDE_TF14 = 0x2d6, /* Device/Head 2 */
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.ba5_IDE_TF15 = 0x2d7, /* Cmd Sts 2 */
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.ba5_IDE_TF16 = 0x2d8, /* Sector Count 2 ext */
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.ba5_IDE_TF17 = 0x2d9, /* Start Sector 2 ext */
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.ba5_IDE_TF18 = 0x2da, /* Cyl Low 2 ext */
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.ba5_IDE_TF19 = 0x2db, /* Cyl High 2 ext */
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.ba5_IDE_RABC = 0x2dc,
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.ba5_IDE_CMD_STS = 0x2e0,
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.ba5_IDE_CFG_STS = 0x2e1,
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.ba5_IDE_DTM = 0x2f4,
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.ba5_SControl = 0x380,
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.ba5_SStatus = 0x384,
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.ba5_SError = 0x388,
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.ba5_SActive = 0x38c,
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.ba5_SMisc = 0x3c0,
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.ba5_PHY_CONFIG = 0x3c4,
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.ba5_SIEN = 0x3c8,
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.ba5_SFISCfg = 0x3cc,
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},
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};
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#define ba5_SIS 0x214 /* summary interrupt status */
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/* Interrupt steering bit in BA5[0x200]. */
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#define IDEDMA_CMD_INT_STEER (1U << 1)
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static int satalink_match(struct device *, struct cfdata *, void *);
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static void satalink_attach(struct device *, struct device *, void *);
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@ -165,6 +265,7 @@ CFATTACH_DECL(satalink, sizeof(struct pciide_softc),
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satalink_match, satalink_attach, NULL, NULL);
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static void sii3112_chip_map(struct pciide_softc*, struct pci_attach_args*);
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static void sii3114_chip_map(struct pciide_softc*, struct pci_attach_args*);
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static int sii3112_drv_probe(struct channel_softc*);
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static void sii3112_setup_channel(struct channel_softc*);
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@ -174,6 +275,11 @@ static const struct pciide_product_desc pciide_satalink_products[] = {
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"Silicon Image SATALink 3112",
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sii3112_chip_map,
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},
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{ PCI_PRODUCT_CMDTECH_3114,
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0,
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"Silicon Image SATALink 3114",
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sii3114_chip_map,
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},
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{ 0,
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0,
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NULL,
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@ -204,6 +310,20 @@ satalink_attach(struct device *parent, struct device *self, void *aux)
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}
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static __inline uint32_t
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ba5_read_4_ind(struct pciide_softc *sc, bus_addr_t reg)
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{
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uint32_t rv;
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int s;
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s = splbio();
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pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg);
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rv = pci_conf_read(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA);
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splx(s);
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return (rv);
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}
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static __inline uint32_t
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ba5_read_4(struct pciide_softc *sc, bus_addr_t reg)
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{
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@ -211,25 +331,31 @@ ba5_read_4(struct pciide_softc *sc, bus_addr_t reg)
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if (__predict_true(sc->sc_ba5_en != 0))
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return (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg));
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pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg);
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return (pci_conf_read(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA));
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return (ba5_read_4_ind(sc, reg));
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}
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#define BA5_READ_4(sc, chan, reg) \
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ba5_read_4((sc), satalink_ba5_regmap[(chan)].reg)
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static __inline void
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ba5_write_4_ind(struct pciide_softc *sc, bus_addr_t reg, uint32_t val)
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{
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int s;
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s = splbio();
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pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg);
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pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA, val);
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splx(s);
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}
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static __inline void
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ba5_write_4(struct pciide_softc *sc, bus_addr_t reg, uint32_t val)
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{
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if (__predict_true(sc->sc_ba5_en != 0))
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bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg, val);
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else {
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pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR,
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reg);
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pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA,
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val);
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}
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else
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ba5_write_4_ind(sc, reg, val);
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}
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#define BA5_WRITE_4(sc, chan, reg, val) \
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@ -246,9 +372,21 @@ sii3112_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
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if (pciide_chipen(sc, pa) == 0)
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return;
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#define SII3112_RESET_BITS \
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(SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \
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SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \
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SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET)
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/*
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* Reset everything and then unblock all of the interrupts.
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*/
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scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD);
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pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD,
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scs_cmd | SII3112_RESET_BITS);
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delay(50 * 1000);
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pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD,
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scs_cmd & SCS_CMD_BA5_EN);
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delay(50 * 1000);
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if (scs_cmd & SCS_CMD_BA5_EN) {
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aprint_verbose("%s: SATALink BA5 register space enabled\n",
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@ -266,7 +404,6 @@ sii3112_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
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aprint_verbose("%s: SATALink BA5 register space disabled\n",
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sc->sc_wdcdev.sc_dev.dv_xname);
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/* Enable indirect BA5 addressing. */
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cfgctl = pci_conf_read(pa->pa_pc, pa->pa_tag,
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SII3112_PCI_CFGCTL);
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pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_PCI_CFGCTL,
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@ -329,6 +466,257 @@ sii3112_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
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}
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}
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static void
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sii3114_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa)
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{
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struct pciide_channel *pc;
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int chan, reg;
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bus_size_t size;
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sc->sc_wdcdev.dma_arg = sc;
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sc->sc_wdcdev.dma_init = pciide_dma_init;
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sc->sc_wdcdev.dma_start = pciide_dma_start;
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sc->sc_wdcdev.dma_finish = pciide_dma_finish;
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if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags &
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PCIIDE_OPTIONS_NODMA) {
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aprint_normal(
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", but unused (forced off by config file)");
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sc->sc_dma_ok = 0;
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return;
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}
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/*
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* Slice off a subregion of BA5 for each of the channel's DMA
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* registers.
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*/
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sc->sc_dma_iot = sc->sc_ba5_st;
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for (chan = 0; chan < 4; chan++) {
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pc = &sc->pciide_channels[chan];
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for (reg = 0; reg < IDEDMA_NREGS; reg++) {
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size = 4;
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if (size > (IDEDMA_SCH_OFFSET - reg))
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size = IDEDMA_SCH_OFFSET - reg;
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if (bus_space_subregion(sc->sc_ba5_st,
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sc->sc_ba5_sh,
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satalink_ba5_regmap[chan].ba5_IDEDMA_CMD + reg,
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size, &pc->dma_iohs[reg]) != 0) {
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sc->sc_dma_ok = 0;
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aprint_normal(", but can't subregion offset "
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"%lu size %lu",
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(u_long) satalink_ba5_regmap[
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chan].ba5_IDEDMA_CMD + reg,
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(u_long) size);
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return;
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}
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}
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}
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/* DMA registers all set up! */
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sc->sc_dmat = pa->pa_dmat;
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sc->sc_dma_ok = 1;
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}
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static int
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sii3114_chansetup(struct pciide_softc *sc, int channel)
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{
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static const char *channel_names[] = {
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"port 0",
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"port 1",
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"port 2",
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"port 3",
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};
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struct pciide_channel *cp = &sc->pciide_channels[channel];
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sc->wdc_chanarray[channel] = &cp->wdc_channel;
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/*
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* We must always keep the Interrupt Steering bit set in channel 2's
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* IDEDMA_CMD register.
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*/
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if (channel == 2)
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cp->idedma_cmd = IDEDMA_CMD_INT_STEER;
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cp->name = channel_names[channel];
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cp->wdc_channel.channel = channel;
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cp->wdc_channel.wdc = &sc->sc_wdcdev;
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cp->wdc_channel.ch_queue =
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malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT);
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if (cp->wdc_channel.ch_queue == NULL) {
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aprint_error("%s %s channel: "
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"can't allocate memory for command queue",
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sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
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return (0);
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}
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return (1);
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}
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static void
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sii3114_mapchan(struct pciide_channel *cp)
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{
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struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
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struct channel_softc *wdc_cp = &cp->wdc_channel;
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int i;
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cp->compat = 0;
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cp->ih = sc->sc_pci_ih;
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wdc_cp->cmd_iot = sc->sc_ba5_st;
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if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
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satalink_ba5_regmap[wdc_cp->channel].ba5_IDE_TF0,
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9, &wdc_cp->cmd_baseioh) != 0) {
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aprint_error("%s: couldn't subregion %s cmd base\n",
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||||
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
|
||||
goto bad;
|
||||
}
|
||||
|
||||
wdc_cp->ctl_iot = sc->sc_ba5_st;
|
||||
if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
|
||||
satalink_ba5_regmap[wdc_cp->channel].ba5_IDE_TF9,
|
||||
1, &cp->ctl_baseioh) != 0) {
|
||||
aprint_error("%s: couldn't subregion %s ctl base\n",
|
||||
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
|
||||
goto bad;
|
||||
}
|
||||
wdc_cp->ctl_ioh = cp->ctl_baseioh;
|
||||
|
||||
for (i = 0; i < WDC_NREG; i++) {
|
||||
if (bus_space_subregion(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh,
|
||||
i, i == 0 ? 4 : 1,
|
||||
&wdc_cp->cmd_iohs[i]) != 0) {
|
||||
aprint_error("%s: couldn't subregion %s channel "
|
||||
"cmd regs\n",
|
||||
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
|
||||
goto bad;
|
||||
}
|
||||
}
|
||||
wdc_cp->data32iot = wdc_cp->cmd_iot;
|
||||
wdc_cp->data32ioh = wdc_cp->cmd_iohs[0];
|
||||
wdcattach(wdc_cp);
|
||||
return;
|
||||
|
||||
bad:
|
||||
cp->wdc_channel.ch_flags |= WDCF_DISABLED;
|
||||
}
|
||||
|
||||
static void
|
||||
sii3114_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
|
||||
{
|
||||
struct pciide_channel *cp;
|
||||
pcireg_t scs_cmd;
|
||||
pci_intr_handle_t intrhandle;
|
||||
const char *intrstr;
|
||||
int channel;
|
||||
|
||||
if (pciide_chipen(sc, pa) == 0)
|
||||
return;
|
||||
|
||||
#define SII3114_RESET_BITS \
|
||||
(SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \
|
||||
SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \
|
||||
SCS_CMD_FF3_RESET | SCS_CMD_FF2_RESET | \
|
||||
SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET | \
|
||||
SCS_CMD_IDE3_RESET | SCS_CMD_IDE2_RESET)
|
||||
|
||||
/*
|
||||
* Reset everything and then unblock all of the interrupts.
|
||||
*/
|
||||
scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD);
|
||||
pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD,
|
||||
scs_cmd | SII3114_RESET_BITS);
|
||||
delay(50 * 1000);
|
||||
pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD,
|
||||
scs_cmd & SCS_CMD_M66EN);
|
||||
delay(50 * 1000);
|
||||
|
||||
/*
|
||||
* On the 3114, the BA5 register space is always enabled. In
|
||||
* order to use the 3114 in any sane way, we must use this BA5
|
||||
* register space, and so we consider it an error if we cannot
|
||||
* map it.
|
||||
*
|
||||
* As a consequence of using BA5, our register mapping is different
|
||||
* from a normal PCI IDE controller's, and so we are unable to use
|
||||
* most of the common PCI IDE register mapping functions.
|
||||
*/
|
||||
if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
|
||||
PCI_MAPREG_TYPE_MEM|
|
||||
PCI_MAPREG_MEM_TYPE_32BIT, 0,
|
||||
&sc->sc_ba5_st, &sc->sc_ba5_sh,
|
||||
NULL, NULL) != 0) {
|
||||
aprint_error("%s: unable to map SATALink BA5 "
|
||||
"register space\n", sc->sc_wdcdev.sc_dev.dv_xname);
|
||||
return;
|
||||
}
|
||||
sc->sc_ba5_en = 1;
|
||||
|
||||
aprint_verbose("%s: %dMHz PCI bus\n", sc->sc_wdcdev.sc_dev.dv_xname,
|
||||
(scs_cmd & SCS_CMD_M66EN) ? 66 : 33);
|
||||
|
||||
/*
|
||||
* Set the Interrupt Steering bit in the IDEDMA_CMD register of
|
||||
* channel 2. This is required at all times for proper operation
|
||||
* when using the BA5 register space (otherwise interrupts from
|
||||
* all 4 channels won't work).
|
||||
*/
|
||||
BA5_WRITE_4(sc, 2, ba5_IDEDMA_CMD, IDEDMA_CMD_INT_STEER);
|
||||
|
||||
aprint_normal("%s: bus-master DMA support present",
|
||||
sc->sc_wdcdev.sc_dev.dv_xname);
|
||||
sii3114_mapreg_dma(sc, pa);
|
||||
aprint_normal("\n");
|
||||
|
||||
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
|
||||
WDC_CAPABILITY_MODE;
|
||||
sc->sc_wdcdev.PIO_cap = 4;
|
||||
if (sc->sc_dma_ok) {
|
||||
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
|
||||
sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
|
||||
sc->sc_wdcdev.irqack = pciide_irqack;
|
||||
sc->sc_wdcdev.DMA_cap = 2;
|
||||
sc->sc_wdcdev.UDMA_cap = 6;
|
||||
}
|
||||
sc->sc_wdcdev.set_modes = sii3112_setup_channel;
|
||||
|
||||
/* We can use SControl and SStatus to probe for drives. */
|
||||
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DRVPROBE;
|
||||
sc->sc_wdcdev.drv_probe = sii3112_drv_probe;
|
||||
|
||||
sc->sc_wdcdev.channels = sc->wdc_chanarray;
|
||||
sc->sc_wdcdev.nchannels = 4;
|
||||
|
||||
/* Map and establish the interrupt handler. */
|
||||
if (pci_intr_map(pa, &intrhandle) != 0) {
|
||||
aprint_error("%s: couldn't map native-PCI interrupt\n",
|
||||
sc->sc_wdcdev.sc_dev.dv_xname);
|
||||
return;
|
||||
}
|
||||
intrstr = pci_intr_string(pa->pa_pc, intrhandle);
|
||||
sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO,
|
||||
/* XXX */
|
||||
pciide_pci_intr, sc);
|
||||
if (sc->sc_pci_ih != NULL) {
|
||||
aprint_normal("%s: using %s for native-PCI interrupt\n",
|
||||
sc->sc_wdcdev.sc_dev.dv_xname,
|
||||
intrstr ? intrstr : "unknown interrupt");
|
||||
} else {
|
||||
aprint_error("%s: couldn't establish native-PCI interrupt",
|
||||
sc->sc_wdcdev.sc_dev.dv_xname);
|
||||
if (intrstr != NULL)
|
||||
aprint_normal(" at %s", intrstr);
|
||||
aprint_normal("\n");
|
||||
return;
|
||||
}
|
||||
|
||||
for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
|
||||
cp = &sc->pciide_channels[channel];
|
||||
if (sii3114_chansetup(sc, channel) == 0)
|
||||
continue;
|
||||
sii3114_mapchan(cp);
|
||||
}
|
||||
}
|
||||
|
||||
static const char *sata_speed[] = {
|
||||
"no negotiated speed",
|
||||
"1.5Gb/s",
|
||||
@ -360,6 +748,8 @@ sii3112_drv_probe(struct channel_softc *chp)
|
||||
/*
|
||||
* The 3112 is a 2-port part, and only has one drive per channel
|
||||
* (each port emulates a master drive).
|
||||
*
|
||||
* The 3114 is similar, but has 4 channels.
|
||||
*/
|
||||
|
||||
/*
|
||||
@ -375,12 +765,17 @@ sii3112_drv_probe(struct channel_softc *chp)
|
||||
scontrol |= SControl_IPM_NONE;
|
||||
|
||||
BA5_WRITE_4(sc, chp->channel, ba5_SControl, scontrol);
|
||||
delay(500);
|
||||
delay(50 * 1000);
|
||||
scontrol &= ~SControl_DET_INIT;
|
||||
BA5_WRITE_4(sc, chp->channel, ba5_SControl, scontrol);
|
||||
delay(500);
|
||||
delay(50 * 1000);
|
||||
|
||||
sstatus = BA5_READ_4(sc, chp->channel, ba5_SStatus);
|
||||
#if 0
|
||||
aprint_normal("%s: port %d: SStatus=0x%08x, SControl=0x%08x\n",
|
||||
sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus,
|
||||
BA5_READ_4(sc, chp->channel, ba5_SControl));
|
||||
#endif
|
||||
switch (sstatus & SStatus_DET_mask) {
|
||||
case SStatus_DET_NODEV:
|
||||
/* No device; be silent. */
|
||||
@ -488,6 +883,5 @@ sii3112_setup_channel(struct channel_softc *chp)
|
||||
bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
|
||||
idedma_ctl);
|
||||
}
|
||||
pci_conf_write(sc->sc_pc, sc->sc_tag,
|
||||
chp->channel == 0 ? SII3112_DTM_IDE0 : SII3112_DTM_IDE1, dtm);
|
||||
BA5_WRITE_4(sc, chp->channel, ba5_IDE_DTM, dtm);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user