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This commit is contained in:
msaitoh 2015-12-01 09:37:17 +00:00
parent 3ea351c27a
commit 98758a1b29
2 changed files with 3358 additions and 3197 deletions
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56
sys/dev/pci/pcidevs.h
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@ -1,10 +1,10 @@
/* $NetBSD: pcidevs.h,v 1.1236 2015/12/01 08:40:34 msaitoh Exp $ */
/* $NetBSD: pcidevs.h,v 1.1237 2015/12/01 09:37:17 msaitoh Exp $ */
/*
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
* NetBSD: pcidevs,v 1.1243 2015/12/01 08:40:06 msaitoh Exp
* NetBSD: pcidevs,v 1.1244 2015/12/01 09:36:52 msaitoh Exp
*/
/*
@ -4094,7 +4094,7 @@
#define PCI_PRODUCT_INTEL_H97_LPC 0x8cc6 /* H97 LPC */
#define PCI_PRODUCT_INTEL_C610_SATA 0x8d00 /* C61x/X99 SATA Controller */
#define PCI_PRODUCT_INTEL_C610_SATA_AHCI 0x8d02 /* C61x/X99 SATA Controller (AHCI) */
#define PCI_PRODUCT_INTEL_C610_SATA_RAID 0x2822 /* C61x/X99 SATA Controller (RAID) */
#define PCI_PRODUCT_INTEL_C610_SATA_RAID 0x2822 /* C61x/X99/Z170 SATA Controller (RAID) */
#define PCI_PRODUCT_INTEL_C610_SATA_RAID_2 0x8d06 /* C61x/X99 SATA Controller (RAID) */
#define PCI_PRODUCT_INTEL_C610_SATA_RAID_3 0x2826 /* C61x/X99 SATA Controller (RAID) */
#define PCI_PRODUCT_INTEL_C610_SATA_2 0x8d08 /* C61x/X99 SATA Controller */
@ -4208,6 +4208,56 @@
#define PCI_PRODUCT_INTEL_PINEVIEW_IGD_1 0xa002 /* Pineview Integrated Graphics Device */
#define PCI_PRODUCT_INTEL_PINEVIEW_M_HB 0xa010 /* Pineview Host Bridge */
#define PCI_PRODUCT_INTEL_PINEVIEW_M_IGD 0xa011 /* Pineview Integrated Graphics Device */
#define PCI_PRODUCT_INTEL_Z170_AHCI 0xa102 /* Z170 AHCI */
#define PCI_PRODUCT_INTEL_Z170_3RD_AHCI 0xa106 /* Z170 3rd Party RAID */
#define PCI_PRODUCT_INTEL_100SERIES_PCIE_1 0xa110 /* 100 Series PCIE */
#define PCI_PRODUCT_INTEL_100SERIES_PCIE_2 0xa111 /* 100 Series PCIE */
#define PCI_PRODUCT_INTEL_100SERIES_PCIE_3 0xa112 /* 100 Series PCIE */
#define PCI_PRODUCT_INTEL_100SERIES_PCIE_4 0xa113 /* 100 Series PCIE */
#define PCI_PRODUCT_INTEL_100SERIES_PCIE_5 0xa114 /* 100 Series PCIE */
#define PCI_PRODUCT_INTEL_100SERIES_PCIE_6 0xa115 /* 100 Series PCIE */
#define PCI_PRODUCT_INTEL_100SERIES_PCIE_7 0xa116 /* 100 Series PCIE */
#define PCI_PRODUCT_INTEL_100SERIES_PCIE_8 0xa117 /* 100 Series PCIE */
#define PCI_PRODUCT_INTEL_100SERIES_PCIE_9 0xa118 /* 100 Series PCIE */
#define PCI_PRODUCT_INTEL_100SERIES_PCIE_10 0xa119 /* 100 Series PCIE */
#define PCI_PRODUCT_INTEL_100SERIES_PCIE_11 0xa11a /* 100 Series PCIE */
#define PCI_PRODUCT_INTEL_100SERIES_PCIE_12 0xa11b /* 100 Series PCIE */
#define PCI_PRODUCT_INTEL_100SERIES_PCIE_13 0xa11c /* 100 Series PCIE */
#define PCI_PRODUCT_INTEL_100SERIES_PCIE_14 0xa11d /* 100 Series PCIE */
#define PCI_PRODUCT_INTEL_100SERIES_PCIE_15 0xa11e /* 100 Series PCIE */
#define PCI_PRODUCT_INTEL_100SERIES_PCIE_16 0xa11f /* 100 Series PCIE */
#define PCI_PRODUCT_INTEL_100SERIES_P2SB 0xa120 /* 100 Series P2SB */
#define PCI_PRODUCT_INTEL_100SERIES_PMC 0xa121 /* 100 Series PMC */
#define PCI_PRODUCT_INTEL_100SERIES_SMB 0xa123 /* 100 Series SMBus */
#define PCI_PRODUCT_INTEL_100SERIES_SPI 0xa124 /* 100 Series SPI */
#define PCI_PRODUCT_INTEL_100SERIES_GBE 0xa125 /* 100 Series GbE */
#define PCI_PRODUCT_INTEL_100SERIES_TRACE 0xa126 /* 100 Series Trace Hub */
#define PCI_PRODUCT_INTEL_100SERIES_UART_0 0xa127 /* 100 Series UART 0 */
#define PCI_PRODUCT_INTEL_100SERIES_UART_1 0xa128 /* 100 Series UART 1 */
#define PCI_PRODUCT_INTEL_100SERIES_GSPI_0 0xa129 /* 100 Series GSPI 0 */
#define PCI_PRODUCT_INTEL_100SERIES_GSPI_1 0xa12a /* 100 Series GSPI 1 */
#define PCI_PRODUCT_INTEL_100SERIES_XHCI 0xa12f /* 100 Series xHCI */
#define PCI_PRODUCT_INTEL_100SERIES_USB_OTG 0xa130 /* 100 Series USB Device (OTG) */
#define PCI_PRODUCT_INTEL_100SERIES_THERM 0xa131 /* 100 Series Thermal */
#define PCI_PRODUCT_INTEL_100SERIES_ISH 0xa135 /* 100 Series ISH */
#define PCI_PRODUCT_INTEL_100SERIES_MEI_1 0xa13a /* 100 Series MEI 1 */
#define PCI_PRODUCT_INTEL_100SERIES_MEI_2 0xa13b /* 100 Series MEI 2 */
#define PCI_PRODUCT_INTEL_100SERIES_IDE_R 0xa13c /* 100 Series IDE-R */
#define PCI_PRODUCT_INTEL_100SERIES_KT 0xa13d /* 100 Series KT */
#define PCI_PRODUCT_INTEL_100SERIES_MEI_3 0xa13e /* 100 Series MEI 3 */
#define PCI_PRODUCT_INTEL_H170_LPC 0xa144 /* H170 LPC */
#define PCI_PRODUCT_INTEL_Z170_LPC 0xa145 /* Z170 LPC */
#define PCI_PRODUCT_INTEL_Q170_LPC 0xa146 /* Q170 LPC */
#define PCI_PRODUCT_INTEL_100SERIES_I2C_0 0xa160 /* 100 Series I2C 0 */
#define PCI_PRODUCT_INTEL_100SERIES_I2C_1 0xa161 /* 100 Series I2C 1 */
#define PCI_PRODUCT_INTEL_100SERIES_I2C_2 0xa162 /* 100 Series I2C 2 */
#define PCI_PRODUCT_INTEL_100SERIES_I2C_3 0xa163 /* 100 Series I2C 3 */
#define PCI_PRODUCT_INTEL_100SERIES_UART_2 0xa166 /* 100 Series UART 2 */
#define PCI_PRODUCT_INTEL_100SERIES_PCIE_17 0xa167 /* 100 Series PCIE */
#define PCI_PRODUCT_INTEL_100SERIES_PCIE_18 0xa168 /* 100 Series PCIE */
#define PCI_PRODUCT_INTEL_100SERIES_PCIE_19 0xa169 /* 100 Series PCIE */
#define PCI_PRODUCT_INTEL_100SERIES_PCIE_20 0xa16a /* 100 Series PCIE */
#define PCI_PRODUCT_INTEL_100SERIES_HDA 0xa170 /* 100 Series HD Audio */
#define PCI_PRODUCT_INTEL_21152 0xb152 /* S21152BB PCI-PCI Bridge */
#define PCI_PRODUCT_INTEL_21154 0xb154 /* S21152BA,S21154AE/BE PCI-PCI Bridge */
#define PCI_PRODUCT_INTEL_21555 0xb555 /* 21555 Non-Transparent PCI-PCI Bridge */

6499
sys/dev/pci/pcidevs_data.h
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