add VR4181 vrip register maps.
add VR4181 vrip intr levels.
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sato
parent
0f1257e6a3
commit
9804ab7c49
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@ -1,4 +1,4 @@
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/* $NetBSD: vripreg.h,v 1.2 2001/04/18 11:07:28 sato Exp $ */
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/* $NetBSD: vripreg.h,v 1.3 2001/04/21 14:46:36 sato Exp $ */
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/*-
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* Copyright (c) 1999
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@ -36,6 +36,40 @@
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*/
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#define VRIP_NO_ADDR 0x00000000
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/*
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* VR4181 registers
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*/
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#define VR4181_BCU_ADDR 0x0a000000
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#define VR4181_DMAAU_ADDR VRIP_NO_ADDR
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#define VR4181_DCU_ADDR VRIP_NO_ADDR
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#define VR4181_CMU_ADDR 0x0a000004
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#define VR4181_ICU_ADDR 0x0a000080
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#define VR4181_PMU_ADDR 0x0a0000a0
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#define VR4181_RTC_ADDR 0x0a0000c0
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#define VR4181_DSU_ADDR 0x0a0000e0
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#define VR4181_GIU_ADDR VRIP_NO_ADDR /* XXX: no register */
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#define VR4181_PIU_ADDR 0x0a000122
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#define VR4181_AIU_ADDR 0x0a000160
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#define VR4181_KIU_ADDR 0x0a000180
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#define VR4181_DSIU_ADDR 0x0a0001a0
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#define VR4181_LED_ADDR 0x0a000240
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#define VR4181_SIU_ADDR 0x0c000000
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#define VR4181_HSP_ADDR 0x0a000020
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#define VR4181_FIR_ADDR 0x0a000000 /* XXX */
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#define VR4181_MEMCON_ADDR 0x0a000300
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#define VR4181_ISABRG_ADDR 0x0b0002c0
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#define VR4181_ECU_ADDR 0x0b0006e0
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#define VR4181_DCU81_ADDR 0x0a000020
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#define VR4181_CSI81_ADDR 0x0b000900
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#define VR4181_GIU81_ADDR 0x0b000300
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#define VR4181_LCD_ADDR 0x0a000400
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#define VR4181_SIU1_ADDR 0x0c000010
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#define VR4181_SCU_ARR VRIP_NO_ADDR /* XXX: no register */
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#define VR4181_SDRAMU_ADDR VRIP_NO_ADDR /* XXX: no register */
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#define VR4181_PCI_ADDR VRIP_NO_ADDR /* XXX: no register */
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#define VR4181_PCICONF_ADDR VRIP_NO_ADDR /* XXX: no register */
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#define VR4181_CSI_ADDR VRIP_NO_ADDR /* XXX: no register */
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/*
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* VR4101-4121 registers
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*/
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@ -49,19 +83,25 @@
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#define VR4102_DSU_ADDR 0x0b0000e0
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#define VR4102_GIU_ADDR 0x0b000100
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#define VR4102_PIU_ADDR 0x0b000120
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#define VR4102_AIU_ADDR 0x0b000000 /* XXX */
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#define VR4102_AIU_ADDR 0x0b000160
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#define VR4102_KIU_ADDR 0x0b000180
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#define VR4102_DSIU_ADDR 0x0b0001a0
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#define VR4102_LED_ADDR 0x0b000240
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#define VR4102_SIU_ADDR 0x0c000000
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#define VR4102_HSP_ADDR 0x0c000020
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#define VR4102_FIR_ADDR 0x0b000000 /* XXX */
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#define VR4102_MEMCON_ADDR VRIP_NO_ADDR /* XXX: no register */
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#define VR4102_ISABRG_ADDR VRIP_NO_ADDR /* XXX: no register */
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#define VR4102_ECU_ADDR VRIP_NO_ADDR /* XXX: no register */
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#define VR4102_DCU81_ADDR VRIP_NO_ADDR /* XXX: no register */
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#define VR4102_CSI81_ADDR VRIP_NO_ADDR /* XXX: no register */
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#define VR4102_GIU81_ADDR VRIP_NO_ADDR /* XXX: no register */
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#define VR4102_SIU1_ADDR VRIP_NO_ADDR /* XXX: no register */
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#define VR4102_SCU_ARR VRIP_NO_ADDR /* XXX: no register */
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#define VR4102_SDRAMU_ADDR VRIP_NO_ADDR /* XXX: no register */
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#define VR4102_PCI_ADDR VRIP_NO_ADDR /* XXX: no register */
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#define VR4102_PCICONF_ADDR VRIP_NO_ADDR /* XXX: no register */
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#define VR4102_CSI_ADDR VRIP_NO_ADDR /* XXX: no register */
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/*
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* VR4122 registers
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*/
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@ -82,6 +122,13 @@
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#define VR4122_SIU_ADDR 0x0f000800
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#define VR4122_HSP_ADDR VRIP_NO_ADDR /* XXX: no register */
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#define VR4122_FIR_ADDR 0x0f000840 /* XXX */
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#define VR4122_MEMCON_ADDR VRIP_NO_ADDR /* XXX: no register */
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#define VR4122_ISABRG_ADDR VRIP_NO_ADDR /* XXX: no register */
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#define VR4122_ECU_ADDR VRIP_NO_ADDR /* XXX: no register */
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#define VR4122_DCU81_ADDR VRIP_NO_ADDR /* XXX: no register */
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#define VR4122_CSI81_ADDR VRIP_NO_ADDR /* XXX: no register */
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#define VR4122_GIU81_ADDR VRIP_NO_ADDR /* XXX: no register */
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#define VR4122_SIU1_ADDR VRIP_NO_ADDR /* XXX: no register */
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#define VR4122_SCU_ARR 0x0f001000
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#define VR4122_SDRAMU_ADDR 0x00000400
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#define VR4122_PCI_ADDR 0x00000c00
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@ -105,6 +152,38 @@
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#if defined VRGROUP_4181
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#define VRIP_BASE_ADDR 0x0a000000
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#define VRIP_BCU_ADDR VR4181_BCU_ADDR
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#define VRIP_DMAAU_ADDR VR4181_DMAAU_ADDR
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#define VRIP_DCU_ADDR VR4181_DCU_ADDR
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#define VRIP_CMU_ADDR VR4181_CMU_ADDR
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#define VRIP_ICU_ADDR VR4181_ICU_ADDR
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#define VRIP_PMU_ADDR VR4181_PMU_ADDR
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#define VRIP_RTC_ADDR VR4181_RTC_ADDR
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#define VRIP_DSU_ADDR VR4181_DSU_ADDR
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#define VRIP_GIU_ADDR VR4181_GIU_ADDR
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#define VRIP_PIU_ADDR VR4181_PIU_ADDR
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#define VRIP_AIU_ADDR VR4181_AIU_ADDR
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#define VRIP_KIU_ADDR VR4181_KIU_ADDR
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#define VRIP_DSIU_ADDR VR4181_DSIU_ADDR
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#define VRIP_LED_ADDR VR4181_LED_ADDR
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#define VRIP_SIU_ADDR VR4181_SIU_ADDR
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#define VRIP_HSP_ADDR VR4181_HSP_ADDR
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#define VRIP_FIR_ADDR VR4181_FIR_ADDR
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#define VRIP_MEMCON_ADDR VR4181_MEMCON_ADDR
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#define VRIP_ISABRG_ADDR VR4181_ISABRG_ADDR
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#define VRIP_ECU_ADDR VR4181_ECU_ADDR
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#define VRIP_DCU81_ADDR VR4181_DCU81_ADDR
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#define VRIP_CSI81_ADDR VR4181_CSI81_ADDR
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#define VRIP_GIU81_ADDR VR4181_GIU81_ADDR
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#define VRIP_LCD_ADDR VR4181_LCD_ADDR
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#define VRIP_SIU1_ADDR VR4181_SIU1_ADDR
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#define VRIP_SCU_ARR VR4181_SCU_ARR /* XXX: no register */
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#define VRIP_SDRAMU_ADDR VR4181_SDRAMU_ADDR /* XXX: no register */
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#define VRIP_PCI_ADDR VR4181_PCI_ADDR /* XXX: no register */
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#define VRIP_PCICONF_ADDR VR4181_PCICONF_ADDR /* XXX: no register */
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#define VRIP_CSI_ADDR VR4181_CSI_ADDR /* XXX: no register */
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#endif /* VRGROUP_4181 */
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#if defined VRGROUP_4122
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@ -127,6 +206,13 @@
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#define VRIP_SIU_ADDR VR4122_SIU_ADDR
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#define VRIP_HSP_ADDR VR4122_HSP_ADDR
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#define VRIP_FIR_ADDR VR4122_FIR_ADDR
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#define VRIP_MEMCON_ADDR VR4122_MEMCON_ADDR /* XXX: no register */
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#define VRIP_ISABRG_ADDR VR4122_ISABRG_ADDR /* XXX: no register */
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#define VRIP_ECU_ADDR VR4122_ECU_ADDR /* XXX: no register */
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#define VRIP_DCU81_ADDR VR4122_DCU81_ADDR /* XXX: no register */
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#define VRIP_CSI81_ADDR VR4122_CSI81_ADDR /* XXX: no register */
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#define VRIP_GIU81_ADDR VR4122_CSI81_ADDR /* XXX: no register */
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#define VRIP_SIU1_ADDR VR4122_SIU1_ADDR /* XXX: no register */
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#define VRIP_SCU_ARR VR4122_SCU_ARR /* XXX: no register */
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#define VRIP_SDRAMU_ADDR VR4122_SDRAMU_ADDR /* XXX: no register */
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#define VRIP_PCI_ADDR VR4122_PCI_ADDR /* XXX: no register */
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@ -155,6 +241,13 @@
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#define VRIP_SIU_ADDR VR4102_SIU_ADDR
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#define VRIP_HSP_ADDR VR4102_HSP_ADDR
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#define VRIP_FIR_ADDR VR4102_FIR_ADDR
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#define VRIP_MEMCON_ADDR VR4102_MEMCON_ADDR /* XXX: no register */
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#define VRIP_ISABRG_ADDR VR4102_ISABRG_ADDR /* XXX: no register */
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#define VRIP_ECU_ADDR VR4102_ECU_ADDR /* XXX: no register */
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#define VRIP_DCU81_ADDR VR4102_DCU81_ADDR /* XXX: no register */
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#define VRIP_CSI81_ADDR VR4102_CSI81_ADDR /* XXX: no register */
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#define VRIP_GIU81_ADDR VR4102_CSI81_ADDR /* XXX: no register */
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#define VRIP_SIU1_ADDR VR4102_SIU1_ADDR /* XXX: no register */
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#define VRIP_SCU_ARR VR4102_SCU_ARR /* XXX: no register */
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#define VRIP_SDRAMU_ADDR VR4102_SDRAMU_ADDR /* XXX: no register */
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#define VRIP_PCI_ADDR VR4102_PCI_ADDR /* XXX: no register */
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#define VRIP_INTR_CSI 24
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#define VRIP_INTR_SCU 23
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#define VRIP_INTR_PCI 22
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#define VRIP_INTR_LCD 22 /* 4181 */
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#define VRIP_INTR_DSIU 21
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#define VRIP_INTR_DCU81 21 /* 4181 */
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#define VRIP_INTR_FIR 20
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#define VRIP_INTR_TCLK 19
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#define VRIP_INTR_CSI81 19 /* 4181 */
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#define VRIP_INTR_HSP 18
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#define VRIP_INTR_ECU 18 /* 4181 */
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#define VRIP_INTR_LED 17
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#define VRIP_INTR_RTCL2 16
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/* reserved 15,14 */
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