Support Basic Mode for Armada XP.
This commit is contained in:
kiyohara
parent
7598b3c28a
commit
9745ea1238
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@ -1,6 +1,6 @@
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/* $NetBSD: if_mvgbe.c,v 1.34 2012/12/28 08:16:53 msaitoh Exp $ */
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/* $NetBSD: if_mvgbe.c,v 1.35 2013/12/23 02:23:25 kiyohara Exp $ */
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/*
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* Copyright (c) 2007, 2008 KIYOHARA Takashi
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* Copyright (c) 2007, 2008, 2013 KIYOHARA Takashi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -25,7 +25,13 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_mvgbe.c,v 1.34 2012/12/28 08:16:53 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: if_mvgbe.c,v 1.35 2013/12/23 02:23:25 kiyohara Exp $");
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#include "opt_multiprocessor.h"
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#if defined MULTIPROCESSOR
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#warning Queue Management Method 'Counters' not support yet
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#endif
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#include <sys/param.h>
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#include <sys/bus.h>
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@ -80,6 +86,10 @@ int mvgbe_debug = MVGBE_DEBUG;
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#define MVGBE_WRITE_FILTER(sc, reg, val, c) \
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bus_space_write_region_4((sc)->sc_iot, (sc)->sc_dafh, (reg), (val), (c))
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#define MVGBE_LINKUP_READ(sc) \
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bus_space_read_4((sc)->sc_iot, (sc)->sc_linkup.ioh, 0)
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#define MVGBE_IS_LINKUP(sc) (MVGBE_LINKUP_READ(sc) & (sc)->sc_linkup.bit)
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#define MVGBE_TX_RING_CNT 256
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#define MVGBE_TX_RING_MSK (MVGBE_TX_RING_CNT - 1)
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#define MVGBE_TX_RING_NEXT(x) (((x) + 1) & MVGBE_TX_RING_MSK)
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@ -208,6 +218,7 @@ struct mvgbec_softc {
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struct mvgbe_softc {
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device_t sc_dev;
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int sc_port;
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uint32_t sc_version;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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@ -232,6 +243,12 @@ struct mvgbe_softc {
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LIST_HEAD(__mvgbe_jinusehead, mvgbe_jpool_entry) sc_jinuse_listhead;
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SIMPLEQ_HEAD(__mvgbe_txmaphead, mvgbe_txmap_entry) sc_txmap_head;
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struct {
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bus_space_handle_t ioh;
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uint32_t bit;
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} sc_linkup;
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uint32_t sc_cmdsts_opts;
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krndsource_t sc_rnd_source;
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struct sysctllog *mvgbe_clog;
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#ifdef MVGBE_EVENT_COUNTERS
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@ -318,6 +335,7 @@ struct mvgbe_port {
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#define FLAGS_FIX_MTU (1 << 1)
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#define FLAGS_IPG1 (1 << 2)
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#define FLAGS_IPG2 (1 << 3)
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#define FLAGS_HAS_PV (1 << 4) /* Has Port Version Register */
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} mvgbe_ports[] = {
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{ MARVELL_DISCOVERY_II, 0, 3, { 32, 33, 34 }, 0 },
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{ MARVELL_DISCOVERY_III, 0, 3, { 32, 33, 34 }, 0 },
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@ -348,6 +366,25 @@ struct mvgbe_port {
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{ MARVELL_MV78XX0_MV78200, 1, 1, { 44 }, FLAGS_FIX_TQTB | FLAGS_IPG2 },
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{ MARVELL_MV78XX0_MV78200, 2, 1, { 48 }, FLAGS_FIX_TQTB | FLAGS_IPG2 },
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{ MARVELL_MV78XX0_MV78200, 3, 1, { 52 }, FLAGS_FIX_TQTB | FLAGS_IPG2 },
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{ MARVELL_ARMADAXP_MV78130, 0, 1, { 66 }, FLAGS_HAS_PV },
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{ MARVELL_ARMADAXP_MV78130, 1, 1, { 70 }, FLAGS_HAS_PV },
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{ MARVELL_ARMADAXP_MV78130, 2, 1, { 74 }, FLAGS_HAS_PV },
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{ MARVELL_ARMADAXP_MV78160, 0, 1, { 66 }, FLAGS_HAS_PV },
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{ MARVELL_ARMADAXP_MV78160, 1, 1, { 70 }, FLAGS_HAS_PV },
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{ MARVELL_ARMADAXP_MV78160, 2, 1, { 74 }, FLAGS_HAS_PV },
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{ MARVELL_ARMADAXP_MV78160, 3, 1, { 78 }, FLAGS_HAS_PV },
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{ MARVELL_ARMADAXP_MV78230, 0, 1, { 66 }, FLAGS_HAS_PV },
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{ MARVELL_ARMADAXP_MV78230, 1, 1, { 70 }, FLAGS_HAS_PV },
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{ MARVELL_ARMADAXP_MV78230, 2, 1, { 74 }, FLAGS_HAS_PV },
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{ MARVELL_ARMADAXP_MV78260, 0, 1, { 66 }, FLAGS_HAS_PV },
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{ MARVELL_ARMADAXP_MV78260, 1, 1, { 70 }, FLAGS_HAS_PV },
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{ MARVELL_ARMADAXP_MV78260, 2, 1, { 74 }, FLAGS_HAS_PV },
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{ MARVELL_ARMADAXP_MV78260, 3, 1, { 78 }, FLAGS_HAS_PV },
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{ MARVELL_ARMADAXP_MV78460, 0, 1, { 66 }, FLAGS_HAS_PV },
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{ MARVELL_ARMADAXP_MV78460, 1, 1, { 70 }, FLAGS_HAS_PV },
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{ MARVELL_ARMADAXP_MV78460, 2, 1, { 74 }, FLAGS_HAS_PV },
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{ MARVELL_ARMADAXP_MV78460, 3, 1, { 78 }, FLAGS_HAS_PV },
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};
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@ -654,6 +691,7 @@ mvgbe_match(device_t parent, cfdata_t match, void *aux)
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static void
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mvgbe_attach(device_t parent, device_t self, void *aux)
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{
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struct mvgbec_softc *csc = device_private(parent);
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struct mvgbe_softc *sc = device_private(self);
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struct marvell_attach_args *mva = aux;
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struct mvgbe_txmap_entry *entry;
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@ -687,6 +725,33 @@ mvgbe_attach(device_t parent, device_t self, void *aux)
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}
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sc->sc_dmat = mva->mva_dmat;
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if (csc->sc_flags & FLAGS_HAS_PV) {
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/* GbE port has Port Version register. */
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sc->sc_version = MVGBE_READ(sc, MVGBE_PV);
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aprint_normal_dev(self, "Port Version 0x%x\n", sc->sc_version);
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}
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if (sc->sc_version >= 0x10) {
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/*
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* Armada XP
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*/
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if (bus_space_subregion(mva->mva_iot, mva->mva_ioh,
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MVGBE_PS0, sizeof(uint32_t), &sc->sc_linkup.ioh)) {
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aprint_error_dev(self, "Cannot map linkup register\n");
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return;
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}
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sc->sc_linkup.bit = MVGBE_PS0_LINKUP;
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csc->sc_flags |= FLAGS_IPG2;
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} else {
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if (bus_space_subregion(mva->mva_iot, sc->sc_ioh,
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MVGBE_PS, sizeof(uint32_t), &sc->sc_linkup.ioh)) {
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aprint_error_dev(self, "Cannot map linkup register\n");
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return;
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}
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sc->sc_linkup.bit = MVGBE_PS_LINKUP;
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}
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maddrh = MVGBE_READ(sc, MVGBE_MACAH);
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maddrl = MVGBE_READ(sc, MVGBE_MACAL);
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sc->sc_enaddr[0] = maddrh >> 24;
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@ -938,13 +1003,13 @@ mvgbe_intr(void *arg)
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break;
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if (ice & MVGBE_ICE_LINKCHG) {
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if (MVGBE_READ(sc, MVGBE_PS) & MVGBE_PS_LINKUP) {
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if (MVGBE_IS_LINKUP(sc)) {
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/* Enable port RX and TX. */
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MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_ENQ(0));
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MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ);
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MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0));
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} else {
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MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ(0));
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MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ);
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MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ(0));
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}
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/* Notify link change event to mii layer */
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@ -954,7 +1019,7 @@ mvgbe_intr(void *arg)
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if (ic & (MVGBE_IC_RXBUF | MVGBE_IC_RXERROR))
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mvgbe_rxeof(sc);
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if (ice & (MVGBE_ICE_TXBUF | MVGBE_ICE_TXERR))
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if (ice & (MVGBE_ICE_TXBUF_MASK | MVGBE_ICE_TXERR_MASK))
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mvgbe_txeof(sc);
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}
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@ -980,7 +1045,7 @@ mvgbe_start(struct ifnet *ifp)
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if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
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return;
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/* If Link is DOWN, can't start TX */
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if (!(MVGBE_READ(sc, MVGBE_PS) & MVGBE_PS_LINKUP))
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if (!MVGBE_IS_LINKUP(sc))
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return;
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while (sc->sc_cdata.mvgbe_tx_chain[idx].mvgbe_mbuf == NULL) {
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@ -1014,7 +1079,7 @@ mvgbe_start(struct ifnet *ifp)
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/* Transmit at Queue 0 */
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if (idx != sc->sc_cdata.mvgbe_tx_prod) {
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sc->sc_cdata.mvgbe_tx_prod = idx;
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MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ);
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MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0));
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/*
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* Set a timeout in case the chip goes out to lunch.
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@ -1092,17 +1157,49 @@ mvgbe_init(struct ifnet *ifp)
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}
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if (csc->sc_flags & FLAGS_FIX_MTU)
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MVGBE_WRITE(sc, MVGBE_MTU, 0); /* hw reset value is wrong */
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MVGBE_WRITE(sc, MVGBE_PSC,
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MVGBE_PSC_ANFC | /* Enable Auto-Neg Flow Ctrl */
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MVGBE_PSC_RESERVED | /* Must be set to 1 */
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MVGBE_PSC_FLFAIL | /* Do NOT Force Link Fail */
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MVGBE_PSC_MRU(MVGBE_PSC_MRU_9022) | /* we want 9k */
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MVGBE_PSC_SETFULLDX); /* Set_FullDx */
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/* XXXX: mvgbe(4) always use RGMII. */
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MVGBE_WRITE(sc, MVGBE_PSC1,
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MVGBE_READ(sc, MVGBE_PSC1) | MVGBE_PSC1_RGMIIEN);
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/* XXXX: Also always Weighted Round-Robin Priority Mode */
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MVGBE_WRITE(sc, MVGBE_TQFPC, MVGBE_TQFPC_EN(0));
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if (sc->sc_version >= 0x10) {
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MVGBE_WRITE(csc, MVGBE_PANC,
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MVGBE_PANC_FORCELINKPASS |
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MVGBE_PANC_INBANDANBYPASSEN |
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MVGBE_PANC_SETMIISPEED |
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MVGBE_PANC_SETGMIISPEED |
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MVGBE_PANC_ANSPEEDEN |
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MVGBE_PANC_SETFCEN |
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MVGBE_PANC_PAUSEADV |
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MVGBE_PANC_SETFULLDX |
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MVGBE_PANC_ANDUPLEXEN |
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MVGBE_PANC_RESERVED);
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MVGBE_WRITE(csc, MVGBE_PMACC0,
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MVGBE_PMACC0_RESERVED |
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MVGBE_PMACC0_FRAMESIZELIMIT(1600));
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MVGBE_WRITE(csc, MVGBE_PMACC2,
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MVGBE_PMACC2_PCSEN |
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MVGBE_PMACC2_RESERVED |
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MVGBE_PMACC2_RGMIIEN);
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MVGBE_WRITE(sc, MVGBE_PXCX,
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MVGBE_READ(sc, MVGBE_PXCX) & ~MVGBE_PXCX_TXCRCDIS);
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#ifndef MULTIPROCESSOR
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MVGBE_WRITE(sc, MVGBE_PACC, MVGVE_PACC_ACCELERATIONMODE_BM);
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#else
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MVGBE_WRITE(sc, MVGBE_PACC, MVGVE_PACC_ACCELERATIONMODE_EDM);
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#endif
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} else {
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MVGBE_WRITE(sc, MVGBE_PSC,
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MVGBE_PSC_ANFC | /* Enable Auto-Neg Flow Ctrl */
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MVGBE_PSC_RESERVED | /* Must be set to 1 */
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MVGBE_PSC_FLFAIL | /* Do NOT Force Link Fail */
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MVGBE_PSC_MRU(MVGBE_PSC_MRU_9022) | /* we want 9k */
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MVGBE_PSC_SETFULLDX); /* Set_FullDx */
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/* XXXX: mvgbe(4) always use RGMII. */
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MVGBE_WRITE(sc, MVGBE_PSC1,
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MVGBE_READ(sc, MVGBE_PSC1) | MVGBE_PSC1_RGMIIEN);
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/* XXXX: Also always Weighted Round-Robin Priority Mode */
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MVGBE_WRITE(sc, MVGBE_TQFPC, MVGBE_TQFPC_EN(0));
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sc->sc_cmdsts_opts = MVGBE_TX_GENERATE_CRC;
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}
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MVGBE_WRITE(sc, MVGBE_CRDP(0), MVGBE_RX_RING_ADDR(sc, 0));
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MVGBE_WRITE(sc, MVGBE_TCQDP, MVGBE_TX_RING_ADDR(sc, 0));
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@ -1119,7 +1216,7 @@ mvgbe_init(struct ifnet *ifp)
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MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x0);
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MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0x0);
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}
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} else
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} else if (sc->sc_version < 0x10)
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for (i = 1; i < 8; i++) {
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MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x3fffffff);
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MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0xffff7fff);
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@ -1149,14 +1246,19 @@ mvgbe_init(struct ifnet *ifp)
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mii_mediachg(mii);
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/* Enable port */
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reg = MVGBE_READ(sc, MVGBE_PSC);
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MVGBE_WRITE(sc, MVGBE_PSC, reg | MVGBE_PSC_PORTEN);
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if (sc->sc_version >= 0x10) {
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reg = MVGBE_READ(csc, MVGBE_PMACC0);
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MVGBE_WRITE(csc, MVGBE_PMACC0, reg | MVGBE_PMACC0_PORTEN);
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} else {
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reg = MVGBE_READ(sc, MVGBE_PSC);
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MVGBE_WRITE(sc, MVGBE_PSC, reg | MVGBE_PSC_PORTEN);
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}
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/* If Link is UP, Start RX and TX traffic */
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if (MVGBE_READ(sc, MVGBE_PS) & MVGBE_PS_LINKUP) {
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if (MVGBE_IS_LINKUP(sc)) {
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/* Enable port RX/TX. */
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MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_ENQ(0));
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MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ);
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MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0));
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}
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/* Enable interrupt masks */
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@ -1167,8 +1269,8 @@ mvgbe_init(struct ifnet *ifp)
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MVGBE_IC_RXERROR |
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MVGBE_IC_RXERRQ_MASK);
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MVGBE_WRITE(sc, MVGBE_PEIM,
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MVGBE_ICE_TXBUF |
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MVGBE_ICE_TXERR |
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MVGBE_ICE_TXBUF_MASK |
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MVGBE_ICE_TXERR_MASK |
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MVGBE_ICE_LINKCHG);
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callout_schedule(&sc->sc_tick_ch, hz);
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@ -1186,7 +1288,7 @@ mvgbe_stop(struct ifnet *ifp, int disable)
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struct mvgbe_softc *sc = ifp->if_softc;
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struct mvgbec_softc *csc = device_private(device_parent(sc->sc_dev));
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struct mvgbe_chain_data *cdata = &sc->sc_cdata;
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uint32_t reg;
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uint32_t reg, txinprog, txfifoemp;
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int i, cnt;
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DPRINTFN(2, ("mvgbe_stop\n"));
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@ -1200,12 +1302,23 @@ mvgbe_stop(struct ifnet *ifp, int disable)
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MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ_DISABLE(reg));
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/* Stop Tx port activity. Check port Tx activity. */
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if (MVGBE_READ(sc, MVGBE_TQC) & MVGBE_TQC_ENQ)
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MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ);
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if (MVGBE_READ(sc, MVGBE_TQC) & MVGBE_TQC_ENQ(0))
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MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ(0));
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/* Force link down */
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reg = MVGBE_READ(sc, MVGBE_PSC);
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MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_FLFAIL);
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if (sc->sc_version >= 0x10) {
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reg = MVGBE_READ(csc, MVGBE_PANC);
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MVGBE_WRITE(csc, MVGBE_PANC, reg | MVGBE_PANC_FORCELINKFAIL);
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txinprog = MVGBE_PS_TXINPROG_(0);
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txfifoemp = MVGBE_PS_TXFIFOEMP_(0);
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} else {
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reg = MVGBE_READ(sc, MVGBE_PSC);
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MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_FLFAIL);
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txinprog = MVGBE_PS_TXINPROG;
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txfifoemp = MVGBE_PS_TXFIFOEMP;
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}
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#define RX_DISABLE_TIMEOUT 0x1000000
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#define TX_FIFO_EMPTY_TIMEOUT 0x1000000
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@ -1239,15 +1352,14 @@ mvgbe_stop(struct ifnet *ifp, int disable)
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cnt++;
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reg = MVGBE_READ(sc, MVGBE_PS);
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} while
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(!(reg & MVGBE_PS_TXFIFOEMP) || reg & MVGBE_PS_TXINPROG);
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} while (!(reg & txfifoemp) || reg & txinprog);
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if (cnt >= TX_FIFO_EMPTY_TIMEOUT)
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break;
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/* Double check */
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reg = MVGBE_READ(sc, MVGBE_PS);
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if (reg & MVGBE_PS_TXFIFOEMP && !(reg & MVGBE_PS_TXINPROG))
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if (reg & txfifoemp && !(reg & txinprog))
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break;
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else
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aprint_error_ifnet(ifp,
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@ -1255,9 +1367,14 @@ mvgbe_stop(struct ifnet *ifp, int disable)
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" %d loops, status 0x%x\n", cnt, reg);
|
||||
}
|
||||
|
||||
/* Reset the Enable bit in the Port Serial Control Register */
|
||||
reg = MVGBE_READ(sc, MVGBE_PSC);
|
||||
MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_PORTEN);
|
||||
/* Reset the Enable bit */
|
||||
if (sc->sc_version >= 0x10) {
|
||||
reg = MVGBE_READ(csc, MVGBE_PMACC0);
|
||||
MVGBE_WRITE(csc, MVGBE_PMACC0, reg & ~MVGBE_PMACC0_PORTEN);
|
||||
} else {
|
||||
reg = MVGBE_READ(sc, MVGBE_PSC);
|
||||
MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_PORTEN);
|
||||
}
|
||||
|
||||
/*
|
||||
* Disable and clear interrupts
|
||||
|
|
@ -1306,7 +1423,7 @@ mvgbe_watchdog(struct ifnet *ifp)
|
|||
* engine. When DMA engine encounters queue end,
|
||||
* it clears MVGBE_TQC_ENQ bit.
|
||||
*/
|
||||
MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ);
|
||||
MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0));
|
||||
ifp->if_timer = 5;
|
||||
sc->sc_wdogsoft = 0;
|
||||
MVGBE_EVCNT_INCR(&sc->sc_ev_wdogsoft);
|
||||
|
|
@ -1661,7 +1778,7 @@ mvgbe_encap(struct mvgbe_softc *sc, struct mbuf *m_head,
|
|||
struct mvgbe_txmap_entry *entry;
|
||||
bus_dma_segment_t *txseg;
|
||||
bus_dmamap_t txmap;
|
||||
uint32_t first, current, last, cmdsts = 0;
|
||||
uint32_t first, current, last, cmdsts;
|
||||
int m_csumflags, i;
|
||||
bool needs_defrag = false;
|
||||
|
||||
|
|
@ -1745,6 +1862,7 @@ do_defrag:
|
|||
current = MVGBE_TX_RING_NEXT(current);
|
||||
}
|
||||
|
||||
cmdsts = sc->sc_cmdsts_opts;
|
||||
if (m_csumflags & M_CSUM_IPv4)
|
||||
cmdsts |= MVGBE_TX_GENERATE_IP_CHKSUM;
|
||||
if (m_csumflags & M_CSUM_TCPv4)
|
||||
|
|
@ -1761,16 +1879,13 @@ do_defrag:
|
|||
}
|
||||
if (txmap->dm_nsegs == 1)
|
||||
f->cmdsts = cmdsts |
|
||||
MVGBE_TX_GENERATE_CRC |
|
||||
MVGBE_TX_ENABLE_INTERRUPT |
|
||||
MVGBE_TX_ZERO_PADDING |
|
||||
MVGBE_TX_FIRST_DESC |
|
||||
MVGBE_TX_LAST_DESC;
|
||||
else {
|
||||
f = &sc->sc_rdata->mvgbe_tx_ring[first];
|
||||
f->cmdsts = cmdsts |
|
||||
MVGBE_TX_GENERATE_CRC |
|
||||
MVGBE_TX_FIRST_DESC;
|
||||
f->cmdsts = cmdsts | MVGBE_TX_FIRST_DESC;
|
||||
|
||||
f = &sc->sc_rdata->mvgbe_tx_ring[last];
|
||||
f->cmdsts =
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/* $NetBSD: mvgbereg.h,v 1.7 2012/11/08 15:39:30 msaitoh Exp $ */
|
||||
/* $NetBSD: mvgbereg.h,v 1.8 2013/12/23 02:23:25 kiyohara Exp $ */
|
||||
/*
|
||||
* Copyright (c) 2007 KIYOHARA Takashi
|
||||
* Copyright (c) 2007, 2013 KIYOHARA Takashi
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
|
@ -37,6 +37,35 @@
|
|||
/*
|
||||
* Ethernet Unit Registers
|
||||
*/
|
||||
|
||||
#define MVGBE_PRXC(q) (0x1400 + ((q) << 2)) /*Port RX queues Config*/
|
||||
#define MVGBE_PRXSNP(q) (0x1420 + ((q) << 2)) /* Port RX queues Snoop */
|
||||
#define MVGBE_PRXF01(q) (0x1440 + ((q) << 2)) /* Port RX Prefetch 0_1 */
|
||||
#define MVGBE_PRXF23(q) (0x1460 + ((q) << 2)) /* Port RX Prefetch 2_3 */
|
||||
#define MVGBE_PRXDQA(q) (0x1480 + ((q) << 2)) /*P RXqueues desc Q Addr*/
|
||||
#define MVGBE_PRXDQS(q) (0x14a0 + ((q) << 2)) /*P RXqueues desc Q Size*/
|
||||
#define MVGBE_PRXDQTH(q) (0x14c0 + ((q) << 2)) /*P RXqueues desc Q Thrs*/
|
||||
#define MVGBE_PRXS(q) (0x14e0 + ((q) << 2)) /*Port RX queues Status */
|
||||
#define MVGBE_PRXSU(q) (0x1500 + ((q) << 2)) /*P RXqueues Stat Update*/
|
||||
#define MVGBE_PPLBSZ(q) (0x1700 + ((q) << 2)) /* P Pool n Buffer Size */
|
||||
#define MVGBE_PRXFC 0x1710 /* Port RX Flow Control */
|
||||
#define MVGBE_PRXTXP 0x1714 /* Port RX_TX Pause */
|
||||
#define MVGBE_PRXFCG 0x1718 /* Port RX Flow Control Generation */
|
||||
#define MVGBE_PRXINIT 0x1cc0 /* Port RX Initialization */
|
||||
#define MVGBE_RXCTRL 0x1d00 /* RX Control */
|
||||
#define MVGBE_RXHWFWD(n) (0x1d10 + (((n) & ~0x1) << 1))
|
||||
/* RX Hardware Forwarding (0_1, 2_3,..., 8_9) */
|
||||
#define MVGBE_RXHWFWDPTR 0x1d30 /* RX Hardware Forwarding Pointer */
|
||||
#define MVGBE_RXHWFWDTH 0x1d40 /* RX Hardware Forwarding Threshold */
|
||||
#define MVGBE_RXHWFWDDQA 0x1d44 /* RX Hw Fwd Descriptors Queue Address*/
|
||||
#define MVGBE_RXHWFWDQS 0x1d48 /* RX Hw Fwd Descriptors Queue Size */
|
||||
#define MVGBE_RXHWFWDQENB 0x1d4c /* RX Hw Fwd Queue Enable */
|
||||
#define MVGBE_RXHWFWDACPT 0x1d50 /* RX Hw Forwarding Accepted Counter */
|
||||
#define MVGBE_RXHWFWDYDSCRD 0x1d54 /* RX Hw Fwd Yellow Discarded Counter */
|
||||
#define MVGBE_RXHWFWDGDSCRD 0x1d58 /* RX Hw Fwd Green Discarded Counter */
|
||||
#define MVGBE_RXHWFWDTHDSCRD 0x1d5c /*RX HwFwd Threshold Discarded Counter*/
|
||||
#define MVGBE_RXHWFWDTXGAP 0x1d6c /*RX Hardware Forwarding TX Access Gap*/
|
||||
|
||||
/* Ethernet Unit Global Registers */
|
||||
#define MVGBE_PHYADDR 0x2000
|
||||
#if defined(MV88W8660)
|
||||
|
|
@ -78,6 +107,7 @@
|
|||
#define MVGBE_PS 0x044 /* Ethernet Port Status */
|
||||
#define MVGBE_TQC 0x048 /* Transmit Queue Command */
|
||||
#define MVGBE_PSC1 0x04c /* Port Serial Control1 */
|
||||
#define MVGBE_MH 0x054 /* Marvell Header */
|
||||
#define MVGBE_MTU 0x058 /* Max Transmit Unit */
|
||||
#define MVGBE_IC 0x060 /* Port Interrupt Cause */
|
||||
#define MVGBE_ICE 0x064 /* Port Interrupt Cause Extend */
|
||||
|
|
@ -85,11 +115,22 @@
|
|||
#define MVGBE_PEIM 0x06c /* Port Extend Interrupt Mask */
|
||||
#define MVGBE_PRFUT 0x070 /* Port Rx FIFO Urgent Threshold */
|
||||
#define MVGBE_PTFUT 0x074 /* Port Tx FIFO Urgent Threshold */
|
||||
#define MVGBE_PXTFTT 0x078 /* Port Tx FIFO Threshold */
|
||||
#define MVGBE_PMFS 0x07c /* Port Rx Minimal Frame Size */
|
||||
#define MVGBE_PXDFC 0x084 /* Port Rx Discard Frame Counter */
|
||||
#define MVGBE_POFC 0x088 /* Port Overrun Frame Counter */
|
||||
#define MVGBE_PIAE 0x094 /* Port Internal Address Error */
|
||||
#define MVGBE_AIP0ADR 0x098 /* Arp IP0 Address */
|
||||
#define MVGBE_AIP1ADR 0x09c /* Arp IP1 Address */
|
||||
#define MVGBE_SERDESCFG 0x0a0 /* Serdes Configuration */
|
||||
#define MVGBE_SERDESSTS 0x0a4 /* Serdes Status */
|
||||
#define MVGBE_ETP 0x0bc /* Ethernet Type Priority */
|
||||
#define MVGBE_TQFPC 0x0dc /* Transmit Queue Fixed Priority Cfg */
|
||||
#define MVGBE_OMSCD 0x0f4 /* One mS Clock Divider */
|
||||
#define MVGBE_PFCCD 0x0f8 /* Periodic Flow Control Clock Divider*/
|
||||
#define MVGBE_PACC 0x100 /* Port Acceleration Mode */
|
||||
#define MVGBE_PBMADDR 0x104 /* Port BM Address */
|
||||
#define MVGBE_PV 0x1bc /* Port Version */
|
||||
#define MVGBE_CRDP(n) (0x20c + ((n) << 4))
|
||||
/* Ethernet Current Receive Descriptor Pointers */
|
||||
#define MVGBE_RQC 0x280 /* Receive Queue Command */
|
||||
|
|
@ -102,6 +143,44 @@
|
|||
#define MVGBE_TQAC(q) (0x308 + ((q) << 4))
|
||||
/* Transmit Queue Arbiter Configuration */
|
||||
|
||||
#define MVGBE_PCP2Q(cpu) (0x2540 + ((cpu) << 2)) /* Port CPUn to Queue */
|
||||
#define MVGBE_PRXITTH(q) (0x2540 + ((q) << 2) /* Port RX Intr Threshold*/
|
||||
#define MVGBE_PRXTXTIC 0x25a0 /*Port RX_TX Threshold Interrupt Cause*/
|
||||
#define MVGBE_PRXTXTIM 0x25a4 /*Port RX_TX Threshold Interrupt Mask */
|
||||
#define MVGBE_PRXTXIC 0x25a8 /* Port RX_TX Interrupt Cause */
|
||||
#define MVGBE_PRXTXIM 0x25ac /* Port RX_TX Interrupt Mask */
|
||||
#define MVGBE_PMIC 0x25b0 /* Port Misc Interrupt Cause */
|
||||
#define MVGBE_PMIM 0x25b4 /* Port Misc Interrupt Mask */
|
||||
#define MVGBE_PIE 0x25b8 /* Port Interrupt Enable */
|
||||
|
||||
#define MVGBE_PMACC0 0x2c00 /* Port MAC Control 0 */
|
||||
#define MVGBE_PMACC1 0x2c04 /* Port MAC Control 1 */
|
||||
#define MVGBE_PMACC2 0x2c08 /* Port MAC Control 2 */
|
||||
#define MVGBE_PANC 0x2c0c /* Port Auto-Negotiation Configuration*/
|
||||
#define MVGBE_PS0 0x2c10 /* Port Status 0 */
|
||||
#define MVGBE_PSPC 0x2c14 /* Port Serial Parameters Config */
|
||||
#define MVGBE_PIC_2 0x2c20 /* Port Interrupt Cause */
|
||||
#define MVGBE_PIM_2 0x2c24 /* Port Interrupt Mask */
|
||||
#define MVGBE_PPRBSS 0x2c38 /* Port PRBS Status */
|
||||
#define MVGBE_PPRBSEC 0x2c3c /* Port PRBS Error Counter */
|
||||
#define MVGBE_PMACC3 0x2c48 /* Port MAC Control 3 */
|
||||
#define MVGBE_CCFCPST(p) (0x2c58 + ((p) << 2)) /*CCFC Port Speed Timerp*/
|
||||
#define MVGBE_PMACC4 0x2c90 /* Port MAC Control 4 */
|
||||
#define MVGBE_PSP1C 0x2c94 /* Port Serial Parameters 1 Config */
|
||||
#define MVGBE_LPIC0 0x2cc0 /* LowPowerIdle control 0 */
|
||||
#define MVGBE_LPIC1 0x2cc4 /* LPI control 1 */
|
||||
#define MVGBE_LPIC2 0x2cc8 /* LPI control 2 */
|
||||
#define MVGBE_LPIS 0x2ccc /* LPI status */
|
||||
#define MVGBE_LPIC 0x2cd0 /* LPI counter */
|
||||
|
||||
#define MVGBE_PPLLC 0x2e04 /* Power and PLL Control */
|
||||
#define MVGBE_DLE 0x2e8c /* Digital Loopback Enable */
|
||||
#define MVGBE_RCS 0x2f18 /* Reference Clock Select */
|
||||
|
||||
/* MAC MIB Counters 0x3000 - 0x307c */
|
||||
|
||||
/* Rx DMA Wake on LAN Registers 0x3690 - 0x36b8 */
|
||||
|
||||
#define MVGBE_PORTDAFR_BASE 0x3400
|
||||
#define MVGBE_PORTDAFR_SIZE 0x400
|
||||
|
||||
|
|
@ -115,9 +194,24 @@
|
|||
#define MVGBE_DFUT 0x200
|
||||
/* Destination Address Filter Unicast Table */
|
||||
|
||||
#define MVGBE_PTXDQA(q) (0x3c00 + ((q) << 2)) /*P TXqueues desc Q Addr*/
|
||||
#define MVGBE_PTXDQS(q) (0x3c20 + ((q) << 2)) /*P TXqueues desc Q Size*/
|
||||
#define MVGBE_PTXS(q) (0x3c40 + ((q) << 2)) /* Port TX queues Status*/
|
||||
#define MVGBE_PTXSU(q) (0x3c60 + ((q) << 2)) /*P TXqueues Stat Update*/
|
||||
#define MVGBE_PTXDI(q) (0x3c80 + ((q) << 2)) /* P TXqueues Desc Index*/
|
||||
#define MVGBE_TXTBC(q) (0x3ca0 + ((q) << 2)) /* TX Trans-ed Buf Count*/
|
||||
#define MVGBE_PTXINIT 0x3cf0 /* Port TX Initialization */
|
||||
#define MVGBE_PTXDOSD 0x3cf4 /* Port TX Disable Outstanding Reads */
|
||||
|
||||
/* MAC MIB Counters 0x3000 - 0x307c */
|
||||
#define MVGBE_TXBADFCS 0x3cc0 /*Tx Bad FCS Transmitted Pckts Counter*/
|
||||
#define MVGBE_TXDROPPED 0x3cc4 /* Tx Dropped Packets Counter */
|
||||
#define MVGBE_TXNB 0x3cfc /* Tx Number of New Bytes */
|
||||
#define MVGBE_TXGB 0x3d00 /* Tx Green Number of Bytes */
|
||||
#define MVGBE_TXYB 0x3d04 /* Tx Yellow Number of Bytes */
|
||||
|
||||
/* Tx DMA Packet Modification Registers 0x3d00 - 0x3dff */
|
||||
|
||||
/* Tx DMA Queue Arbiter Registers 0x3e00 - 0x3eff */
|
||||
|
||||
|
||||
/* PHY Address (MVGBE_PHYADDR) */
|
||||
|
|
@ -164,8 +258,11 @@
|
|||
|
||||
/* Ethernet Unit Control (MVGBE_EUC) */
|
||||
#define MVGBE_EUC_PORT0DPPAR (1 << 0)
|
||||
#define MVGBE_EUC_POLLING (1 << 1)
|
||||
#define MVGBE_EUC_TOPDPPAR (1 << 3)
|
||||
#define MVGBE_EUC_PORT0PW (1 << 16)
|
||||
#define MVGBE_EUC_PORTRESET (1 << 24)
|
||||
#define MVGBE_EUC_RAMSINITIALIZATIONCOMPLETED (1 << 25)
|
||||
|
||||
/* Base Address (MVGBE_BASEADDR) */
|
||||
#define MVGBE_BASEADDR_TARGET(target) ((target) & 0xf)
|
||||
|
|
@ -195,6 +292,7 @@
|
|||
#define MVGBE_PXC_RBIP (1 << 8)
|
||||
#define MVGBE_PXC_RBARP (1 << 9)
|
||||
#define MVGBE_PXC_AMNOTXES (1 << 12)
|
||||
#define MVGBE_PXC_RBARPF (1 << 13)
|
||||
#define MVGBE_PXC_TCPCAPEN (1 << 14)
|
||||
#define MVGBE_PXC_UDPCAPEN (1 << 15)
|
||||
#define MVGBE_PXC_TCPQ(q) ((q) << 16)
|
||||
|
|
@ -207,6 +305,7 @@
|
|||
|
||||
/* Port Configuration Extend (MVGBE_PXCX) */
|
||||
#define MVGBE_PXCX_SPAN (1 << 1)
|
||||
#define MVGBE_PXCX_TXCRCDIS (1 << 3)
|
||||
|
||||
/* MII Serial Parameters (MVGBE_MIISP) */
|
||||
#define MVGBE_MIISP_JAMLENGTH_12KBIT 0x00000000
|
||||
|
|
@ -282,10 +381,16 @@
|
|||
#define MVGBE_PS_MIISPEED (1 << 5)
|
||||
#define MVGBE_PS_TXINPROG (1 << 7)
|
||||
#define MVGBE_PS_TXFIFOEMP (1 << 10) /* FIFO Empty */
|
||||
#define MVGBE_PS_RXFIFOEMPTY (1 << 16)
|
||||
/* Armada XP */
|
||||
#define MVGBE_PS_TXINPROG_MASK (0xff << 0)
|
||||
#define MVGBE_PS_TXINPROG_(q) (1 << ((q) + 0))
|
||||
#define MVGBE_PS_TXFIFOEMP_MASK (0xff << 8)
|
||||
#define MVGBE_PS_TXFIFOEMP_(q) (1 << ((q) + 8))
|
||||
|
||||
/* Transmit Queue Command (MVGBE_TQC) */
|
||||
#define MVGBE_TQC_ENQ (1 << 0) /* Enable Q */
|
||||
#define MVGBE_TQC_DISQ (1 << 8) /* Disable Q */
|
||||
#define MVGBE_TQC_ENQ(q) (1 << ((q) + 0))/* Enable Q */
|
||||
#define MVGBE_TQC_DISQ(q) (1 << ((q) + 8))/* Disable Q */
|
||||
|
||||
/* Port Serial Control 1 (MVGBE_PSC1) */
|
||||
#define MVGBE_PSC1_PCSLB (1 << 1)
|
||||
|
|
@ -300,17 +405,23 @@
|
|||
#define MVGBE_IC_RXERROR (1 << 10)
|
||||
#define MVGBE_IC_RXERRQ_MASK (0xff << 11)
|
||||
#define MVGBE_IC_RXERRQ(q) (1 << ((q) + 11))
|
||||
#define MVGBE_IC_TXEND (1 << 19)
|
||||
#define MVGBE_IC_TXEND(q) (1 << ((q) + 19))
|
||||
#define MVGBE_IC_ETHERINTSUM (1 << 31)
|
||||
|
||||
/* Port Interrupt Cause Extend (MVGBE_ICE) */
|
||||
#define MVGBE_ICE_TXBUF (1 << 0)
|
||||
#define MVGBE_ICE_TXERR (1 << 8)
|
||||
#define MVGBE_ICE_TXBUF_MASK (0xff << + 0)
|
||||
#define MVGBE_ICE_TXBUF(q) (1 << ((q) + 0))
|
||||
#define MVGBE_ICE_TXERR_MASK (0xff << + 8)
|
||||
#define MVGBE_ICE_TXERR(q) (1 << ((q) + 8))
|
||||
#define MVGBE_ICE_PHYSTC (1 << 16)
|
||||
#define MVGBE_ICE_PTP (1 << 17)
|
||||
#define MVGBE_ICE_RXOVR (1 << 18)
|
||||
#define MVGBE_ICE_TXUDR (1 << 19)
|
||||
#define MVGBE_ICE_LINKCHG (1 << 20)
|
||||
#define MVGBE_ICE_SERDESREALIGN (1 << 21)
|
||||
#define MVGBE_ICE_INTADDRERR (1 << 23)
|
||||
#define MVGBE_ICE_SYNCCHANGED (1 << 24)
|
||||
#define MVGBE_ICE_PRBSERROR (1 << 25)
|
||||
#define MVGBE_ICE_ETHERINTSUM (1 << 31)
|
||||
|
||||
/* Port Tx FIFO Urgent Threshold (MVGBE_PTFUT) */
|
||||
|
|
@ -342,6 +453,293 @@
|
|||
#define MVGBE_DF_QUEUE_MASK ((7) << 1)
|
||||
|
||||
|
||||
/* Port Acceleration Mode (MVGBE_PACC) */
|
||||
#define MVGVE_PACC_ACCELERATIONMODE_MASK 0x7
|
||||
#define MVGVE_PACC_ACCELERATIONMODE_BM 0x0 /* Basic Mode */
|
||||
#define MVGVE_PACC_ACCELERATIONMODE_EDM 0x1 /* Enhanced Desc Mode */
|
||||
#define MVGVE_PACC_ACCELERATIONMODE_EDMBM 0x2 /* with BM */
|
||||
#define MVGVE_PACC_ACCELERATIONMODE_EDMPNC 0x3 /* with PnC */
|
||||
#define MVGVE_PACC_ACCELERATIONMODE_EDMBPMNC 0x4 /* with BM & PnC */
|
||||
|
||||
/* Port BM Address (MVGBE_PBMADDR) */
|
||||
#define MVGBE_PBMADDR_BMADDRESS_MASK 0xfffff800
|
||||
|
||||
/* Ether Type Priority (MVGBE_ETP) */
|
||||
#define MVGBE_ETP_ETHERTYPEPRIEN (1 << 0) /* EtherType Prio Ena */
|
||||
#define MVGBE_ETP_ETHERTYPEPRIFRSTEN (1 << 1)
|
||||
#define MVGBE_ETP_ETHERTYPEPRIQ (0x7 << 2) /*EtherType Prio Queue*/
|
||||
#define MVGBE_ETP_ETHERTYPEPRIVAL (0xffff << 5) /*EtherType Prio Value*/
|
||||
#define MVGBE_ETP_FORCEUNICSTHIT (1 << 21) /* Force Unicast hit */
|
||||
|
||||
/* RX Hardware Forwarding (0_1, 2_3,..., 8_9) (MVGBE_RXHWFWD) */
|
||||
#define MVGBE_RXHWFWD_PORT_BASEADDRESS(p, x) xxxxx
|
||||
|
||||
/* RX Hardware Forwarding Pointer (MVGBE_RXHWFWDPTR) */
|
||||
#define MVGBE_RXHWFWDPTR_QUEUENO(q) ((q) << 8) /* Queue Number */
|
||||
#define MVGBE_RXHWFWDPTR_PORTNO(p) ((p) << 11) /* Port Number */
|
||||
|
||||
/* RX Hardware Forwarding Threshold (MVGBE_RXHWFWDTH) */
|
||||
#define MVGBE_RXHWFWDTH_DROPRNDGENBITS(n) (((n) & 0x3ff) << 0)
|
||||
#define MVGBE_RXHWFWDTH_DROPTHRESHOLD(n) (((n) & 0xf) << 16)
|
||||
|
||||
/* RX Control (MVGBE_RXCTRL) */
|
||||
#define MVGBE_RXCTRL_PACKETCOLORSRCSELECT(x) (1 << 0)
|
||||
#define MVGBE_RXCTRL_GEMPORTIDSRCSEL(x) ((x) << 4)
|
||||
#define MVGBE_RXCTRL_TXHWFRWMQSRC(x) (1 << 8)
|
||||
#define MVGBE_RXCTRL_RX_MH_SELECT(x) ((x) << 12)
|
||||
#define MVGBE_RXCTRL_RX_TX_SRC_SELECT (1 << 16)
|
||||
#define MVGBE_RXCTRL_HWFRWDENB (1 << 17)
|
||||
#define MVGBE_RXCTRL_HWFRWDSHORTPOOLID(id) (((id) & 0x3) << 20)
|
||||
#define MVGBE_RXCTRL_HWFRWDLONGPOOLID(id) (((id) & 0x3) << 22)
|
||||
|
||||
/* Port RX queues Configuration (MVGBE_PRXC) */
|
||||
#define MVGBE_PRXC_POOLIDSHORT(i) (((i) & 0x3) << 4)
|
||||
#define MVGBE_PRXC_POOLIDLONG(i) (((i) & 0x3) << 6)
|
||||
#define MVGBE_PRXC_PACKETOFFSET(o) (((o) & 0xf) << 8)
|
||||
#define MVGBE_PRXC_USERPREFETCHCMND0 (1 << 16)
|
||||
|
||||
/* Port RX queues Snoop (MVGBE_PRXSNP) */
|
||||
#define MVGBE_PRXSNP_SNOOPNOOFBYTES(b) (((b) & 0x3fff) << 0)
|
||||
#define MVGBE_PRXSNP_L2DEPOSITNOOFBYTES(b) (((b) & 0x3fff) << 16)
|
||||
|
||||
/* Port RX queues Snoop (MVGBE_PRXSNP) */
|
||||
#define MVGBE_PRXF01_PREFETCHCOMMAND0(c) (((c) & 0xffff) << 0) xxxx
|
||||
#define MVGBE_PRXF01_PREFETCHCOMMAND1(c) (((c) & 0xffff) << 16) xxxx
|
||||
|
||||
/* Port RX queues Descriptors Queue Size (MVGBE_PRXDQS) */
|
||||
#define MVGBE_PRXDQS_DESCRIPTORSQUEUESIZE(s) (((s) & 0x0003fff) << 0)
|
||||
#define MVGBE_PRXDQS_BUFFERSIZE(s) (((s) & 0xfff80000) << 19)
|
||||
|
||||
/* Port RX queues Descriptors Queue Threshold (MVGBE_PRXDQTH) */
|
||||
/* Occupied Descriptors Threshold */
|
||||
#define MVGBE_PRXDQTH_ODT(x) (((x) & 0x3fff) << 0)
|
||||
/* Non Occupied Descriptors Threshold */
|
||||
#define MVGBE_PRXDQTH_NODT(x) (((x) & 0x3fff) << 16)
|
||||
|
||||
/* Port RX queues Status (MVGBE_PRXS) */
|
||||
/* Occupied Descriptors Counter */
|
||||
#define MVGBE_PRXS_ODC(x) (((x) & 0x3fff) << 0)
|
||||
/* Non Occupied Descriptors Counter */
|
||||
#define MVGBE_PRXS_NODC(x) (((x) & 0x3fff) << 16)
|
||||
|
||||
/* Port RX queues Status Update (MVGBE_PRXSU) */
|
||||
#define MVGBE_PRXSU_NOOFPROCESSEDDESCRIPTORS(x) (((x) & 0xff) << 0)
|
||||
#define MVGBE_PRXSU_NOOFNEWDESCRIPTORS(x) (((x) & 0xff) << 16)
|
||||
|
||||
/* Port RX Flow Control (MVGBE_PRXFC) */
|
||||
#define MVGBE_PRXFC_PERPRIOFCGENCONTROL (1 << 0)
|
||||
#define MVGBE_PRXFC_TXPAUSECONTROL (1 << 1)
|
||||
|
||||
/* Port RX_TX Pause (MVGBE_PRXTXP) */
|
||||
#define MVGBE_PRXTXP_TXPAUSE(x) ((x) & 0xff)
|
||||
|
||||
/* Port RX Flow Control Generation (MVGBE_PRXFCG) */
|
||||
#define MVGBE_PRXFCG_PERPRIOFCGENDATA (1 << 0)
|
||||
#define MVGBE_PRXFCG_PERPRIOFCGENQNO(x) (((x) & 0x7) << 4)
|
||||
|
||||
/* Port RX Initialization (MVGBE_PRXINIT) */
|
||||
#define MVGBE_PRXINIT_RXDMAINIT (1 << 0)
|
||||
|
||||
/* TX Number of New Bytes (MVGBE_TXNB) */
|
||||
#define MVGBE_TXNB_NOOFNEWBYTES(b) (((b) & 0xffff) << 0)
|
||||
#define MVGBE_TXNB_PKTQNO(q) (((q) & 0x7) << 28)
|
||||
#define MVGBE_TXNB_PKTCOLOR (1 << 31)
|
||||
|
||||
/* Port TX queues Descriptors Queue Size (MVGBE_PTXDQS) */
|
||||
/* Descriptors Queue Size */
|
||||
#define MVGBE_PTXDQS_DQS(x) (((x) & 0x3fff) << 0)
|
||||
/* Transmitted Buffer Threshold */
|
||||
#define MVGBE_PTXDQS_TBT(x) (((x) & 0x3fff) << 16)
|
||||
|
||||
/* Port TX queues Status (MVGBE_PTXS) */
|
||||
/* Pending Descriptors Counter */
|
||||
#define MVGBE_PTXDQS_PDC(x) (((x) & 0x3fff) << 0)
|
||||
/* Transmitted Buffer Counter */
|
||||
#define MVGBE_PTXS_TBC(x) (((x) & 0x3fff) << 16)
|
||||
|
||||
/* Port TX queues Status Update (MVGBE_PTXSU) */
|
||||
/* Number Of Written Descriptoes */
|
||||
#define MVGBE_PTXSU_NOWD(x) (((x) & 0xff) << 0)
|
||||
/* Number Of Released Buffers */
|
||||
#define MVGBE_PTXSU_NORB(x) (((x) & 0xff) << 16)
|
||||
|
||||
/* TX Transmitted Buffers Counter (MVGBE_TXTBC) */
|
||||
/* Transmitted Buffers Counter */
|
||||
#define MVGBE_TXTBC_TBC(x) (((x) & 0x3fff) << 16)
|
||||
|
||||
/* Port TX Initialization (MVGBE_PTXINIT) */
|
||||
#define MVGBE_PTXINIT_TXDMAINIT (1 << 0)
|
||||
|
||||
/* Marvell Header (MVGBE_MH) */
|
||||
#define MVGBE_MH_MHEN (1 << 0)
|
||||
#define MVGBE_MH_DAPREFIX (0x3 << 1)
|
||||
#define MVGBE_MH_SPID (0xf << 4)
|
||||
#define MVGBE_MH_MHMASK (0x3 << 8)
|
||||
#define MVGBE_MH_MHMASK_8QUEUES (0x0 << 8)
|
||||
#define MVGBE_MH_MHMASK_4QUEUES (0x1 << 8)
|
||||
#define MVGBE_MH_MHMASK_2QUEUES (0x3 << 8)
|
||||
#define MVGBE_MH_DSAEN_MASK (0x3 << 10)
|
||||
#define MVGBE_MH_DSAEN_DISABLE (0x0 << 10)
|
||||
#define MVGBE_MH_DSAEN_NONEXTENDED (0x1 << 10)
|
||||
#define MVGBE_MH_DSAEN_EXTENDED (0x2 << 10)
|
||||
|
||||
/* Port Auto-Negotiation Configuration (MVGBE_PANC) */
|
||||
#define MVGBE_PANC_FORCELINKFAIL (1 << 0)
|
||||
#define MVGBE_PANC_FORCELINKPASS (1 << 1)
|
||||
#define MVGBE_PANC_INBANDANEN (1 << 2)
|
||||
#define MVGBE_PANC_INBANDANBYPASSEN (1 << 3)
|
||||
#define MVGBE_PANC_INBANDRESTARTAN (1 << 4)
|
||||
#define MVGBE_PANC_SETMIISPEED (1 << 5)
|
||||
#define MVGBE_PANC_SETGMIISPEED (1 << 6)
|
||||
#define MVGBE_PANC_ANSPEEDEN (1 << 7)
|
||||
#define MVGBE_PANC_SETFCEN (1 << 8)
|
||||
#define MVGBE_PANC_PAUSEADV (1 << 9)
|
||||
#define MVGBE_PANC_ANFCEN (1 << 11)
|
||||
#define MVGBE_PANC_SETFULLDX (1 << 12)
|
||||
#define MVGBE_PANC_ANDUPLEXEN (1 << 13)
|
||||
#define MVGBE_PANC_RESERVED (1 << 15)
|
||||
|
||||
/* Port MAC Control 0 (MVGBE_PMACC0) */
|
||||
#define MVGBE_PMACC0_PORTEN (1 << 0)
|
||||
#define MVGBE_PMACC0_PORTTYPE (1 << 1)
|
||||
#define MVGBE_PMACC0_FRAMESIZELIMIT(x) ((((x) >> 1) & 0x7ffc) << 2)
|
||||
#define MVGBE_PMACC0_RESERVED (1 << 15)
|
||||
|
||||
/* Port MAC Control 1 (MVGBE_PMACC1) */
|
||||
#define MVGBE_PMACC1_PCSLB (1 << 6)
|
||||
|
||||
/* Port MAC Control 2 (MVGBE_PMACC2) */
|
||||
#define MVGBE_PMACC2_PCSEN (1 << 3)
|
||||
#define MVGBE_PMACC2_RGMIIEN (1 << 4)
|
||||
#define MVGBE_PMACC2_PADDINGDIS (1 << 5)
|
||||
#define MVGBE_PMACC2_PORTMACRESET (1 << 6)
|
||||
#define MVGBE_PMACC2_PRBSCHECKEN (1 << 10)
|
||||
#define MVGBE_PMACC2_PRBSGENEN (1 << 11)
|
||||
#define MVGBE_PMACC2_SDTT_MASK (3 << 12) /* Select Data To Transmit */
|
||||
#define MVGBE_PMACC2_SDTT_RM (0 << 12) /* Regular Mode */
|
||||
#define MVGBE_PMACC2_SDTT_PRBS (1 << 12) /* PRBS Mode */
|
||||
#define MVGBE_PMACC2_SDTT_ZC (2 << 12) /* Zero Constant */
|
||||
#define MVGBE_PMACC2_SDTT_OC (3 << 12) /* One Constant */
|
||||
#define MVGBE_PMACC2_RESERVED (3 << 14)
|
||||
|
||||
/* Port MAC Control 3 (MVGBE_PMACC3) */
|
||||
#define MVGBE_PMACC3_IPG_MASK 0x7f80
|
||||
|
||||
/* Port Interrupt Cause/Mask (MVGBE_PIC_2/MVGBE_PIM_2) */
|
||||
#define MVGBE_PI_2_INTSUM (1 << 0)
|
||||
#define MVGBE_PI_2_LSC (1 << 1) /* LinkStatus Change */
|
||||
#define MVGBE_PI_2_ACOP (1 << 2) /* AnCompleted OnPort */
|
||||
#define MVGBE_PI_2_AOOR (1 << 5) /* AddressOut Of Range */
|
||||
#define MVGBE_PI_2_SSC (1 << 6) /* SyncStatus Change */
|
||||
#define MVGBE_PI_2_PRBSEOP (1 << 7) /* QSGMII PRBS error */
|
||||
#define MVGBE_PI_2_MIBCWA (1 << 15) /* MIB counter wrap around */
|
||||
#define MVGBE_PI_2_QSGMIIPRBSE (1 << 10) /* QSGMII PRBS error */
|
||||
#define MVGBE_PI_2_PCSRXPRLPI (1 << 11) /* PCS Rx path received LPI*/
|
||||
#define MVGBE_PI_2_PCSTXPRLPI (1 << 12) /* PCS Tx path received LPI*/
|
||||
#define MVGBE_PI_2_MACRXPRLPI (1 << 13) /* MAC Rx path received LPI*/
|
||||
#define MVGBE_PI_2_MIBCCD (1 << 14) /* MIB counters copy done */
|
||||
|
||||
/* LPI Control 0 (MVGBE_LPIC0) */
|
||||
#define MVGBE_LPIC0_LILIMIT(x) (((x) & 0xff) << 0)
|
||||
#define MVGBE_LPIC0_TSLIMIT(x) (((x) & 0xff) << 8)
|
||||
|
||||
/* LPI Control 1 (MVGBE_LPIC1) */
|
||||
#define MVGBE_LPIC1_LPIRE (1 << 0) /* LPI request enable */
|
||||
#define MVGBE_LPIC1_LPIRF (1 << 1) /* LPI request force */
|
||||
#define MVGBE_LPIC1_LPIMM (1 << 2) /* LPI manual mode */
|
||||
#define MVGBE_LPIC1_TWLIMIT (((x) & 0xfff) << 4)
|
||||
|
||||
/* LPI Status (MVGBE_LPIS) */
|
||||
#define MVGBE_LPIS_PCSRXPLPIS (1 << 0) /* PCS Rx path LPI status */
|
||||
#define MVGBE_LPIS_PCSTXPLPIS (1 << 1) /* PCS Tx path LPI status */
|
||||
#define MVGBE_LPIS_MACRXPLPIS (1 << 2)/* MAC Rx path LP idle status */
|
||||
#define MVGBE_LPIS_MACTXPLPWS (1 << 3)/* MAC Tx path LP wait status */
|
||||
#define MVGBE_LPIS_MACTXPLPIS (1 << 4)/* MAC Tx path LP idle status */
|
||||
|
||||
/* Port PRBS Status (MVGBE_PPRBSS) */
|
||||
#define MVGBE_PPRBSS_PRBSCHECKLOCKED (1 << 0)
|
||||
#define MVGBE_PPRBSS_PRBSCHECKRDY (1 << 1)
|
||||
|
||||
/* Port Status 0 (MVGBE_PS0) */
|
||||
#define MVGBE_PS0_LINKUP (1 << 0)
|
||||
#define MVGBE_PS0_GMIISPEED (1 << 1)
|
||||
#define MVGBE_PS0_MIISPEED (1 << 2)
|
||||
#define MVGBE_PS0_FULLDX (1 << 3)
|
||||
#define MVGBE_PS0_RXFCEN (1 << 4)
|
||||
#define MVGBE_PS0_TXFCEN (1 << 5)
|
||||
#define MVGBE_PS0_PRP (1 << 6) /* Port Rx Pause */
|
||||
#define MVGBE_PS0_PTP (1 << 7) /* Port Tx Pause */
|
||||
#define MVGBE_PS0_PDP (1 << 8) /*Port is Doing Back-Pressure*/
|
||||
#define MVGBE_PS0_SYNCFAIL10MS (1 << 10)
|
||||
#define MVGBE_PS0_ANDONE (1 << 11)
|
||||
#define MVGBE_PS0_IBANBA (1 << 12) /* InBand AutoNeg BypassAct */
|
||||
#define MVGBE_PS0_SYNCOK (1 << 14)
|
||||
|
||||
/* Port CPUn to Queue (MVGBE_PCP2Q) */
|
||||
#define MVGBE_PCP2Q_RXQAE(q) (1 << ((q) + << 0))/*QueueAccessEnable*/
|
||||
#define MVGBE_PCP2Q_TXQAE(q) (1 << ((q) + << 8))/*QueueAccessEnable*/
|
||||
|
||||
/* Port RX_TX Threshold Interrupt Cause/Mask (MVGBE_PRXTXTIC/MVGBE_PRXTXTIM) */
|
||||
#define MVGBE_PRXTXTI_TBTCQ(q) (1 << ((q) + 0))
|
||||
#define MVGBE_PRXTXTI_RBICTAPQ(q) (1 << ((q) + 8))
|
||||
#define MVGBE_PRXTXTI_RDTAQ(q) (1 << ((q) + 16))
|
||||
#define MVGBE_PRXTXTI_PRXTXICSUMMARY (1 << 29)
|
||||
#define MVGBE_PRXTXTI_PTXERRORSUMMARY (1 << 30)
|
||||
#define MVGBE_PRXTXTI_PMISCICSUMMARY (1 << 31)
|
||||
|
||||
/* Port RX_TX Interrupt Cause/Mask (MVGBE_PRXTXIC/MVGBE_PRXTXIM) */
|
||||
#define MVGBE_PRXTXI_TBRQ(q) (1 << ((q) + 0))
|
||||
#define MVGBE_PRXTXI_RPQ(q) (1 << ((q) + 8))
|
||||
#define MVGBE_PRXTXI_RREQ(q) (1 << ((q) + 16))
|
||||
#define MVGBE_PRXTXI_PRXTXTHICSUMMARY (1 << 29)
|
||||
#define MVGBE_PRXTXI_PTXERRORSUMMARY (1 << 30)
|
||||
#define MVGBE_PRXTXI_PMISCICSUMMARY (1 << 31)
|
||||
|
||||
/* Port Misc Interrupt Cause/Mask (MVGBE_PMIC/MVGBE_PMIM) */
|
||||
#define MVGBE_PMI_PHYSTATUSCHNG (1 << 0)
|
||||
#define MVGBE_PMI_LINKCHANGE (1 << 1)
|
||||
#define MVGBE_PMI_PTP (1 << 4)
|
||||
#define MVGBE_PMI_PME (1 << 6) /* Packet Modification Error */
|
||||
#define MVGBE_PMI_IAE (1 << 7) /* Internal Address Error */
|
||||
#define MVGBE_PMI_RXOVERRUN (1 << 8)
|
||||
#define MVGBE_PMI_RXCRCERROR (1 << 9)
|
||||
#define MVGBE_PMI_RXLARGEPACKET (1 << 10)
|
||||
#define MVGBE_PMI_TXUNDRN (1 << 11)
|
||||
#define MVGBE_PMI_PRBSERROR (1 << 12)
|
||||
#define MVGBE_PMI_SRSE (1 << 14) /* SerdesRealignSyncError */
|
||||
#define MVGBE_PMI_RNBTP(q) (1 << ((q) + 16)) /* RxNoBuffersToPool*/
|
||||
#define MVGBE_PMI_TREQ(q) (1 << ((q) + 24)) /* TxResourceErrorQ */
|
||||
|
||||
/* Port Interrupt Enable (MVGBE_PIE) */
|
||||
#define MVGBE_PIE_RXPKTINTRPTENB(q) (1 << ((q) + 0))
|
||||
#define MVGBE_PIE_TXPKTINTRPTENB(q) (1 << ((q) + 8))
|
||||
|
||||
/* Power and PLL Control (MVGBE_PPLLC) */
|
||||
#define MVGBE_PPLLC_REF_FREF_SEL_MASK (0xf << 0)
|
||||
#define MVGBE_PPLLC_PHY_MODE_MASK (7 << 5)
|
||||
#define MVGBE_PPLLC_PHY_MODE_SATA (0 << 5)
|
||||
#define MVGBE_PPLLC_PHY_MODE_SAS (1 << 5)
|
||||
#define MVGBE_PPLLC_PLL_LOCK (1 << 8)
|
||||
#define MVGBE_PPLLC_PU_DFE (1 << 10)
|
||||
#define MVGBE_PPLLC_PU_TX_INTP (1 << 11)
|
||||
#define MVGBE_PPLLC_PU_TX (1 << 12)
|
||||
#define MVGBE_PPLLC_PU_RX (1 << 13)
|
||||
#define MVGBE_PPLLC_PU_PLL (1 << 14)
|
||||
|
||||
/* Digital Loopback Enable (MVGBE_DLE) */
|
||||
#define MVGBE_DLE_LOCAL_SEL_BITS_MASK (3 << 10)
|
||||
#define MVGBE_DLE_LOCAL_SEL_BITS_10BITS (0 << 10)
|
||||
#define MVGBE_DLE_LOCAL_SEL_BITS_20BITS (1 << 10)
|
||||
#define MVGBE_DLE_LOCAL_SEL_BITS_40BITS (2 << 10)
|
||||
#define MVGBE_DLE_LOCAL_RXPHER_TO_TX_EN (1 << 12)
|
||||
#define MVGBE_DLE_LOCAL_ANA_TX2RX_LPBK_EN (1 << 13)
|
||||
#define MVGBE_DLE_LOCAL_DIG_TX2RX_LPBK_EN (1 << 14)
|
||||
#define MVGBE_DLE_LOCAL_DIG_RX2TX_LPBK_EN (1 << 15)
|
||||
|
||||
/* Reference Clock Select (MVGBE_RCS) */
|
||||
#define MVGBE_RCS_REFCLK_SEL (1 << 10)
|
||||
|
||||
|
||||
/*
|
||||
* Set the chip's packet size limit to 9022.
|
||||
* (ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN)
|
||||
|
|
|
|||
Loading…
Reference in New Issue