First pass at a header file for the NCR 53C96 driver (still under
construction).
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/*
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* Copyright (C) 1994 Allen K. Briggs
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: scsi96reg.h,v 1.1 1994/06/26 13:22:32 briggs Exp $
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*
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*/
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#ifndef _MACHINE_SCSI96REG_H_
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#define _MACHINE_SCSI96REG_H_
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#define NCR96_CTCREG 0x0 /* Current transfer count. R */
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/* 16 bits, LSB first. */
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#define NCR96_STCREG 0x0 /* Short transfer count. W */
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/* 16 bits, LSB first. */
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#define NCR96_FFREG 0x2 /* FIFO register. R/W */
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#define NCR96_CMDREG 0x3 /* Command register. R/W */
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#define NCR96_DMA 0x80 /* This flag means to use DMA mode. */
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/* Initiator Commands */
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#define NCR96_CMD_INFOXFER 0x10 /* Information Transfer. */
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#define NCR96_CMD_ICCS 0x11 /* Initiator Cmd Complete steps. */
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#define NCR96_CMD_MSGACC 0x12 /* Message Accepted. */
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#define NCR96_CMD_TPB 0x18 /* Transfer pad bytes. */
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#define NCR96_CMD_SETATN 0x1A /* Set ATN */
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#define NCR96_CMD_RESETATN 0x1B /* Reset ATN */
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/* Target Commands -- skipped. */
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/* Idle State Commands. */
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#define NCR96_CMD_RESEL 0x40 /* Reselect steps */
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#define NCR96_CMD_SEL 0x41 /* Select without ATN steps */
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#define NCR96_CMD_SELATN 0x42 /* Select with ATN steps */
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#define NCR96_CMD_SELATNS 0x43 /* Select with ATN and stop steps */
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#define NCR96_CMD_ENSEL 0x44 /* Enable selection/reselection */
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#define NCR96_CMD_DISSEL 0x45 /* Disable selection/reselection */
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#define NCR96_CMD_SELATN3 0x46 /* Select with ATN3 */
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/* General Commands. */
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#define NCR96_CMD_NOOP 0x00 /* No Operation */
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#define NCR96_CMD_CLRFIFO 0x01 /* Clear FIFO */
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#define NCR96_CMD_RESETDEV 0x02 /* Reset Device */
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#define NCR96_CMD_RESETBUS 0x03 /* Reset SCSI Bus */
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#define NCR96_STATREG 0x4 /* Status register. R */
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#define NCR96_STAT_INT 0x80 /* Interrupt */
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#define NCR96_STAT_IOE 0x40 /* Illegal Operation Error */
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#define NCR96_STAT_PE 0x20 /* Parity Error */
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#define NCR96_STAT_CTZ 0x10 /* Count To Zero */
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#define NCR96_STAT_GCV 0x08 /* Group Code Valid */
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#define NCR96_STAT_MSG 0x04 /* Message */
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#define NCR96_STAT_CD 0x02 /* Command/Data */
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#define NCR96_STAT_IO 0x01 /* Input/Output */
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#define NCR96_SDIDREG 0x4 /* SCSI Dest. ID register. W */
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#define NCR96_SDID_MASK 0x07 /* Mask for Dest. ID */
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#define NCR96_INSTREG 0x5 /* Interrupt status register. R */
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#define NCR96_ISR_SRST 0x80 /* SCSI Reset */
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#define NCR96_ISR_INVAL 0x40 /* Invalid Command */
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#define NCR96_ISR_DISCONN 0x20 /* Disconnected */
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#define NCR96_ISR_SREQ 0x10 /* Service Request */
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#define NCR96_ISR_SO 0x08 /* Successful Operation */
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#define NCR96_ISR_RESEL 0x04 /* Relected */
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#define NCR96_ISR_SELATN 0x02 /* Selected with ATN */
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#define NCR96_ISR_SEL 0x01 /* Selected */
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#define NCR96_STIMREG 0x5 /* SCSI Timeout register. W */
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#define NCR96_ISREG 0x6 /* Internal state register. R */
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#define NCR96_IS_MASK 0x0f /* Mask for non-reserved fields. */
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#define NCR96_STPREG 0x6 /* Synch. Trans. per. register. W */
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#define NCR96_STP_MASK 0x1f /* Mask for non-reserved fields. */
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#define NCR96_CFISREG 0x7 /* Current FIFO/i.s. register. R */
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#define NCR96_CF_MASK 0x1f /* Mask for current FIFO count. */
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#define NCR96_SOFREG 0x7 /* Synch. Offset register. W */
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#define NCR96_SOF_MASK 0x0f /* Mask for non-reserved fields. */
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#define NCR96_CNTLREG1 0x8 /* Control register one. R/W */
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#define NCR96_C1_ETM 0x80 /* Extended Timing mode */
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#define NCR96_C1_DISR 0x40 /* Disable interrupt on SCSI Reset */
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#define NCR96_C1_PTE 0x20 /* Parity Test Enable */
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#define NCR96_C1_PERE 0x10 /* Parity Error Reporting Enable */
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#define NCR96_C1_STE 0x08 /* Self Test Enable */
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#define NCR96_C1_SCSIID_MSK 0x07 /* Chip SCSI ID Mask */
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#define NCR96_CLKFREG 0x9 /* Clock Factor register. W */
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#define NCR96_CLKF_MASK 0x07 /* Mask for non-reserved fields */
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#define NCR96_FTMREG 0xA /* Forced Test Mode register. W */
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#define NCR96_FTM_MASK 0x07 /* Mask for non-reserved fields */
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#define NCR96_CNTLREG2 0xB /* Control register two. R/W */
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#define NCR96_C2_DAE 0x80 /* Data alignment enable */
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#define NCR96_C2_LSP 0x40 /* Latch SCSI Phase */
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#define NCR96_C2_SBO 0x20 /* Select Byte Order */
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#define NCR96_C2_TSDR 0x10 /* Tri-state DMA request */
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#define NCR96_C2_S2FE 0x08 /* SCSI-2 Features Enable */
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#define NCR96_C2_ACDPE 0x04 /* Abort on Cmd/Data parity error */
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#define NCR96_C2_PGRP 0x02 /* Pass through/gen register parity */
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#define NCR96_C2_PGDP 0x01 /* Pass through/gen data parity */
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#define NCR96_CNTLREG3 0xC /* Control register three. R/W */
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#define NCR96_C3_LBTM 0x04 /* Last byte transfer mode */
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#define NCR96_C3_MDM 0x02 /* Modity DMA mode */
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#define NCR96_C3_BS8 0x01 /* Burst Size 8 */
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#define NCR96_DALREG 0xF /* Data alignment register. W */
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#endif /* _MACHINE_SCSI96REG_H_ */
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