Document the Processor-Dependent Code firmware driver. From OpenBSD.
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mjf
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# $NetBSD: mi,v 1.1125 2009/02/19 00:58:59 jmcneill Exp $
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# $NetBSD: mi,v 1.1126 2009/02/20 13:17:58 mjf Exp $
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#
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# Note: don't delete entries from here - mark them as "obsolete" instead.
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#
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@ -985,6 +985,7 @@
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./usr/share/man/cat4/hp700/lasi.0 man-sys-catman .cat
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./usr/share/man/cat4/hp700/mem.0 man-sys-catman .cat
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./usr/share/man/cat4/hp700/mongoose.0 man-sys-catman .cat
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./usr/share/man/cat4/hp700/pdc.0 man-sys-catman .cat
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./usr/share/man/cat4/hp700/phantomas.0 man-sys-catman .cat
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./usr/share/man/cat4/hp700/wax.0 man-sys-catman .cat
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./usr/share/man/cat4/hpcarm/intro.0 man-sys-catman .cat
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@ -3557,6 +3558,7 @@
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./usr/share/man/html4/hp700/lasi.html man-sys-htmlman html
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./usr/share/man/html4/hp700/mem.html man-sys-htmlman html
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./usr/share/man/html4/hp700/mongoose.html man-sys-htmlman html
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./usr/share/man/html4/hp700/pdc.html man-sys-htmlman html
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./usr/share/man/html4/hp700/phantomas.html man-sys-htmlman html
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./usr/share/man/html4/hp700/wax.html man-sys-htmlman html
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./usr/share/man/html4/hpcarm/intro.html man-sys-htmlman html
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@ -5927,6 +5929,7 @@
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./usr/share/man/man4/hp700/lasi.4 man-sys-man .man
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./usr/share/man/man4/hp700/mem.4 man-sys-man .man
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./usr/share/man/man4/hp700/mongoose.4 man-sys-man .man
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./usr/share/man/man4/hp700/pdc.4 man-sys-man .man
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./usr/share/man/man4/hp700/phantomas.4 man-sys-man .man
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./usr/share/man/man4/hp700/wax.4 man-sys-man .man
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./usr/share/man/man4/hpcarm/intro.4 man-sys-man .man
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# $NetBSD: Makefile,v 1.1 2004/09/22 16:38:26 jkunz Exp $
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# $NetBSD: Makefile,v 1.2 2009/02/20 13:17:58 mjf Exp $
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# from: @(#)Makefile 8.1 (Berkeley) 6/18/93
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MAN= asp.4 cpu.4 dino.4 gsc.4 gsckbc.4 harmony.4 intro.4 io.4 lasi.4 \
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mem.4 mongoose.4 phantomas.4 wax.4
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mem.4 mongoose.4 pdc.4 phantomas.4 wax.4
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USETBL=
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.\" $NetBSD: pdc.4,v 1.1 2009/02/20 13:17:58 mjf Exp $
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.\"
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.\" $OpenBSD: pdc.4,v 1.6 2007/06/01 19:54:10 aanriot Exp $
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.\"
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.\" Copyright (c) 2004 Michael Shalayeff
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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.\" IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
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.\" INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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.\" (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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.\" SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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.\" STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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.\" IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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.\" THE POSSIBILITY OF SUCH DAMAGE.
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.\"
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.Dd $Mdocdate: June 1 2007 $
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.Dt PDC 4 hp700
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.Os
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.Sh NAME
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.Nm pdc
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.Nd Processor-Dependent Code firmware driver
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.Sh SYNOPSIS
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.Cd "pdc0 at mainbus?"
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.Sh DESCRIPTION
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The
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.Nm
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driver provides system console services through the PDC
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and also a means for calling PDC procedures, described later.
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The PDC console is used early in the kernel startup before enough kernel
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subsystems have been initialized to directly use the hardware
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i.e. serial ports, keyboard, and video.
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.Pp
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The PDC version displayed at system boot is relevant to the particular
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system model and is not necessarily comparable to PDC versions
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on other systems.
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.\" TODO page0 description and entry points
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.Sh PDC PROCEDURES
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PDC procedure calls are all made through a single entry point
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and assume normal C language calling conventions, with option
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number in the first argument and the return data address in the
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second, unless indicated otherwise.
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Each call requires at most 7KB of the available stack.
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Here is the list of procedures and options descriptions:
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.Bl -tag -width pdc
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.It Fn pdc "PDC_ADD_VALID" "PDC_ADD_VALID_DFLT" "paddr"
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Perform a read operation attempt at the physical address
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.Ar paddr
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without causing a HPMC, in order to verify that the address is valid
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and there is a device to respond to it.
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The implementation may choose to call the caller's HPMC handler and
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raise error conditions on the bus convertors.
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.It Fn pdc "PDC_ALLOC" "PDC_ALLOC_DFLT" "ptr" "size"
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Allocate static storage for IODC use of
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.Ar size
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bytes and return the address in a word pointed to by the
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.Ar ptr
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argument.
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There is no way of freeing the storage allocated and thus
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care shall be taken to not exhaust the total allocation limit of 32KB.
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.It Fn pdc "PDC_BLOCK_TLB" "PDC_BTLB_DEFAULT" "ptr"
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Get block TLB parameters into the data area pointed to by the
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.Ar ptr
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argument.
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This includes minimal and maximal entry size and number of fixed and
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variable sized entries in the block TLB.
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Fixed entries have size of power of two and are aligned to the size
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where variable entries can have any size and base address both
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aligned to a page.
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.It Xo
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.Fo pdc
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.Fa PDC_BLOCK_TLB
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.Fa PDC_BTLB_INSERT
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.Fa sp
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.Fa va
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.Fa pa
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.Fa len
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.Fa acc
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.Fa slot
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.Fc
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.Xc
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Insert block TLB entry specified by the space ID
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.Ar sp ,
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virtual address
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.Ar va ,
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physical address
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.Ar pa ,
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region length
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.Ar len ,
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access rights
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.Ar acc ,
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into the slot number
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.Ar slot .
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.It Fn pdc "PDC_BLOCK_TLB" "PDC_BTLB_PURGE" "sp" "va" "slot" "len"
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Purge one entry from the block TLB specified by the space ID
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.Ar sp ,
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virtual address
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.Ar va ,
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region length
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.Ar len ,
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from slot number
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.Ar slot .
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.It Fn pdc "PDC_BLOCK_TLB" "PDC_BTLB_PURGE_ALL"
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Purge all entries from the block TLB.
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.\" TODO .It Fn pdc "PDC_BUS_BAD" "PDC_BUS_BAD_DLFT"
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.It Fn pdc "PDC_CACHE" "PDC_CACHE_DFLT" "ptr"
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Retrieve cache and TLB configuration parameters into the data area
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pointed to by the
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.Ar ptr
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argument.
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The format of the data stores is as follows:
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.Bl -column "0x00" "contents" -offset left
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.It Sy "addr" Ta Sy "contents"
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.It "0x00" Ta "I-cache size in bytes"
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.It "0x04" Ta "I-cache configuration"
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.It "0x08" Ta "I-cache base for flushing"
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.It "0x0c" Ta "I-cache stride for flushing"
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.It "0x10" Ta "I-cache count for flushing"
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.It "0x14" Ta "I-cache loop size for flushing"
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.It "0x18" Ta "D-cache size in bytes"
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.It "0x1c" Ta "D-cache configuration"
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.It "0x20" Ta "D-cache base for flushing"
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.It "0x24" Ta "D-cache stride for flushing"
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.It "0x28" Ta "D-cache count for flushing"
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.It "0x2c" Ta "D-cache loop size for flushing"
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.It "0x30" Ta "ITLB size"
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.It "0x34" Ta "ITLB configuration"
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.It "0x38" Ta "ITLB space base for flushing"
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.It "0x3c" Ta "ITLB space stride for flushing"
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.It "0x40" Ta "ITLB space count for flushing"
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.It "0x44" Ta "ITLB address base for flushing"
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.It "0x48" Ta "ITLB address stride for flushing"
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.It "0x4c" Ta "ITLB address count for flushing"
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.It "0x50" Ta "ITLB loop size for flushing"
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.It "0x54" Ta "DTLB size"
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.It "0x58" Ta "DTLB configuration"
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.It "0x5c" Ta "DTLB space base for flushing"
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.It "0x60" Ta "DTLB space stride for flushing"
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.It "0x64" Ta "DTLB space count for flushing"
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.It "0x68" Ta "DTLB address base for flushing"
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.It "0x6c" Ta "DTLB address stride for flushing"
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.It "0x70" Ta "DTLB address count for flushing"
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.It "0x74" Ta "DTLB loop size for flushing"
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.El
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.Pp
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The cache configuration word is formatted as follows:
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.Bl -column "bit" "len" "contents" -offset left
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.It Sy "bit" "len" "contents"
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.It "0" "12" "reserved"
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.It "13" "3" "set 1 if coherent operation supported"
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.It "16" "2" "flush mode: 0 -- fdc & fic; 1 -- fdc; 2 -- fic; 3 -- either"
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.It "18" "1" "write-thru D-cache if set"
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.It "19" "2" "reserved"
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.It "21" "3" "cache line size"
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.It "24" "4" "associativity"
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.It "28" "4" "virtual address alias boundary"
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.El
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.Pp
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.It Fn pdc "PDC_CACHE" "PDC_CACHE_SETCS" "ptr" "i_cst" "d_cst" "it_cst" "dt_cst"
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The second word in each of the
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.Ar i_cst ,
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.Ar d_cst ,
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.Ar it_cst ,
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and
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.Ar dt_cst
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arguments specifies the desired coherency operation for the instructions cache,
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data cache, instructions TLB, and data TLB, respectively.
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The data area pointed to by the
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.Ar ptr
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argument receives the actual coherent operation state
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after an attempted change.
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The CPU does not support the requested operation change
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should the corresponding words not match the arguments upon return.
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The currently supported values are zero for incoherent operation,
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and one for coherent operation.
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.It Fn pdc "PDC_CACHE" "PDC_CACHE_GETSPIDB" "ptr"
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The word pointed to by the
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.Ar ptr
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argument receives a mask of space ID used in hashing for cache tag.
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.It Fn pdc "PDC_CHASSIS" "PDC_CHASSIS_DISP" "display"
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Update the chassis display with data given in the
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.Ar display
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argument.
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The bitfields in the word are as follows:
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.Pp
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.Bl -tag -width 0xfffff -compact
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.It 0xe0000
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Specifies the system state.
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.Bl -tag -width 0xfffff -compact
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.It 0x00000
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off
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.It 0x20000
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fault
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.It 0x40000
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test
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.It 0x60000
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initialize
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.It 0x80000
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shutdown
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.It 0xa0000
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warning
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.It 0xc0000
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run
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.It 0xe0000
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all on
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.El
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.It 0x10000
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Blank the chassis display.
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.It 0x0f000
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This and the other lower three nibbles specify the four hex digits
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to be displayed on the chassis display.
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.El
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.It Fn pdc "PDC_CHASSIS" "PDC_CHASSIS_WARN" "ptr"
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Return the warnings from the chassis fans, temperature sensors,
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batteries and power supplies.
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A word of data is returned in the area pointed by the
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.Ar ptr
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argument and is described with bitfields:
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.Pp
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.Bl -tag -width 0xff -compact
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.It 0xff000000
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Zero means none of the redundant chassis components has indicated any failures.
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A non-zero value specifies the failing component.
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.It 0x4
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Indicates the chassis battery charge is low.
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.It 0x2
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The chassis temperature has exceeded the low threshold.
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.It 0x1
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The chassis temperature has exceeded the middle threshold.
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.El
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.It Fn pdc "PDC_CHASSIS" "PDC_CHASSIS_ALL" "ptr" "display"
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Both retrieves the chassis warnings into the word pointed by the
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.Ar ptr
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argument and sets the chassis display using data in the
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.Ar display
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argument.
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.\" TODO .It Fn pdc "PDC_CONF" "PDC_CONFIG_DECONF" "ptr" "hpa"
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.\" TODO .It Fn pdc "PDC_CONF" "PDC_CONFIG_RECONF" "ptr" "hpa"
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.\" TODO .It Fn pdc "PDC_CONF" "PDC_CONFIG_INFO" "ptr" "hpa"
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.It Fn pdc "PDC_COPROC" "PDC_COPROC_DFLT" "ptr"
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Identify the coprocessors attached to the CPU.
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The
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.Ar ptr
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points to a memory location where data is to be stored.
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The first word provides a mask for functional coprocessors and
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the second word is the mask for all present coprocessors.
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.It Fn pdc "PDC_DEBUG" "PDC_DEBUG_DFLT" "ptr"
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Retrieve address of the PDC debugger placed in to the word
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pointed to by the
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.Ar ptr
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argument.
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.\" TODO .It Fn pdc "PDC_INSTR" "PDC_INSTR_DFLT"
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.It Fn pdc "PDC_IODC" "PDC_IODC_READ" "ptr" "hpa" "entry" "addr" "count"
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Given a module
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.Ar hpa ,
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retrieve the specified
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.Ar entry
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from the module's IODC into a memory area at
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.Ar adr
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of
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.Ar count
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bytes long at most.
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The
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.Ar entry
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index is a one-byte index, with a value of zero being a special case.
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For the 0th entry, an IODC header of 16 bytes is returned instead
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of an actual code.
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.It Fn pdc "PDC_IODC" "PDC_IODC_NINIT" "ptr" "hpa" "spa"
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Non-destructively initialize the memory module specified by the
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.Ar hpa
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and
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.Ar spa
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arguments and return the module status after the init in the first word
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pointed to by the
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.Ar ptr
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argument, followed by the SPA space size and an amount of
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available memory bytes in the subsequent two words.
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.It Fn pdc "PDC_IODC" "PDC_IODC_DINIT" "ptr" "hpa" "spa"
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Same as
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.Nm PDC_IODC_NINIT
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except a destructive memory test is performed.
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.It Fn pdc "PDC_IODC" "PDC_IODC_MEMERR" "ptr" "hpa" "spa"
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For the memory module that is specified by
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.Ar hpa
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and
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.Ar spa ,
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return the last most severe error information comprised of copies of
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IO_STATUS, IO_ERR_RESP, IO_ERR_INFO, and IO_ERR_REQ registers placed
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into the data area pointed to by the
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.Ar ptr
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argument, and clear the error status.
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.It Fn pdc "PDC_IODC" "PDC_IODC_IMEMMASTER" "ptr" "hpa"
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HPA for the primary memory module is returned in a word pointed to by the
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.Ar ptr
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argument for a memory module specified by
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.Ar hpa
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if it's configured as a slave module in an interleave group.
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.It Fn pdc "PDC_LAN_STATION_ID" "PDC_LAN_STATION_ID_READ" "macptr" "hpa"
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Retrieve the MAC address for the device at
|
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.Ar hpa
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into the data area pointed to by the
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.Ar macptr
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argument.
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.\" TODO .It Fn pdc "PDC_MEM" "PDC_MEM_INFO" "ptr"
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.\" TODO .It Fn pdc "PDC_MEM" "PDC_MEM_ADD" "ptr" "PDT"
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.\" TODO .It Fn pdc "PDC_MEM" "PDC_MEM_CLR" "ptr"
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.\" TODO .It Fn pdc "PDC_MEM" "PDC_MEM_READ" "ptr" "PDT"
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.\" TODO .It Fn pdc "PDC_MEM" "PDC_MEM_RSTCLR" "ptr"
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.\" TODO .It Fn pdc "PDC_MEM" "PDC_MEM_SETGOOD" "ptr" "good"
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.It Fn pdc "PDC_MEMMAP" "PDC_MEMMAP_HPA." "ptr" "path"
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Returns device HPA in the word pointed to by the
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.Ar ptr
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argument given the device
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.Ar path
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pointer.
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.It Fn pdc "PDC_MODEL" "PDC_MODEL_INFO" "ptr"
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Returns the System model numbers.
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.It Fn pdc "PDC_MODEL" "PDC_MODEL_BOOTID" "boot_id"
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Set BOOT_ID of the processor module (used during boot
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process of monarch selection) to a word given in the
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.Ar boot_id
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argument.
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.It Fn pdc "PDC_MODEL" "PDC_MODEL_COMP" "ptr" "index"
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Retrieve processor component versions by issuing this procedure with
|
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subsequent indexes in the
|
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.Ar index
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argument starting at zero.
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The component version number is stored in the word pointed to by
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the
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.Ar ptr
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argument.
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.It Fn pdc "PDC_MODEL" "PDC_MODEL_MODEL" "ptr" "os_id" "mod_addr"
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Return a string of 80 chars maximum stored at address
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.Ar mod_addr
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and conforming to the OS specified by the
|
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.Ar os_id
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16-bit integer (see
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.Nm PDC_STABLE
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for more information on OS ID).
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A word at the
|
||||
.Ar ptr
|
||||
address receives the result string length.
|
||||
.\" TODO .It Fn pdc "PDC_MODEL" "PDC_MODEL_ENSPEC" "ptr"
|
||||
.\" TODO .It Fn pdc "PDC_MODEL" "PDC_MODEL_DISPEC" "ptr"
|
||||
.It Fn pdc "PDC_MODEL" "PDC_MODEL_CPUID" "ptr"
|
||||
Retrieve CPU model information.
|
||||
A word stored at the address given by the
|
||||
.Ar ptr
|
||||
argument specifies the CPU revision in the lower 5 bits followed by 7 bits
|
||||
of CPU model number.
|
||||
.It Fn pdc "PDC_MODEL" "PDC_MODEL_CPBALITIES" "ptr"
|
||||
Retrieve platform capabilities into the word pointed by the
|
||||
.Ar ptr
|
||||
argument.
|
||||
Bit 0 and 1 specify that a 64- or 32-bit OS is supported, respectively.
|
||||
.It Fn pdc "PDC_MODEL" "PDC_MODEL_GETBOOTOPTS" "ptr"
|
||||
Retrieve the currently enabled, overall supported, and enabled by default
|
||||
boot test masks respectively stored at location pointed to by
|
||||
the
|
||||
.Ar ptr
|
||||
argument.
|
||||
.It Fn pdc "PDC_MODEL" "PDC_MODEL_SETBOOTOPTS" "ptr" "disable" "enable"
|
||||
Disable boot tests specified by mask in the
|
||||
.Ar disable
|
||||
argument and enable
|
||||
boot tests specified by the mask given in the
|
||||
.Ar enable
|
||||
argument.
|
||||
The memory location pointed to by
|
||||
.Ar ptr
|
||||
will contain the resulting masks as returned
|
||||
by the PDC_MODEL_GETBOOTOPTS function.
|
||||
If an attempt is made to enable and disable the same test in one
|
||||
call a PDC_ERR_INVAL will be returned.
|
||||
.It Fn pdc "PDC_NVM" "PDC_NVM_READ" "offset" "ptr" "count"
|
||||
Read contents of the NVM at
|
||||
.Ar offset
|
||||
into the memory area pointed to by the
|
||||
.Ar ptr
|
||||
argument of no more than
|
||||
.Ar count
|
||||
bytes.
|
||||
.Pp
|
||||
The format of the NVM is as follows:
|
||||
.Bl -column "0x0000" "size" "contents" -offset left
|
||||
.It Sy "offset" Ta Sy "size" Ta Sy "contents"
|
||||
.It "0x00" Ta "0x24" Ta "HV dependent"
|
||||
.It "0x24" Ta "0x20" Ta "bootpath"
|
||||
.It "0x44" Ta "0x04" Ta "ISL revision"
|
||||
.It "0x48" Ta "0x04" Ta "timestamp"
|
||||
.It "0x4c" Ta "0x30" Ta "LIF utility entries"
|
||||
.It "0x7c" Ta "0x04" Ta "entry point"
|
||||
.It "0x80" Ta "0x80" Ta "OS panic information"
|
||||
.El
|
||||
.It Fn pdc "PDC_NVM" "PDC_NVM_WRITE" "offset" "ptr" "count"
|
||||
Write data pointed to by the
|
||||
.Ar ptr
|
||||
argument of
|
||||
.Ar count
|
||||
bytes at
|
||||
.Ar address
|
||||
in the NVM.
|
||||
.It Fn pdc "PDC_NVM" "PDC_NVM_SIZE" "ptr"
|
||||
Put the size of Non-Volatile Memory into the word pointed to by the
|
||||
.Ar ptr
|
||||
argument.
|
||||
.It Fn pdc "PDC_NVM" "PDC_NVM_VRFY"
|
||||
Verify that the contents of NVM are valid.
|
||||
.It Fn pdc "PDC_NVM" "PDC_NVM_INIT"
|
||||
Reset the contents of NVM to zeroes without any arguments.
|
||||
.It Fn pdc "PDC_HPA" "PDC_HPA_DFLT" "ptr"
|
||||
The data returned provides the monarch CPUs HPA in the word pointed to by
|
||||
.Ar ptr .
|
||||
.It Fn pdc "PDC_HPA" "PDC_HPA_MODULES" "ptr"
|
||||
Retrieve the bit mask for devices on the CPU bus into the data location
|
||||
pointed to by
|
||||
.Ar ptr .
|
||||
The first word is a bitmask for devices 0-31, and the second is
|
||||
a bitmask for devices 32-63, where bits set to one specify that
|
||||
the corresponding device number is on the same bus as the CPU.
|
||||
.\" TODO .It Fn pdc "PDC_PAT_IO" "PDC_PAT_IO_GET_PCI_RTSZ"
|
||||
.\" TODO .It Fn pdc "PDC_PAT_IO" "PDC_PAT_IO_GET_PCI_RT"
|
||||
.It Fn pdc "PDC_PIM" "PDC_PIM_HPMC" "offset" "ptr" "count"
|
||||
Get HPMC data from
|
||||
.Ar offset
|
||||
in Processor Internal Memory (PIM) into a
|
||||
.Ar ptr
|
||||
memory area of no more than
|
||||
.Ar count
|
||||
bytes in size.
|
||||
Data provided includes (in the order it is copied into the buffer):
|
||||
general registers (r0-r31), control registers (cr0-cr31), space
|
||||
registers (sr0-sr7), IIA space tail, IIA offset tail, check type,
|
||||
CPU state, cache check, TLB check, bus check, assist check, assist
|
||||
state, path info, system responder address, system requestor address,
|
||||
FPU registers (fpr0-fpr31).
|
||||
.It Fn pdc "PDC_PIM" "PDC_PIM_SIZE" "ptr"
|
||||
Return the amount of data available in bytes in the word pointed to by
|
||||
.Ar ptr .
|
||||
.It Fn pdc "PDC_PIM" "PDC_PIM_LPMC" "offset" "ptr" "count"
|
||||
Get LPMC data from
|
||||
.Ar offset
|
||||
in PIM into a
|
||||
.Ar ptr
|
||||
memory area of no more than
|
||||
.Ar count
|
||||
bytes in size.
|
||||
Data provided includes: HV dependent 0x4a words, check type, HV dependent
|
||||
word, cache check, TLB check, bus check, assist check, assist state,
|
||||
path info, system responder address, system requestor address,
|
||||
FPU registers (fpr0-fpr31).
|
||||
.It Fn pdc "PDC_PIM" "PDC_PIM_SBD" "offset" "ptr" "count"
|
||||
Get Soft Boot Data from
|
||||
.Ar offset
|
||||
in PIM into a
|
||||
.Ar ptr
|
||||
memory area of no more than
|
||||
.Ar count
|
||||
bytes in size.
|
||||
Data provided includes: general registers (r0-r31), control registers
|
||||
(cr0-cr31), space registers (sr0-sr7), IIA space tail, IIA offset tail,
|
||||
HV dependent word, CPU state.
|
||||
.It Fn pdc "PDC_PIM" "PDC_PIM_TOC" "offset" "ptr" "count"
|
||||
Get TOC (Transfer Of Control) data from
|
||||
.Ar offset
|
||||
in PIM into a
|
||||
.Ar ptr
|
||||
memory area of no more than
|
||||
.Ar count
|
||||
bytes in size.
|
||||
Data provided includes: general registers (r0-r31), control registers
|
||||
(cr0-cr31), space registers (sr0-sr7), IIA space tail, IIA offset tail,
|
||||
HV dependent word, CPU state.
|
||||
.It Fn pdc "PDC_POW_FAIL" "PDC_POW_FAIL_DFLT"
|
||||
Prepare for power fail.
|
||||
On the machines that provide power failure interrupts, this function is
|
||||
to be called after the operating system has completed
|
||||
.Xr shutdown 8
|
||||
to finish system-dependent tasks and power down.
|
||||
This function only requires 512 bytes of stack.
|
||||
.It Fn pdc "PDC_PROC" "PDC_PROC_STOP"
|
||||
Stop the currently executing processor and also disable bus requestorship,
|
||||
disable interrupts, and exclude the processor from cache coherency protocols.
|
||||
The caller must flush any necessary data from the cache before calling this
|
||||
function.
|
||||
.It Fn pdc "PDC_PROC" "PDC_PROC_RENDEZVOUS"
|
||||
Enter the reset rendezvous code on the current processor.
|
||||
This function is only implemented on category B processors and
|
||||
implementation is optional on category A processors.
|
||||
.It Fn pdc "PDC_PSW" "PDC_PSW_GETMASK" "ptr"
|
||||
Get the mask of default bits implemented into a word pointed to by the
|
||||
.Ar ptr
|
||||
argument.
|
||||
The following mask values are possible:
|
||||
.Pp
|
||||
.Bl -tag -width 100 -compact
|
||||
.It 1
|
||||
Default endianness bit is available.
|
||||
.It 2
|
||||
Default word width bit is available.
|
||||
.El
|
||||
.It Fn pdc "PDC_PSW" "PDC_PSW_DEFAULTS" "ptr"
|
||||
Retrieve the default PSW bits into the word pointed to by the
|
||||
.Ar ptr
|
||||
argument.
|
||||
.It Fn pdc "PDC_PSW" "PDC_PSW_SETDEFAULTS" "bits"
|
||||
Set the default PSW
|
||||
.Ar bits .
|
||||
.It Fn pdc "PDC_SOFT_POWER" "PDC_SOFT_POWER_INFO" "ptr"
|
||||
Retrieve
|
||||
.Dq power
|
||||
register address into the word pointed to by the
|
||||
.Ar ptr
|
||||
argument.
|
||||
Bit-0 in the
|
||||
.Dq power
|
||||
register address being set specifies the power button being depressed.
|
||||
No dampening is required, unlike with the
|
||||
.Xr lasi 4
|
||||
power circuit.
|
||||
.It Fn pdc "PDC_SOFT_POWER" "PDC_SOFT_POWER_ENABLE" "ptr" "stat"
|
||||
Enable (zero
|
||||
.Ar stat )
|
||||
or disable (non-zero
|
||||
.Ar stat )
|
||||
the soft power function,
|
||||
where disable means the machine will turn immediately off
|
||||
should the power get depressed.
|
||||
The
|
||||
.Ar ptr
|
||||
argument still points to the data provided previously
|
||||
by the PDC_SOFT_POWER_INFO call.
|
||||
.It Fn pdc "PDC_STABLE" "PDC_STABLE_READ" "offset" "ptr" "count"
|
||||
Read contents of the
|
||||
.Dq Stable Storage
|
||||
at
|
||||
.Ar offset
|
||||
into the memory area pointed to by the
|
||||
.Ar ptr
|
||||
argument of no more than
|
||||
.Ar count
|
||||
bytes.
|
||||
.Pp
|
||||
The format of the stable storage is as follows:
|
||||
.Bl -column "offset" "0x00" "contents" -offset left
|
||||
.It Sy "offset" "size" "contents"
|
||||
.It "0x0000" "0x20" "primary bootpath"
|
||||
.It "0x0020" "0x20" "reserved"
|
||||
.It "0x0040" "0x02" "OS ID"
|
||||
.It "0x0042" "0x16" "OS dependent"
|
||||
.It "0x0058" "0x02" "diagnostic"
|
||||
.It "0x005a" "0x03" "reserved"
|
||||
.It "0x005d" "0x02" "OS dependent
|
||||
.It "0x005f" "0x01" "fast size"
|
||||
.It "0x0060" "0x20" "console path"
|
||||
.It "0x0080" "0x20" "alternative boot path"
|
||||
.It "0x00a0" "0x20" "keyboard path"
|
||||
.It "0x00c0" "0x20" "reserved"
|
||||
.It "0x00e0" "size" "OS dependent"
|
||||
.El
|
||||
.Pp
|
||||
The
|
||||
.Dq OS ID
|
||||
field may have the following values:
|
||||
.Bl -column "value" "OS" -offset left
|
||||
.It Sy "value" "OS"
|
||||
.It "0x000" "No OS-dependent info"
|
||||
.It "0x001" "HP-UX"
|
||||
.It "0x002" "MPE-iX"
|
||||
.It "0x003" "OSF"
|
||||
.It "0x004" "HP-RT"
|
||||
.It "0x005" "Novell Netware"
|
||||
.El
|
||||
.Pp
|
||||
The
|
||||
.Dq fast size
|
||||
field is the amount of memory to be tested upon system boot
|
||||
and is a power of two multiplier for 256KB.
|
||||
Values of 0xe and 0xf are reserved.
|
||||
.It Fn pdc "PDC_STABLE" "PDC_STABLE_WRITE" "address" "ptr" "count"
|
||||
Write data pointed to by the
|
||||
.Ar ptr
|
||||
argument of
|
||||
.Ar count
|
||||
bytes at
|
||||
.Ar address
|
||||
in the
|
||||
.Dq Stable Storage .
|
||||
.It Fn pdc "PDC_STABLE" "PDC_STABLE_SIZE" "ptr"
|
||||
Put the size of the
|
||||
.Dq Stable Storage
|
||||
into the word pointed to by the
|
||||
.Ar ptr
|
||||
argument.
|
||||
.It Fn pdc "PDC_STABLE" "PDC_STABLE_VRFY" "ptr"
|
||||
Verify that the contents of the
|
||||
.Dq Stable Storage
|
||||
are valid.
|
||||
.It Fn pdc "PDC_STABLE" "PDC_STABLE_INIT" "ptr"
|
||||
Reset the contents of the
|
||||
.Dq Stable Storage
|
||||
to zeroes.
|
||||
.It Fn pdc "PDC_SYSMAP" "PDC_SYSMAP_FIND" "ptr" "path" "number"
|
||||
Map module
|
||||
.Ar number
|
||||
into HPA and also provide an area size starting at HPA and a number of
|
||||
additional addresses placed into the data area pointed to by the
|
||||
.Ar ptr
|
||||
argument words one, two, and three, respectively.
|
||||
The device path is placed into the data area pointed to by the
|
||||
.Ar path
|
||||
argument.
|
||||
.It Fn pdc "PDC_SYSMAP" "PDC_SYSMAP_ADDR" "ptr" "im" "ia"
|
||||
Retrieve a list of additional addresses for the module number
|
||||
.Ar im
|
||||
for the address index
|
||||
.Ar ia .
|
||||
The result is placed into the data area pointed to by
|
||||
.Ar ptr ,
|
||||
where the first word gives the address and the second the size of the area.
|
||||
.It Fn pdc "PDC_SYSMAP" "PDC_SYSMAP_HPA" "ptr" "path_ptr"
|
||||
Map device
|
||||
.Ar path_ptr
|
||||
into device's HPA placed into a word pointed to by the
|
||||
.Ar ptr
|
||||
argument.
|
||||
.It Fn pdc "PDC_TLB" "PDC_TLB_INFO" "ptr"
|
||||
Retrieve the hardware TLB handler parameters.
|
||||
This includes a minimal and maximal size for the page table, in bytes,
|
||||
stored into words zero and one, respectively,
|
||||
in the data area pointed to by the
|
||||
.Ar ptr
|
||||
argument.
|
||||
.It Fn pdc "PDC_TLB" "PDC_TLB_CONFIG" "ptr" "base" "size" "param"
|
||||
Configure the hardware TLB miss handler given the same parameters fetched
|
||||
previously with PDC_TLB_INFO into data area pointed to by the
|
||||
.Ar ptr
|
||||
and page table
|
||||
.Ar base
|
||||
address, page table
|
||||
.Ar size ,
|
||||
and handler parameters
|
||||
.Ar param .
|
||||
The hardware TLB handler parameter bits are as follows:
|
||||
.Pp
|
||||
.Bl -tag -width 0xff -compact
|
||||
.It 1
|
||||
Enable the hardware TLB miss handler.
|
||||
The default is to load cr28 with the faulted page table entry address.
|
||||
.It 4
|
||||
Pointer to the next page table entry is put into cr28.
|
||||
.It 6
|
||||
Next pointer field of the page table entry is put into cr28.
|
||||
.El
|
||||
.Pp
|
||||
Resetting the page table address and/or size without disabling
|
||||
the hardware TLB miss handler is allowed.
|
||||
Any changes made are immediate upon Code or Data virtual
|
||||
address translation bits are set in PSW.
|
||||
.It Fn pdc "PDC_TOD" "PDC_TOD_READ" "ptr"
|
||||
Read the TOD, which is a UNIX Epoch time, into the data area
|
||||
pointed to by the
|
||||
.Ar ptr
|
||||
argument.
|
||||
That includes seconds in the first word and microseconds in
|
||||
the second.
|
||||
.It Fn pdc "PDC_TOD" "PDC_TOD_WRITE" "sec" "usec"
|
||||
Write TOD with UNIX Epoch time with
|
||||
.Ar sec
|
||||
seconds and
|
||||
.Ar usec
|
||||
microseconds.
|
||||
.It Fn pdc "PDC_TOD" "PDC_TOD_ITIMER" "ptr"
|
||||
Get TOD and CPU timer accuracy into the data location pointed to by the
|
||||
.Ar ptr
|
||||
argument.
|
||||
The first two words specify a double floating-point value giving
|
||||
CPU timer frequency.
|
||||
The next two words provide accuracy in parts per billion for the TOD and
|
||||
CPU timer, respectively.
|
||||
.El
|
||||
.Sh FILES
|
||||
.Bl -tag -width /sys/arch/hp700/dev/cpudevs -compact
|
||||
.It machine/pdc.h
|
||||
C header file with relevant definitions.
|
||||
.It /sys/arch/hp700/dev/cpudevs
|
||||
System components' version numbers.
|
||||
.It /dev/console
|
||||
System console device.
|
||||
.El
|
||||
.Sh DIAGNOSTICS
|
||||
Upon successful completion all procedures return zero.
|
||||
The following error codes are returned in case of failures:
|
||||
.Pp
|
||||
.Bl -tag -width PDC_ERR_NOPROC -compact
|
||||
.It PDC_ERR_NOPROC
|
||||
No such procedure
|
||||
.It PDC_ERR_NOPT
|
||||
No such option
|
||||
.It PDC_ERR_COMPL
|
||||
Unable to complete without error
|
||||
.It PDC_ERR_EOD
|
||||
No such device
|
||||
.It PDC_ERR_INVAL
|
||||
Invalid argument
|
||||
.It PDC_ERR_PFAIL
|
||||
Aborted by powerfail
|
||||
.El
|
||||
.Sh SEE ALSO
|
||||
.Xr intro 4 ,
|
||||
.Xr io 4 ,
|
||||
.Xr lasi 4
|
||||
.Rs
|
||||
.%T PA-RISC 1.1 Firmware Architecture Reference Specification
|
||||
.%A Hewlett-Packard
|
||||
.%D March 8, 1999
|
||||
.Re
|
||||
.Rs
|
||||
.%T PA-RISC 2.0 Firmware Architecture Reference Specification
|
||||
.%A Hewlett-Packard
|
||||
.%D March 7, 1999
|
||||
.Re
|
||||
Loading…
Reference in New Issue