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update from SiByte Sample Software version 1.0.26 from:

Browse Source 
http://sibyte.broadcom.com/public/resources/download-request.html?samplesw/samplesw-1.0.26.tar.bz2
This commit is contained in:
cgd 2004-03-11 02:12:24 +00:00
parent dd0b91b507
commit 965d1e331b
15 changed files with 417 additions and 97 deletions
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21
sys/arch/mips/sibyte/include/sb1250_defs.h
View File

@ -8,7 +8,7 @@
*
* SB1250 specification level: User's manual 1/02/02
*
* Author: Mitch Lichtenberg (mpl@broadcom.com)
* Author: Mitch Lichtenberg
*
*********************************************************************
*
@ -113,13 +113,16 @@
* ordering, so be careful when adding support for new minor revs.
********************************************************************* */
#define SIBYTE_HDR_FMASK_1250_ALL 0x00000ff
#define SIBYTE_HDR_FMASK_1250_PASS1 0x0000001
#define SIBYTE_HDR_FMASK_1250_PASS2 0x0000002
#define SIBYTE_HDR_FMASK_1250_ALL 0x000000ff
#define SIBYTE_HDR_FMASK_1250_PASS1 0x00000001
#define SIBYTE_HDR_FMASK_1250_PASS2 0x00000002
#define SIBYTE_HDR_FMASK_1250_PASS3 0x00000004
#define SIBYTE_HDR_FMASK_112x_ALL 0x0000f00
#define SIBYTE_HDR_FMASK_112x_PASS1 0x0000100
#define SIBYTE_HDR_FMASK_112x_PASS3 0x0000200
#define SIBYTE_HDR_FMASK_112x_ALL 0x00000f00
#define SIBYTE_HDR_FMASK_112x_PASS1 0x00000100
#define SIBYTE_HDR_FMASK_1280_ALL 0x0000f000
#define SIBYTE_HDR_FMASK_1280_PASS1 0x00001000
/* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */
#define SIBYTE_HDR_FMASK(chip, pass) \
@ -128,7 +131,7 @@
(SIBYTE_HDR_FMASK_ ## chip ## _ALL)
#define SIBYTE_HDR_FMASK_ALL \
(SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL)
(SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL | SIBYTE_HDR_FMASK_1280_ALL )
#ifndef SIBYTE_HDR_FEATURES
#define SIBYTE_HDR_FEATURES SIBYTE_HDR_FMASK_ALL
@ -250,7 +253,7 @@
*/
#if !defined(__ASSEMBLER__)
#if defined(__mips64) && !defined(__ASSEMBLER__)
#define SBWRITECSR(csr,val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val)
#define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr)))
#endif /* __ASSEMBLER__ */

59
sys/arch/mips/sibyte/include/sb1250_dma.h
View File

@ -7,9 +7,10 @@
* programming the SB1250's DMA controllers, both the data mover
* and the Ethernet DMA.
*
* SB1250 specification level: User's manual 1/02/02
* SB1250 specification level: User's manual 10/21/02
* BCM1280 specification level: User's manual 11/24/03
*
* Author: Mitch Lichtenberg (mpl@broadcom.com)
* Author: Mitch Lichtenberg
*
*********************************************************************
*
@ -81,10 +82,10 @@
#define K_DMA_DESC_TYPE_RING_AL 0
#define K_DMA_DESC_TYPE_CHAIN_AL 1
#if SIBYTE_HDR_FEATURE(112x, PASS3)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1280)
#define K_DMA_DESC_TYPE_RING_UAL_WI 2
#define K_DMA_DESC_TYPE_RING_UAL_RMW 3
#endif
#endif /* 1250 PASS3 || 112x PASS1 || 1280 */
#define M_DMA_EOP_INT_EN _SB_MAKEMASK1(3)
#define M_DMA_HWM_INT_EN _SB_MAKEMASK1(4)
@ -127,11 +128,11 @@
#define M_DMA_NO_DSCR_UPDT _SB_MAKEMASK1(4)
#define M_DMA_L2CA _SB_MAKEMASK1(5)
#if SIBYTE_HDR_FEATURE(112x, PASS3)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1280)
#define M_DMA_RX_XTRA_STATUS _SB_MAKEMASK1(6)
#define M_DMA_TX_CPU_PAUSE _SB_MAKEMASK1(6)
#define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7)
#endif
#endif /* 1250 PASS3 || 112x PASS1 || 1280 */
#define M_DMA_MBZ1 _SB_MAKEMASK(6,15)
@ -181,14 +182,14 @@
#define S_DMA_CURDSCR_COUNT _SB_MAKE64(40)
#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT)
#if SIBYTE_HDR_FEATURE(112x, PASS3)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1280)
#define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56)
#endif
#endif /* 1250 PASS3 || 112x PASS1 || 1280 */
/*
* Receive Packet Drop Registers
*/
#if SIBYTE_HDR_FEATURE(112x, PASS3)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1280)
#define S_DMA_OODLOST_RX _SB_MAKE64(0)
#define M_DMA_OODLOST_RX _SB_MAKEMASK(16,S_DMA_OODLOST_RX)
#define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX)
@ -196,7 +197,7 @@
#define S_DMA_EOP_COUNT_RX _SB_MAKE64(16)
#define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX)
#define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX)
#endif
#endif /* 1250 PASS3 || 112x PASS1 || 1280 */
/* *********************************************************************
* DMA Descriptors
@ -217,21 +218,21 @@
#define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR)
#if SIBYTE_HDR_FEATURE(112x, PASS3)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1280)
#define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0)
#define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA)
#endif
#endif /* 1250 PASS3 || 112x PASS1 || 1280 */
#define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40)
#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE)
#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE)
#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE)
#if SIBYTE_HDR_FEATURE(112x, PASS3)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1280)
#define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40)
#define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT)
#define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT)
#endif
#endif /* 1250 PASS3 || 112x PASS1 || 1280 */
#define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49)
#define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50)
@ -251,12 +252,12 @@
#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS)
#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS)
#if SIBYTE_HDR_FEATURE(112x, PASS3)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1280)
#define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8)
#define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE)
#define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE)
#define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE)
#endif
#endif /* 1250 PASS3 || 112x PASS1 || 1280 */
#define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10)
@ -271,12 +272,12 @@
#define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49)
#if SIBYTE_HDR_FEATURE(112x, PASS3)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1280)
#define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48)
#define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB)
#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB)
#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB)
#endif
#endif /* 1250 PASS3 || 112x PASS1 || 1280 */
#define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50)
#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE)
@ -303,10 +304,10 @@
#define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0)
#endif /* 1250 PASS2 || 112x PASS1 */
#if SIBYTE_HDR_FEATURE(112x, PASS3)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1280)
#define M_DMA_ETH_VLAN_FLAG _SB_MAKEMASK1(1)
#define M_DMA_ETH_CRC_FLAG _SB_MAKEMASK1(2)
#endif
#endif /* 1250 PASS3 || 112x PASS1 || 1280 */
#define S_DMA_ETHRX_RXCH 53
#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH)
@ -454,7 +455,7 @@
M_DM_CUR_DSCR_DSCR_COUNT)
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1280)
/*
* Data Mover Channel Partial Result Registers
* Register: DM_PARTIAL_0
@ -475,10 +476,10 @@
M_DM_PARTIAL_TCPCS_PARTIAL)
#define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48)
#endif /* 112x PASS1 */
#endif /* 1250 PASS3 || 112x PASS1 || 1280 */
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1280)
/*
* Data Mover CRC Definition Registers
* Register: CRC_DEF_0
@ -495,10 +496,10 @@
#define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_POLY)
#define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_POLY,\
M_CRC_DEF_CRC_POLY)
#endif /* 112x PASS1 */
#endif /* 1250 PASS3 || 112x PASS1 || 1280 */
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1280)
/*
* Data Mover CRC/Checksum Definition Registers
* Register: CTCP_DEF_0
@ -527,7 +528,7 @@
#define K_CTCP_DEF_CRC_WIDTH_1 2
#define M_CTCP_DEF_CRC_BIT_ORDER _SB_MAKEMASK1(50)
#endif /* 112x PASS1 */
#endif /* 1250 PASS3 || 112x PASS1 || 1280 */
/*
@ -576,12 +577,12 @@
#define M_DM_DSCRA_L2C_DEST _SB_MAKEMASK1(50)
#define M_DM_DSCRA_L2C_SRC _SB_MAKEMASK1(51)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_DM_DSCRA_RD_BKOFF _SB_MAKEMASK1(52)
#define M_DM_DSCRA_WR_BKOFF _SB_MAKEMASK1(53)
#endif /* 1250 PASS2 || 112x PASS1 */
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1280)
#define M_DM_DSCRA_TCPCS_EN _SB_MAKEMASK1(54)
#define M_DM_DSCRA_TCPCS_RES _SB_MAKEMASK1(55)
#define M_DM_DSCRA_TCPCS_AP _SB_MAKEMASK1(56)
@ -590,7 +591,7 @@
#define M_DM_DSCRA_CRC_AP _SB_MAKEMASK1(59)
#define M_DM_DSCRA_CRC_DFN _SB_MAKEMASK1(60)
#define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61)
#endif /* 112x PASS1 */
#endif /* 1250 PASS3 || 112x PASS1 || 1280 */
#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3,61)

201
sys/arch/mips/sibyte/include/sb1250_genbus.h
View File

@ -6,9 +6,10 @@
* This module contains constants and macros useful for
* manipulating the SB1250's Generic Bus interface
*
* SB1250 specification level: User's manual 1/02/02
* SB1250 specification level: User's manual 10/21/02
* BCM1280 specification level: User's Manual 11/14/03
*
* Author: Mitch Lichtenberg (mpl@broadcom.com)
* Author: Mitch Lichtenberg
*
*********************************************************************
*
@ -112,8 +113,11 @@
#define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */
#define M_IO_BLK_CACHE _SB_MAKEMASK1(15)
/*
* Generic Bus Region 0 Timing Registers (Table 11-7)
* Generic Bus Timing 0 Registers (Table 11-7)
*/
#define S_IO_ALE_WIDTH 0
@ -203,6 +207,124 @@
#define M_IO_COH_ERR _SB_MAKEMASK1(14)
#endif /* 1250 PASS2 || 112x PASS1 */
/*
* Generic Bus Output Drive Control Register 0 (Table 14-18)
*/
#define S_IO_SLEW0 0
#define M_IO_SLEW0 _SB_MAKEMASK(2,S_IO_SLEW0)
#define V_IO_SLEW0(x) _SB_MAKEVALUE(x,S_IO_SLEW0)
#define G_IO_SLEW0(x) _SB_GETVALUE(x,S_IO_SLEW0,M_IO_SLEW0)
#define S_IO_DRV_A 2
#define M_IO_DRV_A _SB_MAKEMASK(2,S_IO_DRV_A)
#define V_IO_DRV_A(x) _SB_MAKEVALUE(x,S_IO_DRV_A)
#define G_IO_DRV_A(x) _SB_GETVALUE(x,S_IO_DRV_A,M_IO_DRV_A)
#define S_IO_DRV_B 6
#define M_IO_DRV_B _SB_MAKEMASK(2,S_IO_DRV_B)
#define V_IO_DRV_B(x) _SB_MAKEVALUE(x,S_IO_DRV_B)
#define G_IO_DRV_B(x) _SB_GETVALUE(x,S_IO_DRV_B,M_IO_DRV_B)
#define S_IO_DRV_C 10
#define M_IO_DRV_C _SB_MAKEMASK(2,S_IO_DRV_C)
#define V_IO_DRV_C(x) _SB_MAKEVALUE(x,S_IO_DRV_C)
#define G_IO_DRV_C(x) _SB_GETVALUE(x,S_IO_DRV_C,M_IO_DRV_C)
#define S_IO_DRV_D 14
#define M_IO_DRV_D _SB_MAKEMASK(2,S_IO_DRV_D)
#define V_IO_DRV_D(x) _SB_MAKEVALUE(x,S_IO_DRV_D)
#define G_IO_DRV_D(x) _SB_GETVALUE(x,S_IO_DRV_D,M_IO_DRV_D)
/*
* Generic Bus Output Drive Control Register 1 (Table 14-19)
*/
#define S_IO_DRV_E 2
#define M_IO_DRV_E _SB_MAKEMASK(2,S_IO_DRV_E)
#define V_IO_DRV_E(x) _SB_MAKEVALUE(x,S_IO_DRV_E)
#define G_IO_DRV_E(x) _SB_GETVALUE(x,S_IO_DRV_E,M_IO_DRV_E)
#define S_IO_DRV_F 6
#define M_IO_DRV_F _SB_MAKEMASK(2,S_IO_DRV_F)
#define V_IO_DRV_F(x) _SB_MAKEVALUE(x,S_IO_DRV_F)
#define G_IO_DRV_F(x) _SB_GETVALUE(x,S_IO_DRV_F,M_IO_DRV_F)
#define S_IO_SLEW1 8
#define M_IO_SLEW1 _SB_MAKEMASK(2,S_IO_SLEW1)
#define V_IO_SLEW1(x) _SB_MAKEVALUE(x,S_IO_SLEW1)
#define G_IO_SLEW1(x) _SB_GETVALUE(x,S_IO_SLEW1,M_IO_SLEW1)
#define S_IO_DRV_G 10
#define M_IO_DRV_G _SB_MAKEMASK(2,S_IO_DRV_G)
#define V_IO_DRV_G(x) _SB_MAKEVALUE(x,S_IO_DRV_G)
#define G_IO_DRV_G(x) _SB_GETVALUE(x,S_IO_DRV_G,M_IO_DRV_G)
#define S_IO_SLEW2 12
#define M_IO_SLEW2 _SB_MAKEMASK(2,S_IO_SLEW2)
#define V_IO_SLEW2(x) _SB_MAKEVALUE(x,S_IO_SLEW2)
#define G_IO_SLEW2(x) _SB_GETVALUE(x,S_IO_SLEW2,M_IO_SLEW2)
#define S_IO_DRV_H 14
#define M_IO_DRV_H _SB_MAKEMASK(2,S_IO_DRV_H)
#define V_IO_DRV_H(x) _SB_MAKEVALUE(x,S_IO_DRV_H)
#define G_IO_DRV_H(x) _SB_GETVALUE(x,S_IO_DRV_H,M_IO_DRV_H)
/*
* Generic Bus Output Drive Control Register 2 (Table 14-20)
*/
#define S_IO_DRV_J 2
#define M_IO_DRV_J _SB_MAKEMASK(2,S_IO_DRV_J)
#define V_IO_DRV_J(x) _SB_MAKEVALUE(x,S_IO_DRV_J)
#define G_IO_DRV_J(x) _SB_GETVALUE(x,S_IO_DRV_J,M_IO_DRV_J)
#define S_IO_DRV_K 6
#define M_IO_DRV_K _SB_MAKEMASK(2,S_IO_DRV_K)
#define V_IO_DRV_K(x) _SB_MAKEVALUE(x,S_IO_DRV_K)
#define G_IO_DRV_K(x) _SB_GETVALUE(x,S_IO_DRV_K,M_IO_DRV_K)
#define S_IO_DRV_L 10
#define M_IO_DRV_L _SB_MAKEMASK(2,S_IO_DRV_L)
#define V_IO_DRV_L(x) _SB_MAKEVALUE(x,S_IO_DRV_L)
#define G_IO_DRV_L(x) _SB_GETVALUE(x,S_IO_DRV_L,M_IO_DRV_L)
#define S_IO_DRV_M 14
#define M_IO_DRV_M _SB_MAKEMASK(2,S_IO_DRV_M)
#define V_IO_DRV_M(x) _SB_MAKEVALUE(x,S_IO_DRV_M)
#define G_IO_DRV_M(x) _SB_GETVALUE(x,S_IO_DRV_M,M_IO_DRV_M)
/*
* Generic Bus Output Drive Control Register 3 (Table 14-21)
*/
#define S_IO_SLEW3 0
#define M_IO_SLEW3 _SB_MAKEMASK(2,S_IO_SLEW3)
#define V_IO_SLEW3(x) _SB_MAKEVALUE(x,S_IO_SLEW3)
#define G_IO_SLEW3(x) _SB_GETVALUE(x,S_IO_SLEW3,M_IO_SLEW3)
#define S_IO_DRV_N 2
#define M_IO_DRV_N _SB_MAKEMASK(2,S_IO_DRV_N)
#define V_IO_DRV_N(x) _SB_MAKEVALUE(x,S_IO_DRV_N)
#define G_IO_DRV_N(x) _SB_GETVALUE(x,S_IO_DRV_N,M_IO_DRV_N)
#define S_IO_DRV_P 6
#define M_IO_DRV_P _SB_MAKEMASK(2,S_IO_DRV_P)
#define V_IO_DRV_P(x) _SB_MAKEVALUE(x,S_IO_DRV_P)
#define G_IO_DRV_P(x) _SB_GETVALUE(x,S_IO_DRV_P,M_IO_DRV_P)
#define S_IO_DRV_Q 10
#define M_IO_DRV_Q _SB_MAKEMASK(2,S_IO_DRV_Q)
#define V_IO_DRV_Q(x) _SB_MAKEVALUE(x,S_IO_DRV_Q)
#define G_IO_DRV_Q(x) _SB_GETVALUE(x,S_IO_DRV_Q,M_IO_DRV_Q)
#define S_IO_DRV_R 14
#define M_IO_DRV_R _SB_MAKEMASK(2,S_IO_DRV_R)
#define V_IO_DRV_R(x) _SB_MAKEVALUE(x,S_IO_DRV_R)
#define G_IO_DRV_R(x) _SB_GETVALUE(x,S_IO_DRV_R,M_IO_DRV_R)
/*
* PCMCIA configuration register (Table 12-6)
*/
@ -218,6 +340,22 @@
#define M_PCMCIA_CFG_RDYMASK _SB_MAKEMASK1(8)
#define M_PCMCIA_CFG_PWRCTL _SB_MAKEMASK1(9)
#if SIBYTE_HDR_FEATURE_CHIP(1280)
#define S_PCMCIA_MODE 16
#define M_PCMCIA_MODE _SB_MAKEMASK(3,S_PCMCIA_MODE)
#define V_PCMCIA_MODE(x) _SB_MAKEVALUE(x,S_PCMCIA_MODE)
#define G_PCMCIA_MODE(x) _SB_GETVALUE(x,S_PCMCIA_MODE,M_PCMCIA_MODE)
#define K_PCMCIA_MODE_PCMA_NOB 0 /* standard PCMCIA "A", no "B" */
#define K_PCMCIA_MODE_IDEA_NOB 1 /* IDE "A", no "B" */
#define K_PCMCIA_MODE_PCMIOA_NOB 2 /* PCMCIA with I/O "A", no "B" */
#define K_PCMCIA_MODE_PCMA_PCMB 4 /* standard PCMCIA "A", standard PCMCIA "B" */
#define K_PCMCIA_MODE_IDEA_PCMB 5 /* IDE "A", standard PCMCIA "B" */
#define K_PCMCIA_MODE_PCMA_IDEB 6 /* standard PCMCIA "A", IDE "B" */
#define K_PCMCIA_MODE_IDEA_IDEB 7 /* IDE "A", IDE "B" */
#endif
/*
* PCMCIA status register (Table 12-7)
*/
@ -288,5 +426,62 @@
#define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE14)
#define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE14,M_GPIO_INTR_TYPE14)
#if SIBYTE_HDR_FEATURE_CHIP(1280)
/*
* GPIO Interrupt Additional Type Register
*/
#define K_GPIO_INTR_BOTHEDGE 0
#define K_GPIO_INTR_RISEEDGE 1
#define K_GPIO_INTR_UNPRED1 2
#define K_GPIO_INTR_UNPRED2 3
#define S_GPIO_INTR_ATYPEX(n) (((n)/2)*2)
#define M_GPIO_INTR_ATYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_ATYPEX(n))
#define V_GPIO_INTR_ATYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPEX(n))
#define G_GPIO_INTR_ATYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPEX(n),M_GPIO_INTR_ATYPEX(n))
#define S_GPIO_INTR_ATYPE0 0
#define M_GPIO_INTR_ATYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE0)
#define V_GPIO_INTR_ATYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE0)
#define G_GPIO_INTR_ATYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE0,M_GPIO_INTR_ATYPE0)
#define S_GPIO_INTR_ATYPE2 2
#define M_GPIO_INTR_ATYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE2)
#define V_GPIO_INTR_ATYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE2)
#define G_GPIO_INTR_ATYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE2,M_GPIO_INTR_ATYPE2)
#define S_GPIO_INTR_ATYPE4 4
#define M_GPIO_INTR_ATYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE4)
#define V_GPIO_INTR_ATYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE4)
#define G_GPIO_INTR_ATYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE4,M_GPIO_INTR_ATYPE4)
#define S_GPIO_INTR_ATYPE6 6
#define M_GPIO_INTR_ATYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE6)
#define V_GPIO_INTR_ATYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE6)
#define G_GPIO_INTR_ATYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE6,M_GPIO_INTR_ATYPE6)
#define S_GPIO_INTR_ATYPE8 8
#define M_GPIO_INTR_ATYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE8)
#define V_GPIO_INTR_ATYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE8)
#define G_GPIO_INTR_ATYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE8,M_GPIO_INTR_ATYPE8)
#define S_GPIO_INTR_ATYPE10 10
#define M_GPIO_INTR_ATYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE10)
#define V_GPIO_INTR_ATYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE10)
#define G_GPIO_INTR_ATYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE10,M_GPIO_INTR_ATYPE10)
#define S_GPIO_INTR_ATYPE12 12
#define M_GPIO_INTR_ATYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE12)
#define V_GPIO_INTR_ATYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE12)
#define G_GPIO_INTR_ATYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE12,M_GPIO_INTR_ATYPE12)
#define S_GPIO_INTR_ATYPE14 14
#define M_GPIO_INTR_ATYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE14)
#define V_GPIO_INTR_ATYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE14)
#define G_GPIO_INTR_ATYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE14,M_GPIO_INTR_ATYPE14)
#endif
#endif

4
sys/arch/mips/sibyte/include/sb1250_int.h
View File

@ -8,7 +8,7 @@
*
* SB1250 specification level: User's manual 1/02/02
*
* Author: Mitch Lichtenberg (mpl@broadcom.com)
* Author: Mitch Lichtenberg
*
*********************************************************************
*
@ -63,6 +63,8 @@
* First, the interrupt numbers.
*/
#define K_INT_SOURCES 64
#define K_INT_WATCHDOG_TIMER_0 0
#define K_INT_WATCHDOG_TIMER_1 1
#define K_INT_TIMER_0 2

6
sys/arch/mips/sibyte/include/sb1250_l2c.h
View File

@ -8,7 +8,7 @@
*
* SB1250 specification level: User's manual 1/02/02
*
* Author: Mitch Lichtenberg (mpl@broadcom.com)
* Author: Mitch Lichtenberg
*
*********************************************************************
*
@ -119,7 +119,7 @@
#define L2C_NUM_WAYS 4
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
/*
* L2 Read Misc. register (A_L2_READ_MISC)
*/
@ -138,7 +138,7 @@
#define M_L2C_MISC_SCACHE_DISABLE_B _SB_MAKEMASK1(2)
#define M_L2C_MISC_SCACHE_DISABLE_R _SB_MAKEMASK1(1)
#define M_L2C_MISC_SCACHE_DISABLE_L _SB_MAKEMASK1(0)
#endif /* 112x PASS1 */
#endif /* 1250 PASS3 || 112x PASS1 */
#endif

2
sys/arch/mips/sibyte/include/sb1250_ldt.h
View File

@ -8,7 +8,7 @@
*
* SB1250 specification level: User's manual 1/02/02
*
* Author: Mitch Lichtenberg (mpl@broadcom.com)
* Author: Mitch Lichtenberg
*
*********************************************************************
*

39
sys/arch/mips/sibyte/include/sb1250_mac.h
View File

@ -8,7 +8,7 @@
*
* SB1250 specification level: User's manual 1/02/02
*
* Author: Mitch Lichtenberg (mpl@broadcom.com)
* Author: Mitch Lichtenberg
*
*********************************************************************
*
@ -97,7 +97,10 @@
#define M_MAC_RESERVED1 _SB_MAKEMASK(8,9)
#define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17)
#define M_MAC_RESERVED2 _SB_MAKEMASK1(18)
#if SIBYTE_HDR_FEATURE_CHIP(1280)
#define M_MAC_TIMESTAMP _SB_MAKEMASK1(18)
#endif
#define M_MAC_DRP_ERRPKT_EN _SB_MAKEMASK1(19)
#define M_MAC_DRP_FCSERRPKT_EN _SB_MAKEMASK1(20)
#define M_MAC_DRP_CODEERRPKT_EN _SB_MAKEMASK1(21)
@ -148,9 +151,9 @@
#define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44)
#endif /* 1250 PASS2 || 112x PASS1 */
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1280)
#define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45)
#endif /* 112x PASS1 */
#endif /* 1250 PASS3 || 112x PASS1 || 1280 */
#define S_MAC_BYPASS_IFG _SB_MAKE64(46)
#define M_MAC_BYPASS_IFG _SB_MAKEMASK(8,S_MAC_BYPASS_IFG)
@ -192,10 +195,22 @@
#define M_MAC_PORT_RESET _SB_MAKEMASK1(8)
#if (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x))
#define M_MAC_RX_ENABLE _SB_MAKEMASK1(10)
#define M_MAC_TX_ENABLE _SB_MAKEMASK1(11)
#define M_MAC_BYP_RX_ENABLE _SB_MAKEMASK1(12)
#define M_MAC_BYP_TX_ENABLE _SB_MAKEMASK1(13)
#endif
/*
* MAC reset information register (1280/1255)
*/
#if SIBYTE_HDR_FEATURE_CHIP(1280)
#define M_MAC_RX_CH0_PAUSE_ON _SB_MAKEMASK1(8)
#define M_MAC_RX_CH1_PAUSE_ON _SB_MAKEMASK1(16)
#define M_MAC_TX_CH0_PAUSE_ON _SB_MAKEMASK1(24)
#define M_MAC_TX_CH1_PAUSE_ON _SB_MAKEMASK1(32)
#endif
/*
* MAC DMA Control Register
@ -283,12 +298,12 @@
#define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x,S_MAC_IFG_RX)
#define G_MAC_IFG_RX(x) _SB_GETVALUE(x,S_MAC_IFG_RX,M_MAC_IFG_RX)
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1280)
#define S_MAC_PRE_LEN _SB_MAKE64(0)
#define M_MAC_PRE_LEN _SB_MAKEMASK(6,S_MAC_PRE_LEN)
#define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x,S_MAC_PRE_LEN)
#define G_MAC_PRE_LEN(x) _SB_GETVALUE(x,S_MAC_PRE_LEN,M_MAC_PRE_LEN)
#endif /* 112x PASS1 */
#endif /* 1250 PASS3 || 112x PASS1 || 1280 */
#define S_MAC_IFG_TX _SB_MAKE64(6)
#define M_MAC_IFG_TX _SB_MAKEMASK(6,S_MAC_IFG_TX)
@ -384,7 +399,7 @@
#define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x,S_MAC_VLAN_TAG)
#define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x,S_MAC_VLAN_TAG,M_MAC_VLAN_TAG)
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define S_MAC_TX_PKT_OFFSET _SB_MAKE64(32)
#define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_TX_PKT_OFFSET)
#define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_PKT_OFFSET)
@ -396,7 +411,7 @@
#define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_CRC_OFFSET,M_MAC_TX_CRC_OFFSET)
#define M_MAC_CH_BASE_FC_EN _SB_MAKEMASK1(48)
#endif /* 112x PASS1 */
#endif /* 1250 PASS3 || 112x PASS1 */
/*
* MAC Status Registers (Table 9-17)
@ -474,9 +489,9 @@
#define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x,S_MAC_COUNTER_ADDR)
#define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x,S_MAC_COUNTER_ADDR,M_MAC_COUNTER_ADDR)
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1280)
#define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52)
#endif /* 112x PASS1 */
#endif /* 1250 PASS3 || 112x PASS1 || 1280 */
/*
* MAC Fifo Pointer Registers (Table 9-19) [Debug register]
@ -610,7 +625,7 @@
#define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_IPHDR_OFFSET)
#define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x,S_MAC_IPHDR_OFFSET,M_MAC_IPHDR_OFFSET)
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1280)
#define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16)
#define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_RX_CRC_OFFSET)
#define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_CRC_OFFSET)
@ -628,7 +643,7 @@
#define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8,S_MAC_RX_CH_MSN_SEL)
#define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_MSN_SEL)
#define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_MSN_SEL,M_MAC_RX_CH_MSN_SEL)
#endif /* 112x PASS1 */
#endif /* 1250 PASS3 || 112x PASS1 || 1280 */
/*
* MAC Receive Channel Select Registers (Table 9-25)

10
sys/arch/mips/sibyte/include/sb1250_mc.h
View File

@ -8,7 +8,7 @@
*
* SB1250 specification level: User's manual 1/02/02
*
* Author: Mitch Lichtenberg (mpl@broadcom.com)
* Author: Mitch Lichtenberg
*
*********************************************************************
*
@ -207,9 +207,9 @@
#define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x,S_MC_ADDR_DRIVE,M_MC_ADDR_DRIVE)
#define V_MC_ADDR_DRIVE_DEFAULT V_MC_ADDR_DRIVE(0x0)
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_MC_REF_DISABLE _SB_MAKEMASK1(30)
#endif /* 112x PASS1 */
#endif /* 1250 PASS3 || 112x PASS1 */
#define M_MC_DLL_BYPASS _SB_MAKEMASK1(31)
@ -311,10 +311,10 @@
#define M_MC_EXTERNALDECODE _SB_MAKEMASK1(35)
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_MC_PRE_ON_A8 _SB_MAKEMASK1(36)
#define M_MC_RAM_WITH_A13 _SB_MAKEMASK1(38)
#endif /* 112x PASS1 */
#endif /* 1250 PASS3 || 112x PASS1 */

2
sys/arch/mips/sibyte/include/sb1250_pci.h
View File

@ -8,7 +8,7 @@
*
* SB1250 specification level: User's manual 1/02/02
*
* Author: Mitch Lichtenberg (mpl@broadcom.com)
* Author: Mitch Lichtenberg
*
*********************************************************************
*

23
sys/arch/mips/sibyte/include/sb1250_regs.h
View File

@ -8,7 +8,7 @@
*
* SB1250 specification level: 01/02/2002
*
* Author: Mitch Lichtenberg (mpl@broadcom.com)
* Author: Mitch Lichtenberg
*
*********************************************************************
*
@ -123,9 +123,9 @@
#define A_L2_READ_TAG 0x0010040018
#define A_L2_ECC_TAG 0x0010040038
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define A_L2_READ_MISC 0x0010040058
#endif /* 112x PASS1 */
#endif /* 1250 PASS3 || 112x PASS1 */
#define A_L2_WAY_DISABLE 0x0010041000
#define A_L2_MAKEDISABLE(x) (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8))
#define A_L2_MGMT_TAG_BASE 0x00D0000000
@ -211,9 +211,9 @@
#define R_MAC_DMA_CUR_DSCRA 0x00000020
#define R_MAC_DMA_CUR_DSCRB 0x00000028
#define R_MAC_DMA_CUR_DSCRADDR 0x00000030
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define R_MAC_DMA_OODPKTLOST_RX 0x00000038 /* rx only */
#endif /* 112x PASS1 */
#endif /* 1250 PASS3 || 112x PASS1 */
/*
* RMON Counters
@ -252,10 +252,10 @@
#define R_MAC_ADFILTER_CFG 0x00000200
#define R_MAC_ETHERNET_ADDR 0x00000208
#define R_MAC_PKT_TYPE 0x00000210
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define R_MAC_ADMASK0 0x00000218
#define R_MAC_ADMASK1 0x00000220
#endif /* 112x PASS1 */
#endif /* 1250 PASS3 || 112x PASS1 */
#define R_MAC_HASH_BASE 0x00000240
#define R_MAC_ADDR_BASE 0x00000280
#define R_MAC_CHLO0_BASE 0x00000300
@ -663,6 +663,7 @@
#define A_SCD_SYSTEM_REVISION 0x0010020000
#define A_SCD_SYSTEM_CFG 0x0010020008
#define A_SCD_SYSTEM_MANUF 0x0010038000
/* *********************************************************************
* System Address Trap Registers
@ -788,16 +789,16 @@
#define R_DM_CUR_DSCR_ADDR 0x0000000010
#define R_DM_DSCR_BASE_DEBUG 0x0000000018
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define A_DM_PARTIAL_0 0x0010020ba0
#define A_DM_PARTIAL_1 0x0010020ba8
#define A_DM_PARTIAL_2 0x0010020bb0
#define A_DM_PARTIAL_3 0x0010020bb8
#define DM_PARTIAL_REGISTER_SPACING 0x8
#define A_DM_PARTIAL(idx) (A_DM_PARTIAL_0 + ((idx) * DM_PARTIAL_REGISTER_SPACING))
#endif /* 112x PASS1 */
#endif /* 1250 PASS3 || 112x PASS1 */
#if SIBYTE_HDR_FEATURE(112x, PASS1)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define A_DM_CRC_0 0x0010020b80
#define A_DM_CRC_1 0x0010020b90
#define DM_CRC_REGISTER_SPACING 0x10
@ -807,7 +808,7 @@
#define R_CRC_DEF_0 0x00
#define R_CTCP_DEF_0 0x08
#endif /* 112x PASS1 */
#endif /* 1250 PASS3 || 112x PASS1 */
/* *********************************************************************
* Physical Address Map

80
sys/arch/mips/sibyte/include/sb1250_scd.h
View File

@ -8,7 +8,7 @@
*
* SB1250 specification level: User's manual 1/02/02
*
* Author: Mitch Lichtenberg (mpl@broadcom.com)
* Author: Mitch Lichtenberg
*
*********************************************************************
*
@ -68,10 +68,14 @@
#define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION)
#if SIBYTE_HDR_FEATURE_CHIP(1250)
#define K_SYS_REVISION_BCM1250_PASS1 1
#define K_SYS_REVISION_BCM1250_PASS2 3
#define K_SYS_REVISION_BCM1250_PASS2_2 16
#define K_SYS_REVISION_BCM1250_PASS3 32
#define K_SYS_REVISION_BCM1250_PASS1 0x01
#define K_SYS_REVISION_BCM1250_PASS2 0x03
#define K_SYS_REVISION_BCM1250_A10 0x0b
#define K_SYS_REVISION_BCM1250_PASS2_2 0x10
#define K_SYS_REVISION_BCM1250_B2 0x11
#define K_SYS_REVISION_BCM1250_PASS3 0x20
#define K_SYS_REVISION_BCM1250_C1 0x21
#define K_SYS_REVISION_BCM1250_C2 0x22
/* XXX: discourage people from using these constants. */
#define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1
@ -81,8 +85,8 @@
#endif /* 1250 */
#if SIBYTE_HDR_FEATURE_CHIP(112x)
#define K_SYS_REVISION_BCM112x_A1 32
#define K_SYS_REVISION_BCM112x_A2 33
#define K_SYS_REVISION_BCM112x_A1 0x20
#define K_SYS_REVISION_BCM112x_A2 0x21
#endif /* 112x */
/* XXX: discourage people from using these constants. */
@ -109,6 +113,8 @@
#define K_SYS_SOC_TYPE_BCM1125 0x3
#define K_SYS_SOC_TYPE_BCM1125H 0x4
#define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */
#define K_SYS_SOC_TYPE_BCM1x80 0x6
#define K_SYS_SOC_TYPE_BCM1x55 0x7
/*
* Calculate correct SOC type given a copy of system revision register.
@ -140,6 +146,43 @@
#define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID)
#define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID)
/* System Manufacturing Register
* Register: SCD_SYSTEM_MANUF
*/
/* Wafer ID: bits 31:0 */
#define S_SYS_WAFERID1_200 _SB_MAKE64(0)
#define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200)
#define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID1_200)
#define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x,S_SYS_WAFERID1_200,M_SYS_WAFERID1_200)
#define S_SYS_BIN _SB_MAKE64(32)
#define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN)
#define V_SYS_BIN _SB_MAKEVALUE(x,S_SYS_BIN)
#define G_SYS_BIN _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN)
/* Wafer ID: bits 39:36 */
#define S_SYS_WAFERID2_200 _SB_MAKE64(36)
#define M_SYS_WAFERID2_200 _SB_MAKEMASK(4,S_SYS_WAFERID2_200)
#define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID2_200)
#define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x,S_SYS_WAFERID2_200,M_SYS_WAFERID2_200)
/* Wafer ID: bits 39:0 */
#define S_SYS_WAFERID_300 _SB_MAKE64(0)
#define M_SYS_WAFERID_300 _SB_MAKEMASK(40,S_SYS_WAFERID_300)
#define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x,S_SYS_WAFERID_300)
#define G_SYS_WAFERID_300(x) _SB_GETVALUE(x,S_SYS_WAFERID_300,M_SYS_WAFERID_300)
#define S_SYS_XPOS _SB_MAKE64(40)
#define M_SYS_XPOS _SB_MAKEMASK(6,S_SYS_XPOS)
#define V_SYS_XPOS(x) _SB_MAKEVALUE(x,S_SYS_XPOS)
#define G_SYS_XPOS(x) _SB_GETVALUE(x,S_SYS_XPOS,M_SYS_XPOS)
#define S_SYS_YPOS _SB_MAKE64(46)
#define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS)
#define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS)
#define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS)
/*
* System Config Register (Table 4-2)
* Register: SCD_SYSTEM_CFG
@ -183,7 +226,7 @@
#define V_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_SYS_CONFIG)
#define G_SYS_CONFIG(x) _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG)
/* The following bits are writable by JTAG only. */
/* The following bits are writeable by JTAG only. */
#define M_SYS_CLKSTOP _SB_MAKEMASK1(32)
#define M_SYS_CLKSTEP _SB_MAKEMASK1(33)
@ -257,7 +300,26 @@
#define S_SCD_WDOG_CNT 0
#define M_SCD_WDOG_CNT _SB_MAKEMASK(23,S_SCD_WDOG_CNT)
#define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(0)
#define S_SCD_WDOG_ENABLE 0
#define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE)
#define S_SCD_WDOG_RESET_TYPE 2
#define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3,S_SCD_WDOG_RESET_TYPE)
#define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x,S_SCD_WDOG_RESET_TYPE)
#define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x,S_SCD_WDOG_RESET_TYPE,M_SCD_WDOG_RESET_TYPE)
#define K_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */
#define K_SCD_WDOG_RESET_SOFT 1
#define K_SCD_WDOG_RESET_CPU0 3
#define K_SCD_WDOG_RESET_CPU1 5
#define K_SCD_WDOG_RESET_BOTH_CPUS 7
/* This feature is present in 1250 C0 and later, but *not* in 112x A revs. */
#if SIBYTE_HDR_FEATURE(1250, PASS3)
#define S_SCD_WDOG_HAS_RESET 8
#define M_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET)
#endif
/*
* Timer Registers (Table 4-11) (Table 4-12) (Table 4-13)

54
sys/arch/mips/sibyte/include/sb1250_smbus.h
View File

@ -6,9 +6,10 @@
* This module contains constants and macros useful for
* manipulating the SB1250's SMbus devices.
*
* SB1250 specification level: 01/02/2002
* SB1250 specification level: 10/21/02
* BCM1280 specification level: 11/24/03
*
* Author: Mitch Lichtenberg (mpl@broadcom.com)
* Author: Mitch Lichtenberg
*
*********************************************************************
*
@ -63,6 +64,7 @@
#define K_SMB_FREQ_400KHZ 0x1F
#define K_SMB_FREQ_100KHZ 0x7D
#define K_SMB_FREQ_10KHZ 1250
#define S_SMB_CMD 0
#define M_SMB_CMD _SB_MAKEMASK(8,S_SMB_CMD)
@ -74,7 +76,11 @@
#define M_SMB_ERR_INTR _SB_MAKEMASK1(0)
#define M_SMB_FINISH_INTR _SB_MAKEMASK1(1)
#define M_SMB_DATA_OUT _SB_MAKEMASK1(4)
#define S_SMB_DATA_OUT 4
#define M_SMB_DATA_OUT _SB_MAKEMASK1(S_SMB_DATA_OUT)
#define V_SMB_DATA_OUT(x) _SB_MAKEVALUE(x,S_SMB_DATA_OUT)
#define M_SMB_DATA_DIR _SB_MAKEMASK1(5)
#define M_SMB_DATA_DIR_OUTPUT M_SMB_DATA_DIR
#define M_SMB_CLK_OUT _SB_MAKEMASK1(6)
@ -87,8 +93,23 @@
#define M_SMB_BUSY _SB_MAKEMASK1(0)
#define M_SMB_ERROR _SB_MAKEMASK1(1)
#define M_SMB_ERROR_TYPE _SB_MAKEMASK1(2)
#define M_SMB_REF _SB_MAKEMASK1(6)
#define M_SMB_DATA_IN _SB_MAKEMASK1(7)
#if SIBYTE_HDR_FEATURE_CHIP(1280) || SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define S_SMB_SCL_IN 5
#define M_SMB_SCL_IN _SB_MAKEMASK1(S_SMB_SCL_IN)
#define V_SMB_SCL_IN(x) _SB_MAKEVALUE(x,S_SMB_SCL_IN)
#define G_SMB_SCL_IN(x) _SB_GETVALUE(x,S_SMB_SCL_IN,M_SMB_SCL_IN)
#endif /* 1280 || 1250 PASS3 || 112x PASS1 */
#define S_SMB_REF 6
#define M_SMB_REF _SB_MAKEMASK1(S_SMB_REF)
#define V_SMB_REF(x) _SB_MAKEVALUE(x,S_SMB_REF)
#define G_SMB_REF(x) _SB_GETVALUE(x,S_SMB_REF,M_SMB_REF)
#define S_SMB_DATA_IN 7
#define M_SMB_DATA_IN _SB_MAKEMASK1(S_SMB_DATA_IN)
#define V_SMB_DATA_IN(x) _SB_MAKEVALUE(x,S_SMB_DATA_IN)
#define G_SMB_DATA_IN(x) _SB_GETVALUE(x,S_SMB_DATA_IN,M_SMB_DATA_IN)
/*
* SMBus Start/Command registers (Table 14-9)
@ -148,7 +169,7 @@
#define V_SPEC_MB(x) _SB_MAKEVALUE(x,S_SPEC_PEC)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#if SIBYTE_HDR_FEATURE_CHIP(1280) || SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define S_SMB_CMDH 8
#define M_SMB_CMDH _SB_MAKEMASK(8,S_SMBH_CMD)
@ -156,8 +177,6 @@
#define M_SMB_EXTEND _SB_MAKEMASK1(14)
#define M_SMB_DIR _SB_MAKEMASK1(13)
#define S_SMB_DFMT 8
#define M_SMB_DFMT _SB_MAKEMASK(3,S_SMB_DFMT)
#define V_SMB_DFMT(x) _SB_MAKEVALUE(x,S_SMB_DFMT)
@ -181,6 +200,23 @@
#define V_SMB_DFMT_CMD5BYTE V_SMB_DFMT(K_SMB_DFMT_CMD5BYTE)
#define V_SMB_DFMT_RESERVED V_SMB_DFMT(K_SMB_DFMT_RESERVED)
#endif /* 1250 PASS2 || 112x PASS1 */
#define S_SMB_AFMT 11
#define M_SMB_AFMT _SB_MAKEMASK(2,S_SMB_AFMT)
#define V_SMB_AFMT(x) _SB_MAKEVALUE(x,S_SMB_AFMT)
#define G_SMB_AFMT(x) _SB_GETVALUE(x,S_SMB_AFMT,M_SMB_AFMT)
#define K_SMB_AFMT_NONE 0
#define K_SMB_AFMT_ADDR 1
#define K_SMB_AFMT_ADDR_CMD1BYTE 2
#define K_SMB_AFMT_ADDR_CMD2BYTE 3
#define V_SMB_AFMT_NONE V_SMB_AFMT(K_SMB_AFMT_NONE)
#define V_SMB_AFMT_ADDR V_SMB_AFMT(K_SMB_AFMT_ADDR)
#define V_SMB_AFMT_ADDR_1BYTE V_SMB_AFMT(K_SMB_AFMT_ADDR_1BYTE)
#define V_SMB_AFMT_ADDR_2BYTE V_SMB_AFMT(K_SMB_AFMT_ADDR_2BYTE)
#define M_SMB_DIR _SB_MAKEMASK1(13)
#endif /* 1280 || 1250 PASS2 || 112x PASS1 */
#endif

2
sys/arch/mips/sibyte/include/sb1250_syncser.h
View File

@ -8,7 +8,7 @@
*
* SB1250 specification level: User's manual 1/02/02
*
* Author: Mitch Lichtenberg (mpl@broadcom.com)
* Author: Mitch Lichtenberg
*
*********************************************************************
*

9
sys/arch/mips/sibyte/include/sb1250_uart.h
View File

@ -8,7 +8,7 @@
*
* SB1250 specification level: User's manual 1/02/02
*
* Author: Mitch Lichtenberg (mpl@broadcom.com)
* Author: Mitch Lichtenberg
*
*********************************************************************
*
@ -256,7 +256,12 @@
*/
#define M_DUART_ISR_TX_A _SB_MAKEMASK1(0)
#define M_DUART_ISR_RX_A _SB_MAKEMASK1(1)
#define S_DUART_ISR_RX_A 1
#define M_DUART_ISR_RX_A _SB_MAKEMASK1(S_DUART_ISR_RX_A)
#define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x,S_DUART_ISR_RX_A)
#define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x,S_DUART_ISR_RX_A,M_DUART_ISR_RX_A)
#define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2)
#define M_DUART_ISR_IN_A _SB_MAKEMASK1(3)
#define M_DUART_ISR_TX_B _SB_MAKEMASK1(4)

2
sys/arch/mips/sibyte/include/sb1250_wid.h
View File

@ -9,7 +9,7 @@
*
* This file describes the WID register layout.
*
* Author: Mitch Lichtenberg (mpl@broadcom.com)
* Author: Mitch Lichtenberg
*
*********************************************************************
*